Datasheet BRT1A16P, BRT1A16NB, BRT1A16G, BRT1A16E, BRR1A16P Datasheet (AGERE)

...

Download

Page 1

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Data Sheet

April 2001

Features

■

Pin equivalent to the general-trade 26LS32 device, with improved speed, reduced power consumption, and significantly lower levels of EMI

■

High input impedance approximately 8 kΩ

■

Four line receivers per package

■

400 Mbits/s maximum data rate when used with Agere Systems Inc. data transmission drivers

■

Meets enhanced small device interface (ESDI) standards

■

4.0 ns maximum propagation delay

■

<0.20 V input sensitivity

■ −1.2 V to +7.2 V common-mode range

■ −40 °C to +125 °C ambient operating temperature

range (wider than the 41 Series)

■

Single 5.0 V ± 10% supply

■

Output defaults to logic 1 when inputs are left open*

■

Available in four package types

■

Lower power requirement than the 41 Series

Description

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. All devices in this family have four receivers with a common enable control. These receivers are pin equivalent to the general-trade 26LS32, but offer increased speed and decreased power consumption. They replace the Agere 41 Series receivers.

* This feature is available on BRF1A and BRF2A.

The BRF1A device is the generic receiver in this family and requires the user to supply external resistors on the circuit board for impedance matching.

The BRF2A is identical to the BRF1A, but has an electrostatic discharge (ESD) protection circuit added to significantly improve the ESD human-body model (HBM) characteristics on the differential input terminals.

The BRS2B is identical to the BRF2A, but has a preferred state feature that places the output in the high state when the inputs are open, shorted to ground, or shorted to the power supply.

The BRR1A is equivalent to the BRF1A, but has a 110 Ω resistor connected across the differential inputs. This eliminates the need for an external resistor when terminating a 100 Ω impedance line. This device is designed to work with the DP1A or PNPA in point-to-point applications.

The BRT1A is equivalent to the BRF1A; however, it is provided with a Y-type resistor network across the differential inputs and terminated to ground. The Y-type termination provides the best EMI results. This device is not recommended for applications where the differences in ground voltage between the driver and the receiver exceed 1 V. This device is designed to work with the DG1A or PNGA in point-topoint applications.

The powerdown loading characteristics of the receiver input circuit are approximately 8 kΩ relative to the power supplies; hence, they will not load the transmission line when the circuit is powered down. For those circuits with termination resistors, the line will remain impedance matched when the circuit is powered down.

The packaging options that are available for these quad differential line drivers include a 16-pin DIP; a 16-pin, J-lead SOJ; a 16-pin, gull-wing small-outline integrated circuit (SOIC); and a 16-pin, narrow-body, gull-wing SOIC.

Page 2

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Pin Information

Data Sheet

April 2001

GND

BRF1A BRF2A BRS2B

Table 1. Enable Truth Table

E1 E2 Condition

00Active 10Active 01Disabled 11Active

GND

BRR1A BRT1A

GND

Figure 1. Quad Differential Receiver Logic Diagrams

12-2281.a(F)

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.

Parameter Symbol Min Max Unit

Power Supply Voltage V Ambient Operating Temperature T Storage Temperature T

stg

—6.5V

−40 125 °C

−40 150 °C

Electrical Characteristics

For electrical characteristics over the temperature range, see Figure 7 through Figure 10.

Table 2. P ower Supply Current Characteristics

See Figure 7 for variati on in I

over the temperature range. T

Parameter Symbol Min Typ Max Unit

Power Supply Current (V

All Outputs Disabled All Outputs Enabled

= 5.5 V):

2 Agere Systems Inc.

= –40 °C to +125 °C, V

 

30 20

= 5 V ± 0.5 V.

45 32

mA mA

Page 3

Data Sheet April 2001

Quad Differential Receivers

BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Electrical Characteristics

(continued)

Table 3. Voltage and Current Characteristics

For variation in minim um V

and maximum VOL over the temperature range, see Figure 8. T

= –40 °C to +125 °C.

Parameter Sym Min Typ Max Unit

Output Voltages, V

Low, I High, I

= 8.0 mA V

= −400 µA V

= 4.5 V:

——0.5V

2.4 — — V

Enable Input Voltages:

Low, V High, V Clamp, V

Differential Input Voltages, V

−0.80 V < V

= 5.5 V V

= 4.5 V, II = –5.0 mA V

IH – VIL

< 7.2 V, −1.2 V < VIL < 6.8 V V Input Offset Voltage V Input Offset Voltage BRS2B V Output Currents, V

Off-state (high Z), V Off-state (high Z), V

= 5.5 V:

= 0.4 V I

= 2.4 V I

Short Circuit I

Enable Currents , V

Low, V High, V

= 0.4 V I

= 2.7 V I

Reverse, V

Differential Input Currents, V

Low, V High, V

= –1.2 V I

= 7.2 V I

= 5.5 V:

= 5.5 V I

= 5.5 V:

TH OFF OFF

OZL OZH OS

IL IH IH

IL IH

1 1

——0.7V

2.0 — — V ——–1.0V

—0.10.20V

 0.02 0.05 V  0.1 0.15 V

——–20µA ——20µA

–25 — –100 mA

— — –400 µA ——20µA ——100µA

——−1.0 mA ——1.0mA

Differential Input Impedance (BRR1A):

Connected Between RI and RI

Differential Input Impedance (BRT1A)

1. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.

2. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recommended that all unused positive inputs be tied to the positive power supply. No external series resistor is required.)

3. Test must be performed one lead at a time to prevent damage to the device.

4. See Figure 2.

— 110 — Ω —60—Ω —90—Ω

R1 R1

12-2819.a(F)

Figure 2. BRT1A Terminating Resistor Configuration

Agere Systems Inc. 3

Page 4

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Timing Characteristics

Data Sheet

April 2001

Table 4. Timing Characteristics

For propagation delays (t

PLH

(See Figure 4 and Figure 5.)

PHL

and t

) over the temperature range, see Figure 9 and Figure 10.

Propagation delay test circuit connected to output is shown in Figure 6.

= –40 °C to +125 °C, V

= 5 V ± 0.5 V.

Parameter Symbol Min Typ Max Unit

Propagation Delay: Input to Output High t Input to Output Low t Disable Time, C

= 5 pF: High-to-high Impedance t Low-to-high Impedance t

PLH PHL

PHZ PLZ

1.5 2.5 4.0 ns

—512ns

—512ns Pulse Width Distortion, ltpHL − tpLHI: Load Capacitance (C Load Capacitance (C

) = 15 pF tskew1 — — 0.7 ns

) = 150 pF tskew1 — — 4.0 ns Output Waveform Skews: Part-to-Part Skew, T Part-to-Part Skew, T

= 75 °C ∆tskew1p-p — 0.8 1.4 ns

= –40 °C to +125 °C ∆tskew1p-p — — 1.5 ns Same Part Skew ∆tskew — — 0.3 ns Enable Time: High Impedance to High t High Impedance to Low t Rise Time (20%—80%) t Fall Time (80%—20%) t

PZH PZL

tLH tHL

—812ns —812ns ——3.0ns ——3.0ns

(ns)

1 0

EXTRINSIC PROPAGATION DELAY, t

Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the

delay due to the external capacitance and the intrinsic delay of the device.

PLH

(TYP)

PHL

(TYP)

25 50 75 100 125 150

LOAD CAPACITANCE, C

(pF)

175 2000

12-3462(F)

Figure 3. T ypical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C

4 Agere Systems Inc.

Page 5

Data Sheet April 2001

Quad Differential Receivers

BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Timing Characteristics

INPUT

OUTPUT

E1*

†

PHZ

(continued)

PHL

80%

20%

tHL

Figure 4. Receiver Propagation Delay Timing

PZH

PLZ

20%

PLH

80%

3.7 V

3.2 V

2.7 V

1.5 V V

tLH

PZL

12-2251.b(F)

3 V

1.5 V 0 V

3 V

1.5 V 0 V

OUTPUT

V = 0.5 V

∆

V = 0.5 V

∆

V = 0.5 V

∆

V = 0.5 V

∆

12-253.b(F)

* E2 = 1 while E1 changes state. †E1 = 0 while E2 changes state.

Figure 5. Receiver Enable and Disable Timing

Test Conditions

Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits.

5 V

Ω

2 k

Ω

12-2249(F)

* Includes probe and jig capacitances. Note: All 458E, IN4148, or equivalent diodes.

TO OUTPUT OF

DEVICE UNDER

TEST

15 pF*

5 k

Figure 6. Receiver Propagation Delay Test Circuit

Agere Systems Inc. 5

Page 6

Quad Differential Receivers

(

)

BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Temperature Characteristics

Data Sheet

April 2001

(mA)

20 18

–50

ICC MAX

= 5.5

ICC TYP

= 5.0

–25 0 25 50 75 100

TEMPERATURE (°C)

125 150

12-3463.a(F)

Figure 7. Typical and Maxim um ICC vs. Temperature

3.8

3.6

3.2

2.8

2.4

2.0

1.6

VOLTAGE (V)

1.2

0.8

0.4

0.0 –25 0 25 50 75 100

–50

Figure 8. Minimum V

Temperature at V

IOH MIN

IOL MAX

TEMPERATURE (°C)

and Maximum V

= 4.5 V

125 150

12-3464.a(F)

vs.

4.00

3.50

N DELAY ATI

PA PR

3.00

2.50

2.00

1.50

1.00 –25 0 25 50 75 100

–50

TEMPERATURE (°C)

MAX

TYP

MIN

125 150

12-3465(F)

Figure 9. Propagation Dela y f or a High Outpu t (t

MAX

TYP

MIN

= 5.0 V

100

125 150–50

12-3466(F)

vs. Temperature at V

4.00

3.50

3.00

2.50

2.00

1.50

PROPAGATION DELAY (ns)

1.00 –25 0 25 50 75

TEMPERATURE (°C)

Figure 10. Propagation Delay for a Low Output

PHL

) vs. Temperature at VCC = 5.0 V

PLH

)

Handling Precautions

CAUTION: This device is susceptible to damage as a result of ESD. Take proper precautions during both

handling and testing. Follow guidelines such as JEDEC Publication No. 108-A (Dec. 1988).

When handling and mounting line driver products, proper precautions should be taken to avoid exposure to ESD. The user should adhere to the following basic rules for ESD control:

1. Assume that all electronic components are sensitive to ESD damage.

2. Never touch a sensitive component unless properly grounded.

3. Never transport, store, or handle sensitive components except in a static-safe environment. 66 Agere Systems Inc.

Page 7

Data Sheet April 2001

Quad Differential Receivers

BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

ESD Failure Models

Agere employs two models for ESD events that can cause device damage or failure:

1. An HBM that is used by most of the industry for ESD-susceptibility testing and pr otec ti on-de si gn evaluation. ESD voltage thresholds are dependent on the critical parameters used to define the model. A standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes.

2. A charged-device model (CDM), which many believe is the better simulator of electronics manufacturing exposure.

Table 5 and Table 6 illustrates the role these two models play in the overall prevention of ESD damage. HBM ESD testing is intended to simulate an ESD event from a charged person. The CDM ESD testing simulates charging and discharging events that occur in production equipment and processes, e.g., an integrated circuit sliding down a shipping tube.

The HBM ESD threshold voltage presented here was obtained by using the following circuit parameters:

Table 5. Typical ESD Thresholds for Data

Transmission Receivers

Device HBM Threshold CDM

Differential

Inputs

BRF1A, BRR1A,

BRT1A

BRF2A, BRS2B >2000 >2000 >2000

Table 6. ESD Damage Protection

Control

Antistatic flooring.

Model

>800 >2000 >1000

ESD Threat Controls

Personnel Processes

Wrist straps.

ESD shoes.

Human body

model (HBM).

Others

Threshold

Static-dissipative

materials.

Air ionization.

Charged-device

model (CDM).

Latch Up

Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if powersupply current exceeds the specified maximum due to the application of a stress to the device under test. A device is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at that level after the stress is removed.

Agere performs latch up testing per an internal test method that is consistent with JEDEC Standard No. 17 (previously JC-40.2)

Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels:

1. dc current stressing of input and output pins.

2. Power supply slew rate.

3. Power supply overvoltage.

Table 7. Latch Up Test Criteria and Test Results

Data Transmission

Receiver ICs

Based on the results in Table 7, the data transmission receivers pass the Agere latch-up esting requirements and are considered not susceptible to latch up.

CMOS Latch Up Standardized Test Procedure

dc Current Stress

of I/O Pins

Minimum Criteria

Test Results

≥150 mA ≤1 µs ≥1.75 x Vmax ≥250 mA ≤100 ns ≥2.25 x Vmax

Power Supply

Slew Rate

Power Supply

Overvoltage

Agere Systems Inc. 7

Page 8

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Data Sheet

April 2001

Power Dissipation

System designers incorporating Agere data transmission drivers in their applications should be aware of package and thermal information associated with these components.

Proper thermal management is essential to the longterm reliability of any plastic encapsulated integrated circuit. Thermal management is especially important for surface-mount devices, given the increasing circuit pack density and resulting higher thermal density. A key aspect of thermal management involves the junction temperature (silicon temperature) of the integrated circuit.

Several factors contribute to the resulting junction temperature of an integrated circuit:

■

Ambient use temperature

■

Device power dissipation

■

Component placement on the board

■

Thermal properties of the board

■

Thermal impedance of the package

Thermal impedance of the package is referred to as

and is measured in °C rise in junction temperature per watt of power dissipation. Thermal impedance is also a function of airflow present in system application.

The following equation can be used to estimate the junction temperature of any device:

The power dissipated in the output is a function of the:

■

Termination scheme on the outputs

■

Termination resistors

■

Duty cycle of the output

Package thermal impedance depends on:

■

Airflow

■

Package type (e.g., DIP, SOIC, SOIC/NB)

The junction temperature can be calculated using the previous equation, after power dissipation levels and package thermal impedances are known.

Figure 11 illustrates the thermal impedance estimates for the various package types as a function of airflow. This figure shows that package thermal impedance is higher for the narrow-body SOIC package. Particular attention should, therefore, be paid to the thermal management issues when using this package type.

In general, system designers should attempt to maintain junction temperature below 125 °C. The following factors should be used to determine if specific data transmission drivers in particular package types meet the system reliability objectives:

■

System ambient temperature

■

Power dissipation

■

Pac kage type

■

Airflow

= TA + PD

where:

is device junction temperature (°C).

is ambient temperature (°C).

is power dissipation (W).

is package thermal impedance (junction to

ambient The power dissipation estimate is derived from two

factors:

■

Internal device power

■

Power associated with output terminations

Multiplying I internal power dissipation.

—

°C/W).

times VCC provides an estimate of

C/W)

(

THERMAL RESISTANCE

140 130

120 110 100

90 80 70 60 50

SOIC/NB

J-LEAD SOIC/GULL WING

DIP

200 400 600 800 1000 12000

AIRFLOW (ft./min.)

12-2753(F)

Figure 11. Power Dissipation

88 Agere Systems Inc.

Page 9

Data Sheet April 2001

Outline Diagrams

16-Pin DIP

Dimensions are in millimeters.

Quad Differential Receivers

BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

PIN #1 IDENTIFIER ZONE

Package

Description

Plastic Dual

In-Line Package

(PDIP3)

SEATING PLANE

0.38 MIN

2.54 TYP

Number of

Pins

(N)

0.58 MAX

Maximum Length

(L)

Package Dimensions

Maximum Width

Without Leads

(B)

Maximum Width Including Leads

(W)

16 20.57 6.48 7.87 5.08

5-4410(F)

Maximum Height

Above Board

(H)

Note: The dimensions in this outline diagram are intended for informational purposes only. F or detailed schematics to assist y our design efforts,

please contact your Agere Systems sales representative.

Agere Systems Inc. 9

Page 10

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Data Sheet

April 2001

Outline Diagrams

(continued)

16-Pin SOIC (SONB/SOG)

Dimensions are in millimeters.

PIN #1 IDENTIFIER ZONE

SEATING PLANE

1.27 TYP

Package

Description

Small-Outline,

0.10

Number of

Pins

(N)

0.51 MAX

Maximum Length

(L)

0.28 MAX

Package Dimensions

Maximum Width

Without Leads

Maximum Width Including Leads

(B)

16 10.11 4.01 6.17 1.73

(W)

0.61

5-4414(F)

Maximum Height

Above Board

(H)

Narrow Body

(SONB)

Small-Outline,

16 10.49 7.62 10.64 2.67

Gull-Wing

(SOG)

Note: The dimensions in this outline diagram are intended for informational purposes only. For det ailed schematics to assist your design efforts,

please contact your Agere Systems sales representative.

10 Agere Systems Inc.

Page 11

Data Sheet April 2001

Quad Differential Receivers

BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Outline Diagrams

(continued)

16-Pin SOIC (SOJ)

Dimensions are in millimeters.

PIN #1 IDENTIFIER ZONE

SEATING PLANE

0.10

1.27 TYP

Package

Description

Small-Outline,

Number of

Pins

(N)

16 10.41 7.62 8.81 3.18

0.51 MAX

Maximum Length

(L)

0.79 MAX

Package Dimensions

Maximum Width

Without Leads

(B)

Maximum Width Including Leads

(W)

5-4413(F)

Maximum Height

Above Board

(H)

J-Lead (SOJ)

Note: The dimensions in this outline diagram are intended for informational purposes only. F or detailed schematics to assist y our design efforts,

please contact your Agere Systems sales representative.

Agere Systems Inc. 11

Page 12

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Data Sheet

April 2001

Ordering Information

Part Number Package Type Comcode Former Pkg. Type Former Part Number

BRF1A16E 16-pin, Plastic SOJ 107949927 1041 LF, MF, LS BRF1A16E-TR Tape & Reel SOJ 107949935 1041 LF, MF, LS BRF1A16G 16-pin, Plastic SOIC 107950297 1141 LF, MF, LS BRF1A16G-TR Tape & Reel SOIC 107950305 1141 LF, MF, LS BRF1A16NB 16-pin, Plastic SOIC/NB 107949968 1241 LF, MF, LS BRF1A16NB-TR Tape & Reel SOIC/NB 107949976 1241 LF, MF, LS BRF1A16P 16-pin, Plastic DIP 107949984 41 LF, MF, LS BRF2A16E 16-pin, Plastic SOJ 107949992 1041 LF2, MF2 BRF2A16E-TR Tape & Reel SOJ 107950008 1041 LF2, MF2 BRF2A16G 16-pin, Plastic SOIC 107950016 1141 LF2, MF2 BRF2A16G-TR Tape & Reel SOIC 107950024 1141 LF2, MF2 BRF2A16NB 16-pin, Plastic SOIC/NB 107950032 1241 LF2, MF2 BRF2A16NB-TR Tape & Reel SOIC/NB 107950040 1241 LF2, MF2 BRF2A16P 16-pin, Plastic DIP 107950057 41 LF2, MF2 BRR1A16E 16-pin, Plastic SOJ 107950065 1041 LR, MR BRR1A16E-TR Tape & Reel SOJ 107950073 1041 LR, MR BRR1A16G 16-pin, Plastic SOIC 107950081 1141 LR, MR BRR1A16G-TR Tape & Reel SOIC 107950099 1141 LR, MR BRR1A16NB 16-pin, Plastic SOIC/NB 107950107 1241 LR, MR BRR1A16NB-TR Tape & Reel SOIC/NB 107950115 1241 LR, MR BRR1A16P 16-pin, Plastic DIP 107950123 41 LR, MR BRS2B16E 16-pin, Plastic SOJ 108888470 1041 MF, MF2, LS BRS2B16E-TR Tape & Reel SOJ 108888488 1041 MF, MF2, LS BRS2B16G 16-pin, Plastic SOIC 108699133 1141 MF, MF2, LS BRS2B16G-TR Tape & Reel SOIC 108699125 1141 MF, MF2, LS BRS2B16P 16-pin, Plastic DIP 108888447 41 MF, MF2, LS BRS2B16NB 16-pin, Plastic SOIC/NB 108888454 1241 MF, MF2, LS BRS2B16NB-TR Tape & Reel SOIC/NB 108888462 1241 MF, MF2, LS BRT1A16E 16-pin, Plastic SOJ 107950131 1041 LT, MT BRT1A16E-TR Tape & Reel SOJ 107950149 1041 LT, MT BRT1A16G 16-pin, Plastic SOIC 107950156 1141 LT, MT BRT1A16G-TR Tape & Reel SOIC 107950164 1141 LT, MT BRT1A16NB 16-pin, Plastic SOIC/NB 107950313 1241 LT, MT BRT1A16NB-TR Tape & Reel SOIC/NB 107950321 1241 LT, MT BRT1A16P 16-pin, Plastic DIP 107950339 41 LT, MT

For additional information, contact your Agere Systems Account Ma na ger or the following: INTERNET: E-MAIL: N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan EUROPE: Data Requests: DATALINE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

April 2001 DS01-069ANET-1 (Replaces DS01-069ANET)

http://www.agere.com docmaster@micro.lucent.com

1-800-372-2447 Tel. (65) 778 8833 Tel. (86) 21 50471212 Tel. (81) 3 5421 1600

Technical Inquiries:GERMANY:

, FAX 610-712-4106 (In CANADA:

, FAX (65) 777 7495

, FAX (86) 21 50472266

, FAX (81) 3 5421 1700

Tel. (44) 7000 582 368

FRANCE:

(39) 02 6608131

ITALY:

(49) 89 95086 0

(33) 1 40 83 68 00

(Milan), SPAIN:

1-800-553-2448

, FAX (44) 1189 328 148

(Munich), UNITED KINGDOM:

(Paris), SWEDEN:

, FAX 610-712-4106)

(46) 8 594 607 00

(34) 1 807 1441

(Madrid)

(44) 1344 865 900

(Stockholm), FINLAND:

(Ascot),

(358) 9 3507670

(Helsinki),