Page 1
bq4017/bq4017Y
2048Kx8 Nonvolatile SRAM
Features
Data retention in the absence of
➤
power
Automatic write-protection dur
➤
ing power-up/power-down cycles
Conventional SRAM operation;
➤
unlimited write cycles
5-year minimum data retention
➤
in absence of power
Battery internally isolated until
➤
power is applied
Pin Connections
36
V
CC
A
35
19
NC
34
A
33
15
A
32
17
31
WE
A
30
13
A
29
8
A
28
9
A
27
11
26
OE
A
25
10
24
CE
DQ
23
22
DQ
DQ
21
20
DQ
19
DQ
DQ
DQ
DQ
V
NC
1
A
2
20
A
3
18
A
4
16
A
5
14
A
6
12
A
7
7
A
8
6
9
A
5
A
10
4
11
A
3
A
12
2
A
13
1
A
14
0
15
0
16
1
17
2
18
SS
General Description
The CMOS bq4017 is a nonvolatile
16,777,216-bit static RAM organized
as 2,097,152 words by 8 bits. The
integral control circuitry and lith
ium energy source provide reliable
nonvolatility coupled with the un
limited write cycles of standard
SRAM.
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When V
falls out of tolerance, the SRAM is
At this time the integral energy
source is switched on to sustain the
memory until after V
returns valid.
CC
The bq4017 uses extremely low
standby current CMOS SRAMs, cou
pled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EE
PROM.
The bq4017 has the same interface
as industry-standard SRAMs and
CC
requires no external circuitry.
-
-
unconditionally write-protected to
prevent an inadvertent write opera
-
tion.
Pin Names
A0–A
DQ
0
CE
OE
WE
V
CC
7
6
5
4
3
V
SS
NC No connect
Address inputs
20
–DQ7Data input/output
Chip enable input
Output enable input
Write enable input
Supply voltage input
Ground
Block Diagram
36-Pin DIP Module
PN401701.eps
Selection Guide
Part
Number
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
Part
Number
Maximum
Access
Time (ns)
bq4017MC -70 70 -5% bq4017YMC -70 70 -10%
5/95
1
Negative
Supply
Tolerance
Page 2
bq4017/bq4017Y
Functional Description
When power is valid, the bq4017 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4017 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
Power-down/power-up control circuitry constantly moni
tors the V
V
. The bq4017 monitors for V
PFD
use in systems with 5% supply tolerance. The bq4017Y
monitors for V
with 10% supply tolerance.
When V
automatically write-protects the data. All outputs be
come high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com
pletion. If the memory cycle fails to terminate within
time t
WPT
supply for a power-fail-detect threshold
CC
= 4.37V typical for use in systems
PFD
falls below the V
CC
= 4.62V typical for
PFD
threshold, the SRAM
PFD
, write-protection takes place.
As V
falls past V
CC
circuitry switches to the internal lithium backup supply,
which provides data retention until valid V
When V
returns to a level above the internal backup
CC
cell voltage, the supply is switched back to V
V
ramps above the V
CC
continues for a time t
processor stabilization. Normal memory operation may
resume after this time.
The internal coin cells used by the bq4017 have an ex
tremely long shelf life. The bq4017 provides data reten
tion for more than 5 years in the absence of system
power.
As shipped from Unitrode, the integral lithium cells are
electrically isolated from the memory. (Self-discharge in
this condition is approximately 0.5% per year.) Follow
ing the first application of V
and the lithium backup provides data retention on sub
sequent power-downs.
and approaches 3V, the control
PFD
is applied.
CC
threshold, write-protection
PFD
(120ms maximum) to allow for
CER
, this isolation is broken,
CC
CC
Truth Table
Mode CE WE OE I/O Operation Power
Not selected H X X High Z Standby
Output disable L H H High Z Active
Read L H L D
Write L L X D
OUT
IN
Active
Active
. After
-
-
-
-
Absolute Maximum Ratings
Symbol Parameter Value Unit Conditions
V
CC
V
T
T
OPR
T
STG
T
BIAS
T
SOLDER
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
DC voltage applied on VCCrelative to V
SS
DC voltage applied on any pin excluding V
relative to V
SS
CC
-0.3 to 7.0 V
-0.3 to 7.0 V
V
+ 0.3
V
≤
T
CC
Operating temperature 0 to +70 °C
Storage temperature -40 to +70 °C
Temperature under bias -10 to +70 °C
Soldering temperature +260 °C For 10 seconds
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con
ditions beyond the operational limits for extended periods of time may affect device reliability.
2
-
Page 3
bq4017/bq4017Y
Recommended DC Operating Conditions (T
= 0 to 70°C)
A
Symbol Parameter Minimum Typical Maximum Unit Notes
V
CC
V
SS
V
IL
V
IH
Supply voltage
Supply voltage 0 0 0 V
Input low voltage -0.3 - 0.8 V
Input high voltage 2.2 - VCC+ 0.3 V
4.5 5.0 5.5 V bq4017Y
4.75 5.0 5.5 V bq4017
Note: Typical values indicate operation at TA= 25°C.
DC Electrical Characteristics (T
= 0 to 70°C, V
A
CCmin
V
CC
V
≤
≤
CCmax
)
Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes
I
I
V
V
I
I
LI
LO
OH
OL
SB1
SB2
Input leakage current - -
Output leakage current - -
Output high voltage 2.4 - - V IOH= -1.0 mA
Output low voltage - - 0.4 V IOL= 2.1 mA
Standby supply current - 7 17 mA CE = V
Standby supply current - 2.5 5 mA
4
±
4
±
AVIN= VSSto V
µ
= VIHor OE = VIHor
CE
A
µ
WE
= V
IL
IH
0V≤V
IN
CE
V
≥
CC
or V
V
≥
IN
0.2V,
≤
- 0.2V,
CC
CC
- 0.2
Min. cycle, duty = 100%,
= VIL,I
I
CC
Operating supply current - 75 115 mA
CE
A19 < V
A20 < V
V
PFD
V
SO
Power-fail-detect voltage
Supply switch-over voltage - 3 - V
4.55 4.62 4.75 V bq4017
4.30 4.37 4.50 V bq4017Y
= 0mA,
I/O
or A19 > VIH,
IL
or A20 > V
IL
IH
Note: Typical values indicate operation at TA= 25°C, VCC= 5V.
3
Page 4
bq4017/bq4017Y
Capacitance (T
= 25°C, F = 1MHz, VCC= 5.0V)
A
Symbol Parameter Minimum Typical Maximum Unit Conditions
C
I/O
C
IN
Input/output capacitance - - 40 pF Output voltage = 0V
Input capacitance - - 40 pF Input voltage = 0V
Note: These parameters are sampled and not 100% tested.
AC Test Conditions
Parameter Test Conditions
Input pulse levels 0V to 3.0V
Input rise and fall times 5 ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2
Figure 1. Output Load A
Read Cycle
Symbol Parameter
t
RC
t
AA
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
(TA= 0 to 70°C, V
CCmin
Read cycle time 70 - ns
Address access time - 70 ns Output load A
Chip enable access time - 70 ns Output load A
Output enable to output valid - 35 ns Output load A
Chip enable to output in low Z 5 - ns Output load B
Output enable to output in low Z 5 - ns Output load B
Chip disable to output in high Z 0 25 ns Output load B
Output disable to output in high Z 0 25 ns Output load B
Output hold from address change 10 - ns Output load A
Figure 2. Output Load B
V
CC
V
≤
≤
CCmax
)
-70
Min. Max.
4
Unit Conditions
Page 5
bq4017/bq4017Y
Read Cycle No. 1 (Address Access)
Read Cycle No. 2 (CE Access)
Read Cycle No. 3 (OE Access)
1,3,4
1,5
1,2
Notes: 1. WE is held high for a read cycle.
2. Device is continuously selected: CE
3. Address is valid prior to or coincident with CE
4. OE
= VIL.
5. Device is continuously selected: CE
=OE= VIL.
transition low.
= VIL.
5
Page 6
bq4017/bq4017Y
Write Cycle (T
= 0 to 70°C, V
A
CCmin
V
CC
V
≤
≤
CCmax
)
-70
Symbol Parameter
t
t
t
t
t
t
t
t
t
t
t
t
WC
CW
AW
AS
WP
WR1
WR2
DW
DH1
DH2
WZ
OW
Write cycle time 70 - ns
Chip enable to end of write 65 - ns (1)
Address valid to end of write 65 - ns (1)
Address setup time 0 - ns
Write pulse width 55 - ns
Write recovery time
(write cycle 1)
Write recovery time
(write cycle 2)
Data valid to end of write 30 - ns
Data hold time
(write cycle 1)
Data hold time
(write cycle 2)
Write enabled to output in high Z 0 25 ns I/O pins are in output state. (5)
Output active from end of write 5 - ns I/O pins are in output state. (5)
Min. Max.
Units Conditions/Notes
5-ns
15 - ns
0-ns
10 - ns
Measured from address valid to be
ginning of write. (2)
Measured from beginning of write to
end of write. (1)
Measured from WE going high to
end of write cycle. (3)
Measured from CE going high to
end of write cycle. (3)
Measured to first low-to-high transition of either CE
Measured from WE going high to
end of write cycle. (4)
Measured from CE going high to
end of write cycle. (4)
Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE
of CE
going low and WE going low.
3. Either t
4. Either t
5. If CE
or t
or t
must be met.
WR2
must be met.
DH2
WR1
DH1
goes low simultaneously with WE going low or after WE going low, the outputs remain in
and a low WE. A write begins at the later transition
high-impedance state.
-
or WE.
6
Page 7
bq4017/bq4017Y
Write Cycle No. 1 (WE-Controlled)
Write Cycle No. 2 (CE-Controlled)
1,2,3
1,2,3,4,5
Notes: 1. CE or WE must be high during address transition.
2. Because I/O may be active (OE
outputs must not be applied.
3. If OE
4. Either t
5. Either t
is high, the I/O pins remain in a state of high impedance.
or t
or t
must be met.
WR2
must be met.
DH2
WR1
DH1
low) during this period, data input signals of opposite polarity to the
7
Page 8
bq4017/bq4017Y
Power-Down/Power-Up Cycle (T
= 0 to 70°C)
A
Symbol Parameter Minimum Typical Maximum Unit Conditions
t
PF
t
FS
t
PU
VCCslew, 4.75 to 4.25 V 300 - -
VCCslew, 4.25 to V
VCCslew, VSOto V
(max.)
SO
PFD
10 - -
0--
s
µ
s
µ
s
µ
Time during which SRAM
t
CER
Chip enable recovery time 40 80 120 ms
is write-protected after
V
passes V
CC
FPD
on
power-up.
t
t
DR
WPT
Data-retention time in
absence of V
CC
5 - - years
Write-protect time 40 100 150
s
µ
T
= 25°C. (2)
A
Delay after V
down past V
CC
PFD
slews
before
SRAM is write-protected.
Notes: 1. Typical values indicate operation at TA= 25°C, VCC= 5V.
2. Batteries are disconnected from circuit until after V
is applied for the first time. tDRis the
CC
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
8
Page 9
MC: 36-Pin C-Type Module
bq4017/bq4017Y
36-Pin MC
Dimension Minimum Maximum
All dimensions are in inches.
(C-Type Module)
A 0.365 0.375
A1 0.015 -
B 0.017 0.023
C 0.008 0.013
D 2.070 2.100
E 0.710 0.740
e 0.590 0.630
G 0.090 0.110
L 0.120 0.150
S 0.175 0.210
9
Page 10
bq4017/bq4017Y
Ordering Information
bq4017 MC -
Temperature:
blank = Commercial (0 to +70°C)
Speed Options:
70 = 70 ns
Package Option:
MC = C-type module
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4017 2048K x 8 NVSRAM
10
Page 11
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