Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Features
Pin-equivalent to the general-trade 26LS31 device,
■
with improved speed, reduced power consumption,
and significantly lower levels of EMI
Four line drivers per package
■
Meets ESDI standards
■
2.0 ns maximum propagation delay
■
Single 5.0 V ± 10% supply
■
Operating temperature range: −40 °C to +125 °C
■
(wider than the 41 Series)
400 Mbits/s maximum data rate
■
Logic to convert TTL input logic levels to differen-
■
tial, pseudo-ECL output logic levels
No line loading when VCC = 0 (BDG1A, BDP1A
■
only)
High output driver for 50 Ω loads
■
<0.2 ns output skew (typical)
■
On-chip 220 Ω loads available
■
Third-state outputs available
■
Surge-protection to ±60 V for 10 ms available
■
(BPNGA, BPNPA, BPPGA)
Available in four package types
■
ESD performance better than the 41 Series
■
Lower power requirement than the 41 Series
■
Description
These quad differential drivers are TTL input-topseudo-ECL-differential-output used for digital data
transmission over balanced transmission lines. All
devices in this family have four drivers with a single
enable control in a common package. These drivers
are compatible with many receivers, including the
Lucent Technologies Microelectronics Group 41
Series receivers and transceivers. They are pin
equivalent to the general-trade 26LS31, but offer
increased speed, decreased power consumption,
and significantly lower lev els of electromagnetic interference (EMI). They replace the Lucent 41 Series
drivers.
The BDG1A device is the generic driver in this family
and requires the user to supply external resistors on
the circuit board for impedance matching.
The BDGLA is a low-power version of the BDG1A,
reducing the power requirement by more than one
half. The BDGLA features a 3-state output with a typical third-state level of 0.2 V.
The BDP1A is equivalent to the BDG1A but has
220 Ω termination resistors to ground on each driver
output. This eliminates the need for external pulldown resistors when driving a 100 Ω impedance line.
The BPNGA and BPNPA are equivalent to the
BDG1A and BDP1A, respectively, except that a lightning protection circuit has been added to the driver
outputs. This circuit will absorb large transitions on
the transmission lines without destroying the device.
The BPPGA combines the features of the BPNGA
and BPNPA. Two of the gates have their outputs terminated to ground through 220 Ω resistors while the
two remaining gates require external termination
resistors.
When the BDG1A and the BDP1A devices are powered down, the output circuit appears as an open circuit relative to the power supplies; hence, they will
not load the transmission line. For those circuits with
termination resistors, the line will remain impedance
matched when the circuit is powered down. The
BPNGA, BPNPA, BPPGA, and BDGLA will load the
transmission line, because of the protection circuit,
when the circuit is powered down.
The packaging options that are available for these
quad differential line drivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing SOIC; and a
16-pin, narrow-body, gull-wing SOIC.
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Pin Information
Data Sheet
January 1999
AI
1
AO
AO
E1
BO
BO
BI
GND
A
2
3
4
5
6
B
7
8
D
C
BDG1A
BDGLA
BPNGA
Table 1. Enable Truth Table
E1 E2 Condition
00Active
10Active
01Disabled
11Active
V
CC
16
DI
15
DO
14
DO
13
E2
12
CO
11
CO
10
CI
9
AO
AO
E1
BO
BO
GND
AI
1
A
2
3
4
5
6
BI
B
7
8
D
C
V
CC
16
DI
15
DO
14
DO
13
E2
12
CO
11
CO
10
CI
9
BDP1A
BPNPA
Figure 1. Quad Differential Driver Logic Diagrams
AO
AO
E1
BO
BO
GND
AI
1
A
2
3
4
5
6
BI
B
7
8
D
C
V
CC
16
DI
15
DO
14
DO
13
E2
12
CO
11
CO
10
CI
9
BPPGA
12-2038b (F)
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter Symbol Min Max Unit
Power Supply Voltage V
Ambient Operating Temperature T
Storage Temperature T
2 Lucent Technologies Inc.
CC
A
stg
—6.5V
40 125 °C
−
55 150 °C
−
Data Sheet
January 199 9
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Quad Differential Drivers
Electrical Characteristics
For electrical characteristics over the entire temperature range, see Figures 7 through 9.
Table 2. Power Supply Current Characteristics
A
= –40 °C to +125 °C, V
T
CC
= 5 V ± 0.5 V.
Parameter Symbol Min Typ Max Unit
Power Supply Current (V
CC
= 5.5 V):
All Outputs Disabled:
BDG1A*, BPNGA* I
BDP1A
†
, BPNPA
†
BDGLA* I
BPPGA*
†
CC
CC
I
CC
CC
I
45 65 mA
120 160 mA
35 55 mA
85 115 mA
All Outputs Enabled:
BDG1A*, BPNGA* I
BDP1A
†
, BPNPA
†
BDGLA* I
BPPGA*
* Measured with no load (BPPGA has no load on drivers C and D).
† The additional power dissipation is the result of integrating the termination resistors into the device. I
across the driver outputs (BPPGA has terminating resistors on drivers A and B).
†
CC
CC
I
CC
CC
I
25 40 mA
150 200 mA
14 20 mA
90 115 mA
CC
is measured with a 100 Ω resistor
Third State
These drivers produce pseudo-ECL levels, and the third-state mode is different than the conventional TTL devices.
When a driver is placed in the third state, the bases of the output transistors are pulled low, bringing the outputs
below the active-low levels. This voltage is typically 2 V for most drivers. In the bidirectional bus application, the
driver of one device, which is in its third state, may be back driven by another driver on the bus whose voltage in the
low state is lower than the third-stated device. This could come about due to differences in the drivers’ independent
power supplies. In this case, the device in the third state will control the line, thus clamping the line and reducing
the signal swing. If the difference voltage between the independent power supplies and the drivers is small, then
this consideration can be ignored. In the typical case, the difference voltage can be as much as 1 V without significantly affecting the amplitude of the driving signal.
Lucent Technologies Inc. 3
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Electrical Characteristics
(continued)
Table 3. Voltage and Current Characteristics
For the variation in V
A
T
= –40 °C to +125 °C.*
OH
and V
OL
over the temperature range, see Figures 7 and 8.
Parameter Symbol Min Typ Max Unit
Output Voltages:
Low* V
OL
V
OH –
1.4 V
OH
1.1 V
−
OH
0.65 V
−
High*:
BDG1A, BDP1A, BPNGA, BPNPA, BPPGA V
BDGLA V
OH
Differential Voltage (V
Output Voltages (T
A
= 0 °C to 85 °C):
– VOL)V
Low* V
OH
OH
DIFF
OL
CC
V
CC
V
1.8 V
−
2.5 V
−
CC
1V
−
CC
2V
−
CC
0.8 V
−
CC
1.6 V
−
0.65 1.1 1.4 V
V
OH –
1.4 V
OH
1.1 V
−
OH
0.8 V
−
High*:
BDG1A, BDP1A, BPNGA, BPNPA, BPPGA V
BDGLA V
OH
Differential Voltage (V
Third State, I
OH
= –1.0 mA, VCC = 4.5 V:
– VOL)V
BDG1A, BDP1A, BPNGA, BPNPA, BPPGA V
BDGLA V
OH
OH
DIFF
OZ
OZ
CC
V
CC
V
1.5 V
−
2.5 V
−
CC
1V
−
CC
2V
−
CC
0.8 V
−
CC
1.6 V
−
0.8 1.1 1.4 V
—V
OL
0.5 V
−
OL
0.2 V
−
—0.20.5V
Input Voltages:
CC
Low, V
Data Input V
Enable Input V
High, V
Clamp, V
Short-circuit Output Current, V
Input Currents, V
Low, V
High, V
Reverse, V
= 5.5 V:
†
CC
= 4.5 V V
CC
= 4.5 V, II = –5.0 mA V
CC
= 5.5 V I
CC
= 5.5 V:
I
= 0.4 V I
I
= 2.7 V I
I
= 5.5 V I
OS
IL
†
IL
IH
IK
‡
IL
IH
IH
——0.8V
——0.7V
2.0 — — V
——−1.0 V
–100 — — mA
——−400
——20 µA
— — 100
Output Resistors:
BDP1A, BPNPA, BP PGA
* Values are with terminations as per Figure 4 or equivalent.
† The input levels and diff erence voltage provide zero noise immunity and should be tested only in a static, noise-free environment.
‡ Test must be performed one lead at a time to prevent damage to the device.
§ See Figure 1 for BPPGA terminations.
§
O
R
— 220 —
µ
µ
A
A
Ω
4 Lucent Technologies Inc.
Data Sheet
January 199 9
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Timing Characteristics
Table 4. Timing Characteristics (See Figures 2 and 3.)
P1
For t
and tP2 propagation delays over the temperature range, see Figure 9.
Propagation delay test circuit connected to output (see Figure 6).
Quad Differential Drivers
A
T
= –40 °C to +125 °C, V
CC
= 5 V ± 0.5 V.
Parameter Symbol Min Typ Max Unit
Propagation Delay:
Input High to Output
Input Low to Output
Capacitive Delay
†
†
tP1* 0.8 1.2 2.0 ns
tP2* 0.8 1.2 2.0 ns
p
t
∆
— 0.02 0.03 ns/pF
Disable Time (either E1 or E2):
High-to-high Impedance t
Low-to-high Impedance t
PHZ
PLZ
4 8 12 ns
4 8 12 ns
Enable Time (either E1 or E2):
High Impedance to High t
High Impedance to Low t
Output Skew, |t
PHH – tPHL
|t
P1
– tP2|t
PLH
|, |t
PLL
– t
|t
Difference Between Drivers
Rise Time ( 20%—80%) t
Fa ll Time (80%—20%) t
*tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 2).
† CL = 5 pF. Capacitor is connected from each output to ground.
PZH
PZL
skew1
skew2
t
∆
skew
tLH
tHL
4 8 12 ns
4 8 12 ns
—0.10.3ns
—0.20.5ns
——0.3ns
—0.7 2 ns
—0.7 2 ns
Lucent Technologies Inc. 5
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Timing Characteristics
INPUT
TRANSITION
OUTPUTS
PHH
t
OUTPUT
OUTPUT
PHL
t
OUTPUT
20%
(continued)
P1
t
80%
2.4 V
1.5 V
0.4 V
P2
t
t
PLL
OH
V
OL
V
OH
V
(VOH + VOL)/2
OL
V
OH
V
(VOH + VOL)/2
OL
PLH
t
80%
20%
tLH
t
tHL
t
V
OH
V
OL
V
12-2677F
Figure 2. Driver Propagation-Delay Timing
E1*
†
E2
PHZ
t
OUTPUT
OUTPUT
PLZ
t
* E2 = 1 while E1 changes state.
† E1 = 0 while E2 changes state.
Note: In the third state, both outputs (i.e., OUTPUT and OUTPUT
PZH
t
PZL
t
) are 0.2 V below the low state.
3.0 V
1.3 V
0.0 V
3.0 V
1.3 V
0.0 V
OH
V
OL
V
+ 0.2 V
OL
V
VOL – 0.1 V
OL
V
VOL – 0.1 V
12-2268.dC
Figure 3. Driver Enable and Disable Timing for a High Input
6 Lucent Technologies Inc.
Data Sheet
10
20
30
40
Y LOAD
π
LOAD
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
V
OL
V
OH
VCC – 2 V VCC – 1 V V
CC
10
20
30
40
V
OH
V
OL
Y LOAD
π
LOAD
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
V
CC
– 3 V V
CC
– 2 V V
CC
– 1 V V
CC
January 199 9
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Test Conditions
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the
data transmission driver devices are measured with the
following output load circuits.
Ω
100
DO(+) DO(–)
Ω
200
BDG1A, BPNGA, BDGLA, BPPGA (Gates A & B)
Ω
100
DO DO
BDP1A, BPNPA, BPPGA (Gates C & D)
Figure 4. Driver Test Circuit
200
Ω
12-2271F
12-2271.bC
Output Characteristics
Figure 6 illustrates typical driver output characteristics.
Included are load lines for two typical termination configurations.
12-2269F
A. Output Current vs. Output Voltage for Loads
Shown in C and D (BDG1A, BDP1A, BPNGA,
BPNPA, and BPPGA)
+5 V
Ω
110
DUT
Note: Surges can be applied simultaneously, but never in opposite
polarities.
Ω
110
+60 V
SURGE
10 µs
DURATION
1 ms
REPITITION
+60 V
SURGE
+
–
10 µs
+
–
DURATION
1 ms
REPETITION
12-2640.aF
B. Output Current vs. Output Voltage for Loads
Shown in C and D (BDGLA)
DO
60
Ω
90
60
Ω
DO
Ω
Figure 5. Lightning-Surge Testing Configuration
(BPNGA, BPNPA, and BPPGA)
DO(+) DO(–)
200
Figure 6. Driver Output Current vs. Voltage
Characteristics
Lucent Technologies Inc. 7
C. Y Load
Ω
D.
100
π
Ω
Load
200
Ω
12-2818aC
12-2270F
12-2271F
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Temperature Characteristics
Data Sheet
January 1999
0
CC
–0.5
–1.0
–1.5
–2.0
OUTPUT VOLTAGE RELATIVE TO V
–2.5
VOH MAX
VOH MIN
VOL MAX
–25 0 25 50 75 100
TEMPERATURE (°C)
VOL MIN
125 150–50
12-3467F
Figure 7. VOL and VOH Extremes vs. Temperature for
100 Ω Load
1.2
1.0
0.8
0.6
VOH – VOL TYP
VOH – VOL MIN
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
PROPAGATION DELAY (ns)
0.7
0.5
0.3
RANGE FOR tP1 AND t
MAX
MIN
–25 0 25 50 75 100
TEMPERATURE (°C)
P2
125 150–50
12-3469aF
Figure 9. Min and Max for tP1 and tP2 Propagation
Delays vs. Temperature
Handling Precautions
CAUTION:This device is susceptible to damage
as a result of electrostatic discharge.
Take proper precautions during both
handling and testing. Follow guidelines such as JEDEC Publication No.
108-A (Dec. 1988).
0.4
DIFFERENTIAL VOLTAGE (V)
0
–25 0 25 50 75 100
TEMPERATURE (°C)
Figure 8. Differential Voltage (VOH – VOL) vs.
Temperature for 100 Ω Load
125 150–50
12-3468F
When handling and mounting line driver products,
proper precautions should be taken to avoid exposure
to electrostatic discharge (ESD). The user should
adhere to the following basic rules for ESD control:
1. Assume that all electronic components are sensitive to ESD damage.
2. Never touch a sensitive component unless properly
grounded.
3. Never transport, store, or handle sensitive components except in a static-safe environment.
8 Lucent Technologies Inc.
Data Sheet
January 199 9
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
ESD Failure Models
Lucent employs two models for ESD events that can
cause device damage or failure.
1. A human-body model (HBM) that is used by most
of the industry for ESD-susceptibility testing and
protection-design evaluation. ESD voltage thresholds are dependent on the critical parameters used
to define the model. A standard HBM (resistance =
1500 Ω, capacitance = 100 pF) is widely used and,
therefore, can be used for comparison purposes.
2. A charged-device model (CDM), which many
believe is the better simulator of electronics manufacturing exposure.
Tables 5 and 6 illustrate the role these two models play
in the overall prevention of ESD damage. HBM ESD
testing is intended to simulate an ESD event from a
charged person. The CDM ESD testing simulates
charging and discharging events that occur in production equipment and processes, e.g., an integrated circuit sliding down a shipping tube.
The HBM ESD threshold voltage presented here was
obtained by using these circuit parameters.
Table 5. Typical ESD Thresholds for Data
Transmission Drivers
Device HBM
Threshold
BDG1A, BDGLA
BDP1A
BPPGA, BPNGA,
BPNPA
Table 6. ESD Damage Protection
Personnel Processes
Control Wrist straps
ESD shoes
Antistatic flooring
Model Human-body model
(HBM)
2500
>
2500
>
3000
>
ESD Threat Controls
Static-dissipative
Charged-device
model (CDM)
CDM
Threshold
1000
>
2000
>
2000
>
materials
Air ionization
Latch-Up
Latch-up evaluation has been performed on the data transmission drivers. Latch-up testing determines if powersupply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch-up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Lucent performs latch-up testing per an internal test method that is consistent with JEDEC Standard No. 17 (previously JC-40.2) “CMOS Latch-Up Standardized Test Procedure.”
Latch-up evaluation involves three separate stresses to evaluate latch-up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch-Up Test Criteria and Test Results
dc Current Stress of
I/O Pins
Data T ransmission
Driver ICs
Based on the results in Table 6, the data transmission drivers pass the Lucent latch-up testing requirements and
are considered not susceptible to latch-up.
Minimum Criteria
Test Results
150 mA
≥
250 mA
≥
Power Supply
Slew Rate
µs
≤1
100 ns
≤
Power Supply
Overvoltage
1.75 × Vmax
≥
2.25 × Vmax
≥
Lucent Technologies Inc. 9
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Outline Diagrams
16-Pin DIP
Dimensions are in millimeters.
Data Sheet
January 1999
N
1
PIN #1 IDENTIFIER ZONE
Package
Description
PDIP3 (Plastic
Dual-In-Line
Package)
L
B
H
SEATING PLANE
0.38 MIN
2.54 TYP
0.58 MAX
Package Dimensions
Number of
Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
16 20.57 6.48 7.87 5.08
W
5-4410r.2 (C)
Above Board
(H)
Note: The dimensions in this outline diagram are intended f or inf ormational purposes only. For detailed schematics to assist your design efforts,
please contact your Lucent Technologies Sales Representative.
10 Lucent Technologies Inc.
Data Sheet
January 199 9
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Outline Diagrams
(continued)
16-Pin SOIC (SONB/SOG)
Dimensions are in millimeters.
L
N
1
PIN #1 IDENTIFIER ZONE
B
W
H
SEATING PLANE
1.27 TYP
0.51 MAX
0.10
0.28 MAX
0.61
5-4414r.3 (C)
Package Dimensions
Package
Description
SONB (Sma ll-
Number of
Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
16 10.11 4.01 6.17 1.73
Above Board
(H)
Outline, Narrow
Body)
SOG (Small-
16 10.49 7.62 10.64 2.67
Outline, Gu ll-
Wing)
Note: The dimensions in this outline diag ram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Lucent Technologies Sales Representative.
Lucent Technologies Inc. 11
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Data Sheet
January 1999
Outline Diagrams
(continued)
16-Pin SOIC (SOJ)
Dimensions are in millimeters.
N
1
PIN #1 IDENTIFIER ZONE
L
B
W
H
SEATING PLANE
0.10
1.27 TYP
0.51 MAX
0.79 MAX
5-4413r.3 (C)
Package Dimensions
Package
Description
SOJ (Small-
Number of
Pins
(N)
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
16 10.41 7.62 8.81 3.18
Above Board
(H)
Outline, J-Lead)
Note: The dimensions in this outline diagram are intended f or inf ormational purposes only. For detailed schematics to assist your design efforts,
please contact your Lucent Technologies Sales Representative.
12 Lucent Technologies Inc.
Data Sheet
DIP
SOIC/NB
J-LEAD SOIC/GULL WING
AIRFLOW (ft./min.)
200 400 600 800 1000 12000
40
50
60
70
80
90
100
110
120
130
140
THERMAL RESISTANCE
Θ
ja
(
°
C/W)
January 199 9
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Power Dissipation
System designers incorporating Lucent data transmission drivers in their applications should be aware of
package and thermal information associated with these
components.
Proper thermal management is essential to the longterm reliability of any plastic encapsulated integrated
circuit. Thermal management is especially important
for surface-mount devices, given the increasing circuit
pack density and resulting higher thermal density. A
key aspect of thermal management involves the junction temperature (silicon temperature) of the integrated
circuit.
Several factors contribute to the resulting junction temperature of an integrated circuit:
Ambient use temperature
■
Device power dissipation
■
Component placement on the board
■
Thermal properties of the board
■
Thermal impedance of the package
■
Thermal impedance of the package is referred to as
ja
and is measured in °C rise in junction temperature
Θ
per watt of power dissipation. Thermal impedance is
also a function of airflow present in system application.
The following equation can be used to estimate the
junction temperature of any device:
The power dissipated in the output is a function of the:
Termination scheme on the outputs
■
Termination resistors
■
Duty cycle of the output
■
Package thermal impedance depends on:
Airflow
■
Package type (e.g., DIP, SOIC, SOIC/NB)
■
The junction temperature can be calculated using the
previous equation, after power dissipation levels and
package thermal impedances are known.
Figure 10 illustrates the thermal impedance estimates
for the various package types as a function of airflow.
This figure shows that package thermal impedance is
higher for the narrow-body SOIC package. Particular
attention should, therefore, be paid to the thermal management issues when using this package type.
In general, system designers should attempt to maintain junction temperature below 125 °C. The following
factors should be used to determine if specific data
transmission drivers in particular package types meet
the system reliability objectives:
System ambient temperature
■
Power dissipation
■
Pac kage type
■
Airflow
■
j
T
= TA + PD
Θ
ja
where:
j
T
is device junction temperature (°C).
A
T
is ambient temperature (°C).
D
P
is power dissipation (W).
ja
is package thermal impedance (junction to ambi-
Θ
ent
°C/W).
—
The power dissipation estimate is derived from two factors:
Internal device power
■
Power associated with output terminations
■
Multiplying I
nal power dissipation.
CC
times VCC provides an estimate of inter-
12-2753F
Figure 10. Power Dissipation
Lucent Technologies Inc. 13
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Ordering Information
Data Sheet
January 1999
Part Number Intern.
Term.
BDG1A16E None No 16-pin, Plastic SOJ 107914186 1041 LG, MG, MGA
BDG1A16E-TR None No Tape & Reel SOJ 107914194 1041 LG, MG, MGA
BDG1A16G None No 16-pin, Plastic SOIC 107914160 1141 LG, MG, MGA
BDG1A16G-TR None No Tape & Reel SOIC 107914178 1141 LG, MG, MGA
BDG1A16NB None No Plastic SOIC/NB 107914202 1241 LG, MG, MGA
BDG1A16NB-TR None No Tape & Reel SOIC/NB 107914210 1241 LG, MG, MGA
BDG1A16P None No 16-pin, Plastic DIP 107914004 41 LG, MG, MGA
BDP1A16E 220
BDP1A16E-TR 220
BDP1A16G 220
BDP1A16G-TR 220
BDP1A16P 220
BDGLA16E None No 16-pin, Plastic SOJ 107914228 1041 MGL3
BDGLA16E-TR None No Tape & Reel SOJ 107914236 1041 MGL3
BDGLA16G None No 16-pin, Plastic SOIC 107914244 1141 MG L 3
BDGLA16G-TR None No Tape & Reel SOIC 107914251 1141 MGL3
BDGLA16NB None No Plastic SOIC/NB 107914269 1241 MGL3
BDGLA16NB-TR None No Tape & Reel SOIC/NB 107914277 1241 MGL3
BDGLA16P None No 16-pin, Plastic DIP 107914285 41 MGL3
BPNGA16E None Yes 16-pi n, Pl astic SOJ 107914343 1041 NG
BPNGA16E-TR None Yes Tape & Reel SOJ 107914350 1041 NG
BPNGA16G None Yes 16-pin, Plastic SOIC 107914368 1141 NG
BPNGA16G-TR None Yes Tape & Reel SOIC 107914376 1141 NG
BPNGA16NB None Yes Plastic SOIC/NB 107914384 1241 NG
BPNGA16NB-TR None Yes Tape & Reel SOIC/NB 107914392 1241 NG
BPNGA16P None Yes 16-pin, Plastic DIP 107914400 41 NG
BPNPA16E 220
BPNPA16E-TR 220
BPNPA16G 220
BPNPA16G-TR 220
BPNPA16P 220
BPPGA16E 220
BPPGA16E-TR 220
BPPGA16G 220
BPPGA16G-TR 220
BPPGA16P 220
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Surge
Prot.
No 16-pin, Plastic SOJ 107914293 1041 LP, MP, MPA
No Tape & Reel SOJ 107914301 1041 LP, MP, MPA
No 16-pin, Plastic SOIC 107914319 1141 LP, MP, MPA
No Tape & Reel SOIC 107914327 1141 LP, MP, MPA
No 16-pin, Plastic DIP 107914335 41 LP, MP, MPA
Yes 16-pin, Plas tic SOJ 107914418 1041 NP
Yes Tape & Reel SOJ 107914426 1041 NP
Yes 16-pin, Plas tic SOIC 107914434 1141 NP
Yes Tape & Reel SOIC 107914442 1141 NP
Yes 16-pin, Plastic DIP 107949745 41 NP
Yes 16-pin, Plas tic SOJ 107949752 1041 PG
Yes Tape & Reel SOJ 107949760 1041 PG
Yes 16-pin, Plas tic SOIC 107949778 1141 PG
Yes Tape & Reel SOIC 107949786 1141 PG
Yes 16-pin, Plastic DIP 107949794 41 PG
Package Type Comcode Former
Pkg. Type
Former
Part #
14 Lucent Technologies Inc.
Data Sheet
January 199 9
Notes
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
Lucent Technologies Inc. 15
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January 1999
DS99-144HSI (Replaces DS99-044HSI)
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