Page 1
DISCRETE SEMICONDUCTORS
DATA SHEET
M3D427
BLF2048
UHF push-pull power
LDMOS transistor
Preliminary specification 1999 Nov 23
Page 2
Preliminary specification
0
UHF push-pull power LDMOS transistor BLF2048
FEATURES
• High power gain
• Easy power control
• Excellent ruggedness
• Source on underside eliminates DC isolators, reducing
common mode inductance
• Designed for broadband operation (HF to 2.2 GHz).
APPLICATIONS
• Common source class-AB operation for PCN and PCS
applications in the 1800 to 2200 MHz frequency range.
DESCRIPTION
Push-pull silicon N-channel enhancement mode lateral
D-MOS transistor encapsulated in a 4-lead flange package
(SOT539A) with a ceramic cap. The common source is
connected to the mounting flange.
QUICK REFERENCE DATA
RF performance at T
=25°C in a common source test circuit.
h
PINNING - SOT539A
PIN DESCRIPTION
1drain 1
2drain 2
3gate 1
4gate 2
5 source connected to flange
12
Top view
Fig.1 Simplified outline.
43
5
MBK88
MODE OF OPERATION
class-AB (2-tone) f
f
(MHz)
= 2200; f2= 2200.1
1
V
(V)
DS
P
(W)
L
G
p
(dB)
η
(%)
D
d
im
(dBc)
26 120 (PEP) >10 >30 ≤−26
28 140 (PEP) typ. 11.2 typ. 31 typ. −25
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
GS
I
D
T
stg
T
j
drain-source voltage − 65 V
gate-source voltage −±15 V
drain current (DC) − 18 A
storage temperature −65 +150 °C
junction temperature − 200 °C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1999 Nov 23 2
Page 3
Preliminary specification
UHF push-pull power LDMOS transistor BLF2048
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-mb
R
th mb-h
Note
1. Thermal resistance is determined under nominal 2-tone RF operating conditions.
CHARACTERISTICS
T
=25°C; per section; unless otherwise specified.
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GSth
I
DSS
I
DSX
I
GSS
g
fs
R
DSon
C
rs
thermal resistance from junction to mounting-base PL=120W; Tmb=50°C,
0.35 K/W
note 1
thermal resistance from mounting-base to heatsink 0.15 K/W
drain-source breakdown voltage VGS=0; ID=1.4mA 65 −−V
gate-source threshold voltage VDS=10V; ID= 140 mA 1.5 − 3.5 V
drain-source leakage current VGS=0; VDS=26V −−10 µA
drain cut-off current VGS=V
+9V; VDS=10V 18 −−A
GS(th)
gate leakage current VGS= ±15 V; VDS=0 −−250 nA
forward transconductance VDS=10V; ID=5A − 4 − S
drain-source on-state resistance VGS=V
+9V; ID=5A − 0.17 −Ω
GS(th)
feedback capacitance VGS=0; VDS=26V; f=1MHz − 3.4 − pF
Notes
1. Capacitance of die only.
APPLICATION INFORMATION
RF performance in a common source class-AB circuit. T
MODE OF OPERATION
class-AB (2-tone) f
= 2200; f2= 2200.1
1
f
(MHz)
=25°C; R
h
V
DS
(V)
(mA)
= 0.5 K/W; unless otherwise specified..
th j-h
I
DQ
P
(W)
L
G
p
(dB)
η
(%)
D
d
im
(dBc)
26 2 x 400 120 (PEP) >10 >30 ≤−26
28 2 x 400 140 (PEP) typ. 11.2 typ. 31 typ. −25
Ruggedness in class-AB operation
The BLF2048 is capable of withstanding a load mismatch corresponding to VSWR = 10 : 1 through all phases under the
following conditions: V
= 26 V; f = 2200 MHz, PL= 120 W (CW).
DS
1999 Nov 23 3
Page 4
Preliminary specification
Fig.2 Power gain and drain efficiency as functions of
peak envelope load power; typical values.
f1=2000MHz; f2= 2000.1 MHz;
I
DQ
=2x400mA; T
h
≤ 25 °C.
f1=2000MHz; f2= 2000.1 MHz;
I
DQ
=2x400mA; T
h
≤ 25 °C.
Fig.4 Intermodulation distortion as a function of
peak envelope load power; typical values.
UHF push-pull power LDMOS transistor BLF2048
20
G
P
(dB)
VDS = 26 V
16
G
12
8
P
η
D
4
0
0 40 80 120 160 200
P
28 V
28 V
26 V
(PEP) (W)
L
50
40
30
20
10
0
η
(%)
20
D
G
P
(dB)
16
12
G
P
η
8
D
VDS = 26 V
26 V
4
0
28 V
28 V
50
40
30
20
10
0
η
(%)
D
0 40 80 120 160 200
P
(PEP) (W)
L
f1=2200MHz; f2= 2200.1 MHz;
=2x400mA; T
I
DQ
≤ 25 °C.
h
Fig.3 Power gain and drain efficiency as functions of
peak envelope load power; typical values.
-10
d
IM
(dBc)
-20
-30
d
-40
d
5
-50
-60
0 40 80 120 160 200
1999 Nov 23 4
-10
d
IM
VDS = 26 V
(dBc)
VDS = 26 V
-20
28 V
28 V
-30
3
28 V
26 V
-40
-50
d
3
d
5
26 V
28 V
-60
0 40 80 120 160 200
P
(PEP) (W)
L
f1=2200MHz; f2= 2200.1 MHz;
=2x400mA; T
I
DQ
≤ 25 °C.
h
P
(PEP) (W)
L
Fig.5 Intermodulation distortion as a function of
peak envelope load power; typical values.
Page 5
Preliminary specification
Fig.6 Input impedance per section as a function of
frequency (series components);
typical values.
VDS=26V; IDQ= 2 x 400 mA; PL= 160 W (total device);
T
h
≤ 25 °C.
UHF push-pull power LDMOS transistor BLF2048
8
Z
i
(Ω)
4
x
0
i
-4
1.6 1.8 2 2.2 2.4 2.6
r
i
f (GHz)
8
Z
L
(Ω)
4
R
L
0
-4
X
L
-8
1.61.822.22.42.6
f (GHz)
VDS=26V; IDQ=2x400mA; PL= 160 W (total device);
≤ 25 °C.
T
h
Fig.7 Load impedance per section as a function of
frequency (series components);
typical values.
1999 Nov 23 5
Page 6
Preliminary specification
UHF push-pull power LDMOS transistor BLF2048
VBIAS
R1
P1
50 Ohm
Input
L1
P2
R3
VBIAS
List of components
C13
C9
L2
B1
B2
L3
C8
C12
R2
R4
C7 C6
C11
C10
C1
C2
C3
L12
L10
L8
L6
L4
C5
C4
L5
L7
L9
L13
L11
T1
Fig.8 Testcircuit for 2.2 GHz.
L14
C14
L15
L16
L17
C15
L23
C19
L18
L19
C25
L25
C17
C16
C18
C20
C26
C21
C27
C22
C28
L20
B3
B4
L21
R5
L24
L26
R6
C23
C29
C24
C30
VDS
L22
VDS
50 Ohm
Output
COMPONENT DESCRIPTION VALUE DIMENSIONS CATALOGUE NO.
C1, C2 multilayer ceramic chip capacitor; note 1 5.1 pF
C3, C5 Tekelec variable capacitor 0.6 to 4.5 pF
C4 Tekelec variable capacitor + multilayer
ceramic chip capacitor; note 1
0.6 to 4.5 pF +
2.4 pF
C6, C10 multilayer ceramic chip capacitor; note 2 100 pF
C7, C11 multilayer ceramic chip capacitor; note 2 18 pF
C8, C12, C23,
tantal SMD capacitor 4.7 µF; 35 V
C29
C9, C13, C24,
tantal SMD capacitor 10 µF; 35 V
C30
C14 multilayer ceramic chip capacitor; note 3 0.5 pF
C15 multilayer ceramic chip capacitor; note 3 1 pF
C16 multilayer ceramic chip capacitor; note 1 1.5 pF
C17, C18 multilayer ceramic chip capacitor; note 1 10 pF
C19, C25 MKT ceramic chip capacitor 33 nF 2222 370 11333
C20, C26 multilayer ceramic chip capacitor; note 2 6.2 pF
C21, C27 multilayer ceramic chip capacitor 100 nF 2222 581 16641
C22, C28 multilayer ceramic chip capacitor; note 1 8.2 pF
1999 Nov 23 6
Page 7
Preliminary specification
UHF push-pull power LDMOS transistor BLF2048
COMPONENT DESCRIPTION VALUE DIMENSIONS CATALOGUE NO.
L1 stripline; note 4 47 Ω 4.5 × 1mm
L2, L3, L20,
L21
L4, L5 stripline; note 4 5.6 × 2.6 mm
L6, L7 stripline; note 4 2.6 × 5.8 mm
L8, L9 stripline; note 4 11.5 × 12 mm
L10, L11 stripline; note 4 2.2 × 16 mm
L12, L13 stripline; note 4 57 Ω 1/4 λ @2.2GHz
L14, L15 stripline; note 4 10.4 × 13.7 mm
L16, L17 stripline; note 4 6.6 × 5.5 mm
L18, L19 stripline; note 4 7 × 2.6 mm
L22 stripline; note 4 47 Ω 4x1mm
L23, L25 stripline; note 4 47 Ω 1/4 λ @2.2GHz
L24, L26 1 turn enamelled 0.7 mm copper wire int.dia. 7 mm;
B1, B4 balun of semi-rigid cable 50 Ω
B2, B3 semi-rigid cable; note 5 50 Ω
R1, R3, R5, R6metal film resistor 5.6 Ω, 0.6 W
stripline; note 4 15 × 2mm
length ...... mm
R2, R4 metal film resistor 10 Ω, 0.6 W
P1, P2 variable resistor (multiturn) 5 kΩ
Notes
1. American Technical Ceramics type 100B or capacitor of same quality.
2. American Technical Ceramics type 100A or capacitor of same quality.
3. American Technical Ceramics type 180R or capacitor of same quality.
4. Semi-rigid cable soldered along the stub to establish balance.
5. The striplines are on a double copper-clad PCB with Teflon dielectric (εr = 6.15); thickness 0.64 mm.
1999 Nov 23 7
Page 8
Preliminary specification
UHF push-pull power LDMOS transistor BLF2048
40 mm
40 mm
60 mm
P1
C8
C9
R1
VBIAS
R5
L14
C20
L23
R2
C6
C7
L12
L10
L8
L24
C21
C22
VDS
C24C23
L15
C14
L25
C26
C19
L16
C15
L17
C25
C27
R6 L26
L18
C16
L19
C28
C17
C18
C29
VDS
B3,L20
L22
B4,L21
C30
B1,L2
L1
B2,L3
C13
R4
C12
P2
Dimensions in mm.
The components are situated on one side of the copper-clad printed-circuit board with Teflon dielectric
ε
= 6.15), thickness 0.64 mm.
(
r
The other side is unetched and serves as a ground plane.
L6
C1
L4
PHILIPS
L13
C5
L9
L11
BLF2048
C4
C3
L5
C2
L7
C11
C10
VBIAS
R3
Fig.9 Component layout for 2.2 GHz class-AB testcircuit.
1999 Nov 23 8
Page 9
Preliminary specification
UHF push-pull power LDMOS transistor BLF2048
PACKAGE OUTLINE
Flanged balanced LDMOST package; 2 mounting holes; 4 leads SOT539A
Package under
development
Philips Semiconductors reserves the
right to make changes without notice.
D
A
D
1
U
1
q
H
1
w
M M
2
F
B
C
C
c
12
H
U
2
L
A
e
43
b
0 5 10 mm
scale
p
5
w
M
3
w
M M M
1
AB
E
1
Q
E
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
11.81
11.56
0.465
0.455
c
Db
D
1
31.55
0.15
0.08
0.006
0.003
31.65
30.94
30.96
1.242
1.246
1.218
1.219
IEC JEDEC EIAJ
EE
e U
9.50
13.72
0.540
9.53
9.20
9.27
0.375
0.374
0.365
0.366
REFERENCES
F
1
1.75
1.50
0.069
0.059
H
17.12
16.10
0.674
0.634
H
1
25.53
25.27
1.005
0.995
L
3.73
2.72
0.147
0.107
p
3.30
3.05
0.130
0.120
qw
Q
2.31
2.01
0.091
0.079
U
41.28
35.56
41.02
1.625
1.615
EUROPEAN
PROJECTION
1
10.29
10.03
0.405
0.395
2
w
1
ISSUE DATE
99-05-10
99-06-25
w
3
2
0.250.25 0.51
0.0100.010 0.0201.400
UNIT
mm
inches
A
5.33
3.96
0.210
0.156
OUTLINE
VERSION
SOT539A
1999 Nov 23 9
Page 10
Preliminary specification
UHF push-pull power LDMOS transistor BLF2048
DEFINITIONS
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Nov 23 10
Page 11
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under patent- or other industrial or intellectual property rights.
1999
Internet: http://www.semiconductors.philips.com
68
Printed in The Netherlands 125108/00/01/pp11 Date of release: 1999 Nov 23 Document order numb er: 9397 7 50 06582
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