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BF904AWR
Datasheet (Philips)
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Datasheet BF904AWR Datasheet (Philips)

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Page 1
DISCRETE SEMICONDUCTORS
DATA SH EET
BF904A; BF904AR; BF904AWR
N-channel dual gate MOS-FETs
Product specification Supersedes data of 1999 Feb 01
1999 May 14
Page 2
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
FEATURES
• Specially designed for use at 5 V supply voltage
• Short channel transistor with high transfer admittance to input capacitance ratio
• Low noise gain controlled amplifier up to 1 GHz
• Superior cross-modulation performance during AGC.
APPLICATIONS
• VHF and UHF applications with 3 to 7 V supply voltage such as television tuners and professional communications equipment.
DESCRIPTION
Enhancement type field-effect transistors. The transistors consist of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. The BF904A, BF904AR and BF904AWR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively.
PINNING
PIN DESCRIPTION
1 source 2 drain 3 gate 2 4 gate 1
handbook, 2 columns
Top view
BF904AR marking code: M42.
Fig.2 Simplified outline
(SOT143R).
43
12
MSB035
handbook, 2 columns
12
Top view
BF904A marking code: M41.
Fig.1 Simplified outline
(SOT143B).
alfpage
21
Top view
BF904AWR marking code: MH.
Fig.3 Simplified outline
(SOT343R).
34
MSB014
43
MSB842
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DS
I
D
P
tot
y
forward transfer admittance 22 25 30 mS
fs
C
ig1-ss
C
rss
drain-source voltage −−7V drain current −−30 mA total power dissipation Ts≤ 110 °C −−200 mW
input capacitance at gate 1 − 2.2 2.6 pF
reverse transfer capacitance f = 1 MHz − 25 35 fF F noise figure f = 800 MHz − 2 − dB T
j
operating junction temperature −−150 °C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1999 May 14 2
Page 3
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. T
is the temperature of the soldering point of the source lead.
s
drain-source voltage − 7V drain current − 30 mA gate 1 current −±10 mA gate 2 current −±10 mA total power dissipation Ts≤ 110 °C; note 1; see Fig.4 − 200 mW storage temperature −65 +150 °C operating junction temperature − 150 °C
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0 50 100 200
MGL615
150
Ts (°C)
Fig.4 Power derating curve.
1999 May 14 3
Page 4
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-s
Note
1. Soldering point of the source lead.
STATIC CHARACTERISTICS
=25°C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-SS
I
G2-SS
thermal resistance from junction to soldering point note 1 200 K/W
gate 1-source breakdown voltage V gate 2-source breakdown voltage V forward source-gate 1 voltage V forward source-gate 2 voltage V gate 1-source threshold voltage V gate 2-source threshold voltage V drain-source current V
G2-S=VDS G1-S=VDS G2-S=VDS G1-S=VDS G2-S G1-S=VDS G2-S
= 0; I = 0; I = 0; I = 0; I
= 10 mA 6 15 V
G1-S
= 10 mA 6 15 V
G2-S
= 10 mA 0.5 1.5 V
S-G1
= 10 mA 0.5 1.5 V
S-G2
=4V; VDS=5V; ID=20µA 0.3 1 V
=5V; ID=20µA 0.3 1.2 V
=4V; VDS=5V;
813mA
RG1= 120 kΩ; note 1 gate 1 cut-off current V gate 2 cut-off current V
G2-S=VDS G1-S=VDS
= 0; V = 0; V
=5V − 50 nA
G1-S
=5V − 50 nA
G2-S
Note
1. R
connects gate 1 to VGG= 5 V; see Fig.21.
G1
DYNAMIC CHARACTERISTICS
Common source; T
=25°C; VDS= 5 V; V
amb
= 4 V; ID= 10 mA; unless otherwise specified.
G2-S
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
y
forward transfer admittance pulsed; Tj=25°C 222530mS
fs
C
ig1-s
C
ig2-s
C
os
C
rs
F noise figure f = 200 MHz; G
input capacitance at gate 1 f = 1 MHz − 2.2 2.6 pF input capacitance at gate 2 f = 1 MHz 1 1.5 2 pF drain-source capacitance f = 1 MHz 1 1.4 1.7 pF reverse transfer capacitance f = 1 MHz − 25 35 fF
f = 800 MHz; G
= 2 mS; BS=B
S S=GSopt
; BS=B
− 1 1.5 dB
Sopt
− 2 2.8 dB
Sopt
1999 May 14 4
Page 5
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
100
MLD268
o
T ( C)
j
40
Y
fs
(mS)
30
20
10
0
50 0 50 150
Fig.5 Transfer admittance as a function of the
junction temperature; typical values.
handbook, halfpage
reduction
0
gain
(dB)
10
20
30
40
50
01234
f =50 MHz.
Fig.6 Typical gain reduction as a function of
the AGC voltage; see Fig.21.
MRA769
V (V)
AGC
120
handbook, halfpage
V
unw
(dB V)
µ
110
100
90
80
0 1020304050
VDS= 5V; VGG= 5V; fw= 50MHz. f
= 60MHz; T
unw
=25°C; RG1= 120kΩ.
amb
gain reduction (dB)
MRA771
Fig.7 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values; see Fig.21.
20
I
D
(mA)
15
10
VDS=5V. Tj=25°C.
5
0
0
0.4 2.0
V = 4 V
G2 S
0.8 1.2 1.6
3 V 2.5 V
V (V)
G1 S
Fig.8 Transfer characteristics; typical values.
MLD270
2 V
1.5 V
1 V
1999 May 14 5
Page 6
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
20
handbook, halfpage
I
D
(mA)
16
12
8
4
0
0
V
=4V.
G2-S
Tj=25°C.
210
V = 1.4 V
G1 S
1.3 V
1.2 V
1.1 V
1.0 V
0.9 V
468
Fig.9 Output characteristics; typical values.
MLD269
V (V)
DS
150
handbook, halfpage
I
G1
(µA)
100
50
0
0
VDS=5V. Tj=25°C.
0.5 2.5
1.0 1.5 2.0
V = 4 V
G2 S
3.5 V
3 V
2.5 V
2 V
V (V)
Fig.10 Gate 1 current as a function of gate 1
voltage; typical values.
MLD271
G1 S
40
handbook, halfpage
y
fs
(mS)
30
20
10
0
0
VDS=5V. Tj=25°C.
4 8 12 16 20
Fig.11 Forward transfer admittance as a
function of drain current; typical values.
MLD272
V = 4 V
G2 S
3.5 V 3 V
2.5 V
2 V
I (mA)
D
16
handbook, halfpage
I
D
(mA)
12
8
4
0
0
VDS=5V. V
=4V.
G2-S
Tj=25°C.
10 50
20 30 40
MLD273
I (µA)
G1
Fig.12 Drain current as a function of gate 1 current;
typical values.
1999 May 14 6
Page 7
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
12
handbook, halfpage
I
D
(mA)
8
4
0
0
VDS= 5 V; V RG1= 120 kΩ (connected to VGG); see Fig.21.
15
= 4 V; Tj=25°C.
G2-S
234
MLD275
V (V)
GG
Fig.13 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
20
handbook, halfpage
I
D
(mA)
15
10
5
0
0
V
= 4 V; Tj=25°C.
G2-S
RG1 connected to VGG; see Fig.21.
R = 47 kΩ
24 8
G1
68 kΩ
V = V (V)
GG DS
Fig.14 Drain current as a function of gate 1
(= VGG) and drain supply voltage; typical values.
MLD274
82 kΩ
100 kΩ 120 kΩ 150 kΩ
180 kΩ 220 kΩ
6
12
handbook, halfpage
I
D
(mA)
8
4
0
0246
VDS= 5 V; Tj=25°C. RG1= 120 kΩ (connected to VGG); see Fig.21.
V = 5 V
GG
4.5 V 4 V
3.5 V 3 V
V (V)
G2 S
MLD276
Fig.15 Drain current as a function of gate 2 voltage;
typical values.
40
handbook, halfpage
I
G1
(µA)
30
20
10
0
0246
VDS= 5 V; Tj=25°C. RG1= 120 kΩ (connected to VGG); see Fig.21.
V = 5 V
GG
V (V)
Fig.16 Gate 1 current as a function of gate 2
voltage; typical values.
MLB945
4.5 V 4 V
3.5 V 3 V
G2 S
1999 May 14 7
Page 8
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
2
10
handbook, halfpage
y
is
MLD277
(mS)
10
b
is
1
g
is
1
10
10
2
10
f (MHz)
10
VDS= 5 V; VG2=4V. ID= 10 mA; T
amb
=25°C.
Fig.17 Input admittance as a function of frequency;
typical values.
f (MHz)
MLD278
3
10
ϕ
rs
(deg)
2
10
10
1
3
10
3
10
y
rs
(µS)
ϕ
2
10
rs
y
rs
10
3
1
10
2
10
VDS= 5 V; VG2=4V. ID= 10 mA; T
amb
=25°C.
Fig.18 Reverse transfer admittance and phase as
a function of frequency; typical values.
MLD279
3
10
y
(mS)
2
10
fs
10
1
10
y
fs
ϕ
fs
2
10
f (MHz)
VDS= 5 V; VG2=4V. ID= 10 mA; T
amb
=25°C.
Fig.19 Forward transfer admittance and phase as
a function of frequency; typical values.
10
ϕ
(deg)
10
1
2
10
handbook, halfpage
y
os
(mS)
MGL614
fs
b
os
1
g
−1
10
−2
10
10 10
os
2
10
f (MHz)
3
VDS= 5 V; VG2=4V. ID= 10 mA; T
amb
=25°C.
Fig.20 Output admittance as a function of
frequency; typical values.
1999 May 14 8
Page 9
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
V
AGC
R1
10 kΩ
C1
R
GEN
50
V
4.7 nF
C2
4.7 nF
R2
50
Ω
I
Ω
R
G1
V
GG
DUT
V
DS
C3 12 pF
L1
450 nH
≈
C4
4.7 nF
R 50 Ω
MLD171
L
Fig.21 Cross-modulation test set-up.
1999 May 14 9
Page 10
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
Table 1 Scattering parameters: VDS= 5 V; V
S
f
(MHz)
MAGNITUDE
(ratio)
11
ANGLE
(deg)
MAGNITUDE
(ratio)
= 4 V; ID= 10 mA; T
G2-S
S
21
ANGLE
(deg)
=25°C
amb
S
12
MAGNITUDE
(ratio)
ANGLE
(deg)
S
MAGNITUDE
(ratio)
22
ANGLE
(deg)
40 0.989 −3.2 2.52 175.9 0.001 87.9 0.989 −1.7 100 0.987 −7.9 2.52 169.4 0.001 86.1 0.988 −4.3 200 0.976 −15.7 2.47 159.2 0.003 81.4 0.984 −8.6 300 0.972 −23.3 2.43 150.5 0.004 80.5 0.985 −12.7 400 0.947 −30.6 2.36 139.6 0.005 76.9 0.975 −16.9 500 0.925 −37.6 2.26 130.3 0.005 75.6 0.968 −20.8 600 0.905 −44.4 2.19 121.1 0.005 75.5 0.961 −24.7 700 0.883 −50.9 2.10 112.3 0.006 78.0 0.954 −28.4 800 0.861 −57.0 2.01 103.6 0.006 85.3 0.946 −32.0 900 0.841 −63.0 1.93 95.5 0.006 90.7 0.934 −35.6
1000 0.822 −68.4 1.85 87.8 0.006 102.6 0.931 −39.3
1200 0.787 −78.9 1.71 72.3 0.007 127.1 0.923 −46.7 1400 0.752 −88.1 1.59 57.3 0.011 143.7 0.926 −54.2 1600 0.723 −97.3 1.47 40.1 0.019 150.0 0.935 −62.2 1800 0.685 −106.3 1.36 25.0 0.021 149.4 0.931 −69.3 2000 0.665 −114.0 1.31 7.7 0.026 151.5 0.930 −77.7 2200 0.659 −119.8 1.30 −14.0 0.035 158.2 0.944 −89.1 2400 0.670 −124.2 1.26 −42.2 0.050 163.4 0.941 −103.5 2600 0.700 −129.3 1.10 −78.2 0.076 162.2 0.849 −119.7 2800 0.729 −138.7 0.82 −120.8 0.106 150.5 0.642 −130.9 3000 0.726 −150.1 0.52 −162.8 0.128 137.4 0.480 −130.6
Table 2 Noise data: V
f
(MHz)
= 5 V; V
DS
= 4 V; ID= 10 mA; T
G2-S
F
min
(dB)
800 2.0 0.686 49.6 50.4
1999 May 14 10
=25°C
amb
Γ
opt
(ratio) (deg)
R
(Ω)
n
Page 11
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
PACKAGE OUTLINES
Plastic surface mounted package; 4 leads SOT143B
D
y
e
b
p
B
w M
E
v M
A
B
H
E
A
X
34
Q
A
A
1
21
b
1
e
1
detail X
L
c
p
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
VERSION
1.1
0.9
OUTLINE
SOT143B
1
A
max
0.1
b
c
D
b
0.48
0.38
1
p
0.88
0.15
0.78
0.09
IEC JEDEC EIAJ
E
3.0
1.4
2.8
1.2
REFERENCES
e
1.9
1999 May 14 11
e
1.7
H
L
E
1
2.5
2.1
0.45
0.15
p
0.55
0.45
EUROPEAN
PROJECTION
ywvQ
0.1 0.10.2
ISSUE DATE
97-02-28
Page 12
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
Plastic surface mounted package; reverse pinning; 4 leads SOT143R
D
y
e
b
p
B
w M
E
v M
A
B
H
E
A
X
43
Q
A
A
1
c
12
L
b
1
e
1
detail X
p
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
VERSION
1.1
0.9
OUTLINE
SOT143R
1
A
max
0.1
b
c
D
b
0.48
0.38
1
p
0.88
0.15
0.78
0.09
IEC JEDEC EIAJ
E
3.0
1.4
2.8
1.2
REFERENCES
e
1.9
1999 May 14 12
e
1.7
H
L
E
1
2.5
2.1
0.55
0.25
p
0.45
0.25
EUROPEAN
PROJECTION
ywvQ
0.1 0.10.2
ISSUE DATE
97-03-10
Page 13
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
Plastic surface mounted package; reverse pinning; 4 leads SOT343R
w M
D
y
e
43
21
b
B
p
e
b
1
1
E
H
E
A
A
1
detail X
AB
Q
L
p
X
v M
A
c
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
OUTLINE
VERSION
SOT343R
A
1.1
0.8
max
0.1
1
b
p
0.4
0.3
IEC JEDEC EIAJ
b
1
0.7
0.5
cD
0.25
2.2
0.10
1.8
REFERENCES
E
1.35
1.15
e
1.3
1999 May 14 13
H
L
e
E
1
2.2
0.45
2.0
0.15
Qwv
p
0.23
0.13
0.2y0.10.21.15
EUROPEAN
PROJECTION
ISSUE DATE
97-05-21
Page 14
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
DEFINITIONS
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1999 May 14 14
Page 15
N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR
NOTES
1999 May 14 15
Page 16
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. SCA All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
1999 64
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 125004/00/03/pp16 Date of release: 1999 May 14 Document order number: 9397 750 05271
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