Datasheet AZ10LVE111EFNR2, AZ10LVE111EFN, AZ100LVE111EFNR2, AZ100LVE111EFN Datasheet (AZMIC)

Download

Page 1

AZ10LVE111E

AZ100LVE111E

ECL/PECL 1:9 Differential Clock Driver with Enable

1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

ARIZONA MICROTEK, INC.

FEATURES

• Operating Range of 3.0V to 5.5V

• Low Skew

• Guaranteed Skew Spec

• Differential Design

• Enable

• V

Output

• 75kΩ Internal Input Pulldown Resistors

• Direct Replacement for ON Semiconductor

MC10E111 & MC100E111

DESCRIPTION

The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH.

The AZ100LVE111E provides a V

output for single-ended use or a DC bias reference for AC coupling to the

device. For single–ended input applications, the V

reference should be connected to one side of the IN/IN¯¯

differential input pair. The input signal is then fed to the other IN/IN¯¯ input. The V

pin should be used only as a

bias for the AZ100LVE111E as its current sink/source capability is limited. When used, the V

pin should be bypassed to ground via a 0.01µF capacitor. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate within-device skew, and empirical modeling is used to determine process control limits that ensure consistent t

distributions from lot-to-lot. The net result is a dependable, guaranteed low

skew device.

To ensure that the tight skew specification is met, both sides of the differential output must be terminated into 50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same V

CCO

) as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.

NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

PACKAGE AVAILABILITY

PACKAGE PART NO. MARKING

PLCC 28 AZ10LVE111EFN AZM10LVE111E PLCC 28 T&R AZ10LVE111EFNR2 AZM10LVE111E PLCC 28 AZ100LVE111EFN AZM100LVE111E PLCC 28 T&R AZ100LVE111EFNR2 AZM100LVE111E

Page 2

AZ10LVE111E AZ100LVE111E

March 2002 * REV - 3 www.azmicrotek.com 2

Absolute Maximum Ratings are those values beyond which device life may be impaired.

Symbol Characteristic Rating Unit

VCC PECL Power Supply (VEE = 0V) 0 to +8.0 Vdc

VI PECL Input Voltage (V

= 0V) 0 to +6.0 Vdc

VEE ECL Power Supply (VCC = 0V) -8.0 to 0 Vdc

VI ECL Input Voltage (VCC = 0V) -6.0 to 0 Vdc

OUT

Output Current --- Continuous

--- Surge

100

TA Operating Temperature Range -40 to +85

°C

STG

Storage Temperature Range -65 to +150

°C

10K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = V

CCO

= GND)

-40°C 0°C 25°C 85°C

Symbol Characteristic

Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Unit

VOH Output HIGH Voltage1 -1080 -890 -1020 -840 -980 -810 -910 -720 mV VOL Output LOW Voltage1 -1950 -1650 -1950 -1630 -1950 -1630 -1950 -1595 mV VIH Input HIGH Voltage -1230 -890 -1170 -840 -1130 -810 -1060 -720 mV VIL Input LOW Voltage -1950 -1500 -1950 -1480 -1950 -1480 -1950 -1445 mV VBB Reference Voltage -1430 -1300 -1380 -1270 -1350 -1250 -1310 -1190 mV IIH

Input HIGH Current 150 150 150 150

µA

IIL

Input LOW Current 0.5 0.5 0.5 0.5

µA

IEE Power Supply Current 48 60 48 60 48 60 48 60 mA

1. Each output is terminated through a 50Ω resistor to VCC – 2V.

LOGIC SYMBOL

Q2 Q2

Q4 Q4

Q5 Q5

Q6 Q6

Q0 Q0 Q1 Q2

CCO

Q1 Q2

CCO

Q6Q6Q7

CCO

Q8Q8

25 24 23 22 21 20 19

111098765

PIN DESCRIPTION

PIN FUNCTION

IN, IN¯¯ Differential Input Pair EN¯¯ Enable Q0, Q0¯¯ - Q8, Q8¯¯ Differential Outputs VBB V

Output

VCC , V

CCO

Positive Supply

Negative Supply

NC No Connect

Pinout: 28-Lead

PLCC (top view)

Page 3

AZ10LVE111E AZ100LVE111E

March 2002 * REV - 3 www.azmicrotek.com 3

10K LVPECL DC Characteristics (V

= GND, VCC = V

CCO

= +3.3V)

-40°C 0°C 25°C 85°C

Symbol Characteristic

Min T

Max Min T

Max

Unit

VOH Output HIGH Voltage

1,2

2220 2410 2280 2460 2320 2490 2390 2580 mV

VOL Output LOW Voltage

1,2

1350 1650 1350 1670 1350 1670 1350 1705 mV VIH Input HIGH Voltage1 2070 2410 2130 2460 2170 2490 2240 2580 mV VIL Input LOW Voltage1 1350 1800 1350 1820 1350 1820 1350 1855 mV VBB Reference Voltage1 1870 2000 1920 2030 1950 2050 1990 2110 mV IIH Input HIGH Current 150 150 150 150

µA

IIL

Input LOW Current 0.5 0.5 0.5 0.3

µA

IEE Power Supply Current 48 60 48 60 48 60 48 60 mA

1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value

2. Each output is terminated through a 50Ω resistor to V

– 2V.

10K PECL DC Characteristics (VEE = GND, VCC = V

CCO

= +5.0V)

-40°C 0°C 25°C 85°C

Symbol Characteristic

Min T

Max Min T

Max

Unit

VOH Output HIGH Voltage

1,2

3920 4110 3980 4160 4020 4190 4090 4280 mV

VOL Output LOW Voltage

1,2

3050 3350 3050 3370 3050 3370 3050 3405 mV VIH Input HIGH Voltage1 3770 4110 3830 4160 3870 4190 3940 4280 mV VIL Input LOW Voltage1 3050 3500 3050 3520 3050 3520 3050 3555 mV VBB Reference Voltage1 3570 3700 3620 3730 3650 3750 3690 3810 mV IIH Input HIGH Current 150 150 150 150

µA

IIL

Input LOW Current 0.5 0.5 0.5 0.3

µA

IEE Power Supply Current 48 60 48 60 48 60 48 60 mA

1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.

2. Each output is terminated through a 50Ω resistor to V

– 2V.

100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = V

CCO

= GND)

-40°C 0°C 25°C 85°C

Symbol Characteristic

Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Unit

VOH Output HIGH Voltage1 -1085 -1005 -880 -1025 -955 -880 -1025 -955 -880 -1025 -955 -880 mV VOL Output LOW Voltage1 -1830 -1695 -1555 -1810 -1705 -1620 -1810 -1705 -1620 -1810 -1705 -1620 mV VIH Input HIGH Voltage -1165 -880 -1165 -880 -1165 -880 -1165 -880 mV VIL Input LOW Voltage -1810 -1475 -1810 -1475 -1810 -1475 -1810 -1475 mV VBB Reference Voltage -1380 -1260 -1380 -1260 -1380 -1260 -1380 -1260 mV IIH

Input HIGH Current 150 150 150 150

µA

IIL

Input LOW Current 0.5 0.5 0.5 0.5

µA

IEE Power Supply Current 48 60 48 60 48 60 55 69 mA

1. Each output is terminated through a 50Ω resistor to VCC – 2V.

100K LVPECL DC Characteristics (VEE = GND, VCC = V

CCO

= +3.3V)

-40°C 0°C 25°C 85°C

Symbol Characteristic

Min T

Max Min T

Max

Unit

VOH Output HIGH Voltage

1,2

2215 2295 2420 2275 2345 2420 2275 2345 2420 2275 2345 2420 mV

VOL Output LOW Voltage

1,2

1470 1605 1745 1490 1595 1680 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage1 2135 2420 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage1 1490 1825 1490 1825 1490 1825 1490 1825 mV VBB Reference Voltage1 1920 2040 1920 2040 1920 2040 1920 2040 mV IIH Input HIGH Current 150 150 150 150

µA

IIL

Input LOW Current 0.5 0.5 0.5 0.5

µA

IEE Power Supply Current 48 60 48 60 48 60 55 69 mA

1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.

2. Each output is terminated through a 50Ω resistor to V

– 2V.

Page 4

AZ10LVE111E AZ100LVE111E

March 2002 * REV - 3 www.azmicrotek.com 4

100K PECL DC Characteristics (V

= GND, VCC = V

CCO

= +5.0V)

-40°C 0°C 25°C 85°C

Symbol Characteristic

Min T

Max Min T

Max

Unit

VOH Output HIGH Voltage

1,2

3915 3995 4120 3975 4045 4120 3975 4045 4120 3975 4045 4120 mV

VOL Output LOW Voltage

1,2

3170 3305 3445 3190 3295 3380 3190 3295 3380 3190 3295 3380 mV VIH Input HIGH Voltage1 3835 4120 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage1 3190 3525 3190 3525 3190 3525 3190 3525 mV VBB Reference Voltage1 3620 3740 3620 3740 3620 3740 3620 3740 mV IIH Input HIGH Current 150 150 150 150

µA

IIL

Input LOW Current 0.5 0.5 0.5 0.5

µA

IEE Power Supply Current 48 60 48 60 48 60 55 69 mA

1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.

2. Each output is terminated through a 50Ω resistor to V

– 2V.

AC Characteristics (V

= -3.0V to -5.5V, VCC = V

CCO

= GND or V

= GND, VCC = V

CCO

= +3.0 to +5.5V)

-40°C 0°C 25°C 85°C

Symbol Characteristic

Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Unit

PLH

/ t

PHL

Propagation Delay to Output IN (Diff)

IN (SE)

Enable

Disable

380 280 400 400

650 700 900 900

460 410 450 450

560 610 850 850

480 430 450 450

580 630 850 850

510 460 450 450

610 660 850 850

tS Setup Time EN¯¯ to IN5 250 0 200 0 200 0 200 0 ps tH Hold Time IN to EN¯¯6 50 -200 0 -200 0 -200 0 -200 ps tR Release Time EN¯¯ to IN7 350 100 300 100 300 100 300 100 ps t

skew

Within-Device Skew4 25 75 25 50 25 50 25 50 ps

(AC) Minimum Input Swing8 250 250 250 250 mV

CMR

Common Mode Range9

1.8

0.4

1.8

0.4

1.8

0.4

1.8

0.4

tr / tf Rise/Fall Time 250 650 275 600 275 600 275 600 ps

1. The differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals.

2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.

3. Enable is defined as the propagation delay from the 50% point of a negative transition on EN¯¯ to the 50% point of a positive transition on Q (or a negative transition on Q¯ ). Disable is defined as the propagation delay from the 50% point of a positive transition on EN¯¯ to the 50% point of a negative transition on Q (or a positive transition on Q¯).

4. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device.

5. The setup time is the minimum time that EN¯¯ must be asserted prior to the next transition of IN/IN¯¯ to prevent an output response greater than ±75mV to that IN/IN¯¯ transition (see Figure 1).

6. The hold time is the minimum time that EN¯¯ must remain asserted after a negative going IN or a positive going IN¯¯ to prevent an output response greater than ±75 mV to that IN/IN¯¯ transition (see Figure 2).

7. The release time is the minimum time that EN¯¯ must be de-asserted prior to the next IN/IN¯¯ transition to ensure an output response that meets the specified IN to Q propagation delay and output transition times (see Figure 3).

8. V

is defined as the minimum peak-to-peak differential input swing for which AC parameters are guaranteed. The VPP(min) is AC limited for the

LVE111E, because differential input as low as 50 mV will still produce full ECL levels at the output.

9. V

CMR

is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level

must be such that the peak-to-peak voltage is less than 1.0 V and greater than or equal to V

(min).

IN IN

Page 5

AZ10LVE111E AZ100LVE111E

March 2002 * REV - 3 www.azmicrotek.com 5

PACKAGE DIAGRAM

PLCC 28

MILLIMETERS INCHES

DIM

MIN MAX MIN MAX

12.32 12.57 0.485 0.495

4.20 4.57 0.165 0.180

2.29 2.79 0.090 0.110

0.33 0.48 0.013 0.019

1.27 BSC 0.050 BSC

0.66 0.81 0.026 0.032

0.51 0.020

0.64 0.025

11.43 11.58 0.450 0.456

1.07 1.21 0.042 0.048

1.07 1.42 0.042 0.056

0.50 0.020

10O 2

10O

10.42 10.92 0.410 0.430

1.02 0.040

OTES:

1. DATUMS –L-, -M-, AND –N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T-, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALOWABLE MOLD FLASH IS

0.010mm (0.250in.) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKGE BOTTOM BY UP TO 0.012mm (0.300in.). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, THE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025mm (0.635in.).

Page 6

AZ10LVE111E AZ100LVE111E

March 2002 * REV - 3 www.azmicrotek.com 6

Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or

sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a

situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,

damages, and expenses, and reasonable attorney fees arising out of, directly

or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges tha

Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.