Datasheet AZ1065-06Q Datasheet (Amazing Microelectronic)

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Page 1

Features



ESD Protect for

Signaling (above 5Gb/s)



Protects six I/O lines and one VDD line



Provide ESD protection for each channel to

IEC 61000-4-2, (ESD) ±15kV (air), ±8kV (contact)



For 5V and below 5V operating voltage



Ultra low capacitance: 0.35pF max.



Fast turn-on and Low clamping voltage



Array of surge rated diodes with internal

Super Speed Differential

channels

equivalent TVS diode



Solid-state silicon-avalanche and active circuit triggering technology



Back-drive protection for power-down mode



Green part

Applications



USB3.0



High Speed I/O Ports in Any Electronic Product

Description

AZ1065-06Q

Ultra Low Capacitance ESD Protection Array

For High Speed I/O Port

AZ1065-06Q is a design which includes surge rated diode arrays to protect high speed data interfaces. The AZ1065-06Q has been specifically designed to protect sensitive components which are connected to data and transmission lines from over-voltage caused by Electrostatic Discharging (ESD). AZ1065-06Q is a unique design which includes surge rated, ultra low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. Besides, there is a back-drive protection design in AZ1065-06Q for power-down mode operation. AZ1065-06Q may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge).

Circuit Diagram

1 2 3 4

5 6

Pin Configuration

I/O-1

I/O-2

I/O-3

I/O-4

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MSOP-8L (Top View)

VDD

GND

I/O-6

I/O-5

Page 2

SPECIFICATIONS

PARAMETER PARAMETER RATING UNITS

Ultra Low Capacitance ESD Protection Array

ABSOLUTE MAXIMUM RATINGS

AZ1065-06Q

For High Speed I/O Port

Operating Supply Voltage (VDD-GND) ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) Lead Soldering Temperature Operating Temperature Storage Temperature DC Voltage at any I/O pin

VDC

ESD

SOL

TOP

STO

VIO

(GND – 0.5) to (VDD + 0.5)

±15

±8

260 (10 sec.)

-40 to +85

-55 to +150

ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL

Reverse Stand-Off Voltage Reverse Leakage Current Channel Leakage Current Reverse Breakdown Voltage

Pin 8 to pin 7, T=25 oC 5 V

RWM

Leak

CH-Leak

VBV IBV = 1mA, T=25 oC, Pin 8 to Pin 7 6 V

= 5V, T=25 oC, Pin 8 to pin 7 2.5

RWM

= 5V, V

Pin 8

CONDITIONS

= 0V, T=25 oC 1 µµµµA

Pin 7

MIN TYP MAX UNITS

Forward Voltage VF IF = 15mA, T=25 oC, Pin 7 to Pin 8 0.8 1.2 ESD Clamping Voltage –I/O ESD Clamping Voltage –VDD ESD Dynamic Turn-on Resistance –I/O ESD Dynamic Turn-on Resistance –VDD Channel Input Capacitance-1 Channel Input Capacitance-2

Channel to Channel Input Capacitance

clamp_io

clamp_VDD

dynamic_io

dynamic_VDD

IN_1

IN_2

CROSS

IEC 61000-4-2 +6kV,T=25 oC,Contact mode, Any Channel pin to Ground IEC 61000-4-2 +6kV, T=25 oC, Contact mode, VDD pin to Ground IEC 61000-4-2, 0~+6kV,T=25 oC, Contact mode,Any Channel pin to Ground

IEC 61000-4-2, 0~+6kV, T=25 oC, Contact mode, VDD pin to Ground

= 5V,V

pin8

1MHz, T=25 oC, pin 1~4 to pin 7. V

= 5V,V

pin8

1MHz, T=25 oC, pin 5~6 to pin 7. V

= 5V, V

pin8

1MHz, T=25 oC , Between Channel

pin7

= 0V,V

= 0V, V

= 2.5V,f =

= 2.5V, f =

pins

13 V

10 V

0.35

0.2

0.27 0.35

0.32 0.4

0.05 0.07

µµµµA

ΩΩΩΩ

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Page 3

Typical Characteristics

AZ1065-06Q

Ultra Low Capacitance ESD Protection Array

For High Speed I/O Port

0.50

f = 1MHz, T=25 oC,

0.45

0.40

0.35

0.30

Input Capacitance (pF)

0.25

0.20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Typical Variation of CIN vs. V

VDD=Floated, Pin 5~6

VDD=5V, Pin 5~6

VDD=5V, Pin 1~4

Input Voltage (V)

VDD=Floated, Pin 1~4

insertion Loss S21 (I/O-to-GND)

-3

-6

-9

-12

-15

-18

-21

Insertion Loss (dB)

-24

-27

-30 1e+8 1e+9

VDD=5V

VDD=Floated

3.8GHz: -3dB

Frequency (Hz)

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

Input Capacitance (pF)

0.02

0.01

0.00

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Typical Variation of C

VDD=Floated

VDD=5V

Input Voltage (V)

vs. V

IO-to-IO

f = 1MHz, T=25 oC,

-10

-20

-30

-40

Analog Cross Talk (dB)

-50

-60 1e+8 1e+9

Analog Cross Talk

VDD=5V VDD=Floated

Frequency (Hz)

Transmission Line Pulsing (TLP) Measurement

18 16 14 12 10

8 6 4 2 0

Transmission Line Pulsing (TLP) Current (A)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

V_pulse

Pulse from a

transmission line

100ns

Transmission Line Pulsing (TLP) Voltage (V)

VDD to GND

TLP_I

DUT

TLP_V

I/O to GND

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Page 4

Applications Information

A. Design Considerations

The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are general used to protect data line from ESD stress pulse. The diode D3 is a back-drive protection design, which blocks the DC back-drive current when the potential of I/O pin is greater than that of VDD pin. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (I current path1. Thus, the ESD clamping voltage VCL of data line can be described as follow:

VCL = Fwd voltage drop of D1 + Breakdown

voltage drop of D3 + supply voltage of VDD rail + L1 × d(I

Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail.

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from

) will pass through the ESD

ESD1

)/dt + L2 × d(I

ESD1

)/dt

AZ1065-06Q

Ultra Low Capacitance ESD Protection Array

For High Speed I/O Port

zero to 30A in 1ns. Here d(I approximated by ∆I

/∆t, or 30/(1x10-9). So just

ESD1

10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded.

The AZ1065-06Q has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (I directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage VCL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current.

)/dt can be

ESD1

) will be

ESD2

power-rail ESD

clamp ing circuit

ESD2

AZ1065-06Q

ESD current path 1 (I ESD current path 2 (I

Fig. 1 Application of positive ESD pulse between data line and GND rail.

ESD1

data line

Protected

VDD rail

GND rail

VESD

)

ESD1

)

ESD2

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B. Device Connection

The AZ1065-06Q is designed to protect six data lines and one power rail from transient over-voltage (such as ESD stress pulse). The device connection of AZ1065-06Q is shown in the Fig. 2. In Fig. 2, the six protected data lines are connected to the ESD protection pins (pin1, pin2, pin3, pin4, pin5, and pin6) of AZ1065-06Q. The ground pin (pin7) of AZ1065-06Q is a negative reference pin. This pin should be directly connected to the GND rail of PCB (Printed Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. In addition, the power pin (pin 8) of AZ1065-06Q is a positive reference pin. This pin should directly connect to the VDD rail of PCB., then the VDD rail also can be protected by the power-rail ESD clamped circuit (not shown) of AZ1065-06Q.

AZ1065-06Q

Ultra Low Capacitance ESD Protection Array

For High Speed I/O Port

AZ1065-06Q can provide protection for 6 I/O signal lines simultaneously. If the number of I/O signal lines is less than 6, the unused I/O pins can be simply left as NC pins.

In some cases, systems are not allowed to be reset or restart after the ESD stress directly applying at the I/O-port connector. Under this situation, in order to enhance the sustainable ESD Level, a 0.1µF chip capacitor can be added between the VDD and GND rails. The place of this chip capacitor should be as close as possible to the AZ1065-06Q.

In some cases, there isn’t power rail presented on the PCB. Under this situation, the power pin (pin 8) of AZ1065-06Q can be left as floating. The protection will not be affected, only the load capacitance of I/O pins will be slightly increased. Fig. 3 shows the detail connection.

VDD rail

1 2 3 4

AZ1065-

06Q

8 7 6 5

GND

rail

*Optional

0.1µµµµF Chip Cap.

I/O-port

Connector

I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6

data line

data line data line data line

I/O 1

I/O 2 I/O 3

I/O 4 I/O 5

I/O 6

To Protected IC

Fig. 2 Data lines and power rails connection of AZ1065-06Q.

VDD

floated

GND

rail

6 5

I/O 1

I/O 2

I/O 3

Protected IC

I/O 4 I/O 5

I/O 6

I/O-port

Connector

I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6

1 2 3 4

AZ1065-

06Q

data line

data line data line

Fig. 3 Data lines and power rails connection of AZ1065-06Q. VDD pin is left as floating when no

power rail presented on the PCB.

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Page 6

C. Application

AZ1065-06Q is designed for protecting high speed I/O ports from over-voltage caused by Electrostatic Discharging (ESD). Thus, a lot of kinds of high speed I/O ports can be the applications of AZ1065-06Q, especially, the USB3.0 port.

USB3.0 Protection for Super Speed Differential signals

USB3.0 is expected to transmit and receive above 5Gb/s data, which needs differential signaling. For differential signaling, keep the differential impedance at constant is the most importance.

ESD protection devices have an inherent

AZ1065-06Q

Ultra Low Capacitance ESD Protection Array

For High Speed I/O Port

junction capacitance. Usually, this added capacitance on an USB3.0 port will cause the impedance of the differential pair to drop to interfere with the signaling. The AZ1065-06Q presents only differential signal while being rated to handle 8kV ESD contact/air discharges as outlined in IEC 61000-4-2 and providing a low clamping voltage to protect the downstream devices.

Therefore, AZ1065-06Q is the most suitable ESD protector for USB3.0 I/O port and other high speed, above 5Gb/s, I/O ports in any electronic product. Fig.4 shows the PCB layout example for USB3.0 I/O port. Fig. 5 shows the 5GHz Eye Diagram when the AZ1065-06Q is used. No degradation is observed.

0.35pF

max. capacitance to each

Fig. 4 USB3.0 ESD Protection by using AZ1065-06Q.

Fig. 5 The 5GHz Eye Diagram when AZ1065-06Q is used.

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Page 7

PACKAGE OUTLINE

AZ1065-06Q

Ultra Low Capacitance ESD Protection Array

For High Speed I/O Port

Symbol

Millimeters Inches

min max min max

A 0.800 1.200 0.031 0.047 A1 0.000 0.200 A2 0.750 0.970

b 0.280 0.380

C 0.130 0.230 D 2.900 3.100

0.000 0.008

0.030 0.038

0.011 0.015

0.005 0.009

0.114 0.122

e 0.65 BASIC 0.026 BASIC

E 4.700 5.100

E1 2.900 3.100

L 0.400 0.700

θ 0∘ 8∘ 0∘ 8∘

0.185 0.201

0.114 0.122

0.016 0.028

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Page 8

LAND LAYOUT

AZ1065-06Q

Ultra Low Capacitance ESD Protection Array

Dimensions

Index Millimeter Inches

For High Speed I/O Port

Notes: This LAND LAYOUT is for reference purposes only. Please consult your manufacturing partners to ensure your company’s PCB design guidelines are met.

MARKING CODE

A B C D

Part Number Marking Code

0.41 0.016

1.02 0.040

0.65 0.023

4.8 0.189

118

1065Q YWXXG

YWXXG

AZ1065-06Q

118

118 = Device Code YW = Date Code XX = Control Code G = Green part

AZ1065-06Q (Engineering

Sample)

1065Q

Ordering Information

PN# Material Type Reel size MOQ/interal box MOQ/carton

AZ1065-06Q.RDG Green T/R 13 inch 1 reel= 3,000/box 5 box =15,000/carton

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Page 9

Ultra Low Capacitance ESD Protection Array

Revision History

Revision Modification Description

Revision 2008/10/13 Preliminary Release. Revision 2008/10/28 Add Land Layout Information. Revision 2009/03/12 Add Typical Characteristics. Revision 2009/06/24 Formal Release. Revision 2009/12/26 Update the PACKAGE DIMENSIONS.

AZ1065-06Q

For High Speed I/O Port

Revision 2011/06/18

1. Update the Company Logo.

2. Add the Ordering Information.

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