Page 1
0
100BASE-TX/FX Repeater Controlle
r
A
S
I
X
ASIX AX88850
100BASE-TX/FX
AX8885
Repeater Controller
Data Sheet(11/03/’97)
DOCUMENT NO. : AX850D2.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558
Page 2
AX88850 PRELIMINARY
CONTENTS
1.0 AX88850 OVERVIEW......................................................................................................................................... 5
1.1 GENERAL DESCRIPTION ....................................................................................................................................... 5
1.2 FEATURES............................................................................................................................................................ 6
1.3 BLOCK DIAGRAM................................................................................................................................................. 7
1.4 PIN CONNECTION DIAGRAM FOR AX88851 (16MII + 2MII MODE) .................................................................... 8
1.5 PIN CONNECTION DIAGRAM FOR AX88852 (8MII + 2MII MODE) ...................................................................... 9
1.6 PIN CONNECTION DIAGRAM FOR AX88853 (8PCS + 2MII MODE) ................................................................... 10
1.7 PIN CONNECTION DIAGRAM FOR AX88854 (MANAGEMENT MODE).................................................................. 11
2.0 PIN DESCRIPTION........................................................................................................................................... 12
2.1A PCS INTERFACE ............................................................................................................................................. 12
2.1B MII INTERFACE (SHARE BUS MII GROUP 0 PORT & MII GROUP 1 PORT)........................................................ 13
2.2 MII INTERFACE ( TWO INDIVIDUAL MII PORTS )............................................................................................... 14
2.3 STATION MANAGEMENT INTERFACE.................................................................................................................. 15
2.4 MANAGEMENT INFORMATION BASE (MIB) INTERFACE..................................................................................... 15
2.5 EXPANSION BUS INTERFACE .............................................................................................................................. 16
2.7 MISCELLANEOUS ............................................................................................................................................... 19
3.0 FUNCTIONAL DESCRIPTION...................................................................................................................... 20
3.1 PCS INTERFACE LOGIC ...................................................................................................................................... 20
3.2 CARRIER INTEGRITY MONITOR STATE MACHINE ( AX88853 PCS MODE ONLY ).............................................. 20
3.3 REPEATER STATE MACHINE .............................................................................................................................. 20
3.4 JABBER STATE MACHINE................................................................................................................................... 21
3.5 PARTITION STATE MACHINE.............................................................................................................................. 21
3.6 EXPANSION LOGIC(CASCADE INTERFACE)......................................................................................................... 22
3.7 MANAGEMENT LOGIC........................................................................................................................................ 22
3.8 MANAGEMENT COUNTERS................................................................................................................................. 23
3.9 STATION MANAGEMENT ACCESS INTERFACE .................................................................................................... 23
3.10 RID RECEIVE-TRANSMIT INTERFACE(DAISY CHAIN LOGIC)........................................................................... 23
3.11 LED INTERFACE.............................................................................................................................................. 25
3.11.1 LED Status Driver wave-form for AX88851............................................................................................ 25
3.11.2 LED Status Driver wave-form for AX88852............................................................................................ 26
3.11.3 LED Status Driver wave-form for AX88853............................................................................................ 26
3.11.4 LED Status Driver wave-form for AX88854............................................................................................ 27
3.12 POWER ON CONFIGURATION(INITIAL SETTING)............................................................................................... 27
4.0 REGISTERS........................................................................................................................................................ 28
4.1 PAGE 0 REGISTER MAP..................................................................................................................................... 28
4.2 PAGE 1 REGISTER MAP..................................................................................................................................... 29
4.3 PAGE 2 REGISTER MAP..................................................................................................................................... 29
4.4 PAGE 3 REGISTER MAP..................................................................................................................................... 29
4.5 CONFIGURATION REGISTER (CONFIG) ............................................................................................................. 30
4.6 PAGE REGISTER (PAGE) ................................................................................................................................... 30
4.7 PARTITION STATUS REGISTER (PARTITION)................................................................................................... 31
4.8 JABBER STATUS REGISTER (JABBER) .............................................................................................................. 31
4.9 ADMINISTRATION REGISTER (ADMIN)............................................................................................................. 31
4.10 DEVICE ID REGISTER (DEVICEID) ................................................................................................................ 32
4.11 SILICON REVISION REGISTER........................................................................................................................... 32
4.12 PORT MANAGEMENT COUNTER REGISTERS ..................................................................................................... 33
4.12.1 Short Event Counter Registers................................................................................................................. 33
4.12.2 Late Event Counter Registers .................................................................................................................. 33
4.12.3 Collision Counter Registers..................................................................................................................... 33
4.12.4 Auto-Partition Counter Registers............................................................................................................ 33
4.12.5 False Carrier Counter Registers.............................................................................................................. 33
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ASIX ELECTRONICS CORPORATION
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AX88850 PRELIMINARY
5.0 ELECTRICAL SPECIFICATION AND TIMING ......................................................................................... 34
5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 34
5.2 GENERAL OPERATION CONDITIONS ................................................................................................................... 34
5.3 DC CHARACTERISTICS ...................................................................................................................................... 34
5.4 AC SPECIFICATIONS........................................................................................................................................... 35
5.4.1 MII Interface Timing Tx & Rx................................................................................................................... 35
5.4.2 Station Management ................................................................................................................................. 36
5.4.3 PCS Interface Timing................................................................................................................................. 37
5.4.4 LED DISPLAY ........................................................................................................................................... 37
5.4.5 LED Display After Reset........................................................................................................................... 38
5.4.6 Repeater ID Daisy Chain........................................................................................................................... 38
5.4.7 Expansion Bus............................................................................................................................................ 39
6.0 PACKAGE INFORMATION............................................................................................................................ 40
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ASIX ELECTRONICS CORPORATION
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AX88850 PRELIMINARY
FIGURES
FIG - 1 CHIP BLOCK DIAGRAM (PCS MODE CONFIGURATION -- 8 PCS + 2 MII).....................................................................7
FIG - 2 CHIP BLOCK DIAGRAM(MII MODE CONFIGURATION -- 16 MII + 2 MII) .....................................................................7
FIG - 3 PIN CONNECTION DIAGRAM FOR 16MII MODE............................................................................................................8
FIG - 4 PIN CONNECTION DIAGRAM FOR 8MII MODE..............................................................................................................9
FIG - 5 PIN CONNECTION DIAGRAM FOR 8PCS MODE..........................................................................................................10
FIG - 6 PIN CONNECTION DIAGRAM FOR MANAGEMENT MODE.............................................................................................11
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ASIX ELECTRONICS CORPORATION
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AX88850 PRELIMINARY
1.0 AX88850 Overview
The AX88850 series 100Mbps Repeater Controllers are designed for both low cost
dumb HUB and high performance intelligent HUB applications. The AX88850 series
product support up-to ten 100Mbps links with its 8 PCS (Physical coding sub-layer , also
called Symbol Interface) interfaces and 2 dedicated MII interfaces or supports up-to eighteen
100Mbps links with 2 shared 8 ports MII interfaces and 2 dedicated MII interfaces.
Maximum up-to 144 ports can be constructed when using expansion bus cascades 8
AX88850s. The AX88850 is designed base on IEEE 802.3u clause 27 “ Repeater for
100Mb/s base-band networks” . It is fully compatible with IEEE 802.3u standard.
1.1 General Description
The AX88850 Repeater Controller is a subset of a repeater set containing all the
repeater-specific components and functions, exclusive of PHY components and functions.
The AX88850 family has two kind of interfaces to connect to PHY devices. There are
Physical coding sub-layer (PCS) interface and Media Independent Interface (MII).
The AX88850 supports 8 PCS ports interface or 2 shared bus (8 ports/per bus) MII
interfaces, 2 dedicated MII ports interface, an expansion port interface, a management
information base IC interface, a repeater ID daisy chain interface, a serial register interface
and LED display interface.
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ASIX ELECTRONICS CORPORATION
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AX88850 PRELIMINARY
1.2 Features
• IEEE 802.3u repeater compatible
• Supports 10 or 18 network connections optional configuration.
• 8 PCS interfaces direct interface to PHY chip with PCS interface ( ie.LUC3X04,
KS8761, QSI6611, NWK914 ) to save user cost
• 16 MII interfaces to double the network connections.
• 2 dedicated MII interfaces can also support 100BASE-T4/FX PHY interfaces
• The 2 dedicated MII interfaces can also easily connect to MII interface of 100BASE
MAC controller for network management purpose or other bridging devices.
• Up-to 8 repeater chips can be cascaded for large HUB application
• Low latency design supports Class II repeater implementation with large port number.
• All ports can be separately isolated or partitioned in response to fault condition
• Separate jabber and partition state machines for each port
• Separate carrier integrity monitor state machines for each port to protect network from
some transient fault conditions (AX88853 PCS mode only)
• Management interface for AX88856 (MIB IC) allows all repeater MIBs to be maintained
• Large per-port management counters to reduce CPU overhead
• External pins setup or automatic daisy chain channel setup repeater ID.
• Per-port LED display for Jabber, Partition, Link/Activity. Global utilization and
collision (%) presentation.
• Power on LED diagnosis. All the LED display will follow the “ON-OFF-ON-OFF-
Normal” operation procedure during/after power on reset.
• Dedicated collision LED display
• 208-pin PQFP
The AX88850 Family has the following members:
AX88851 16 shared MII ports + 2 dedicated MII ports
AX88852 8 shared MII ports + 2 dedicated MII ports
AX88853 8 PCS (Symbol) Interface ports + 2 dedicated MII ports
AX88854 AX88851 + AX88853 + management function
AX88856 MIB co-processor for intelligent Hub applications
Function availability list
Parts Number 16MII + 2MII 8MII + 2MII 8PCS + 2MII Management I/F
AX88851
AX88852
AX88853
AX88854
4
4
4
4 4 4 4
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ASIX ELECTRONICS CORPORATION
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AX88850 PRELIMINARY
1.3 Block Diagram
Q -P H Y
Q -P H Y
P H Y
P H Y
sy m
I/F
M II
I/F
4B /5 B
C od in g/
D ec od i n g
&
S r r am b l e r /
D es cr am b l e r
(P o r t 1 P o rt 7 )
R ec on c ilia ti o n
P o rt 8 P o rt 9
P e r po r t J ab b er ctl,
au to -p artitio n S M &
P e r po r t C o llis io n ,
P a rtit i o n co u nte r s.
........
M U X
E l a st i c ity B u ffe r
R ep ea t e r Sta t e
M a c hin e
R eg is t e rs M IB I/F
C asca de
A rb it r atio n
L o gic
C oll is io n H a n dlin g L og ic
Fig - 1 Chip Block Diagram (PCS mode configuration -- 8 PCS + 2 MII)
M II
Q -P HY
Q -P HY
Q -P HY
Q -P HY
I/F
M II
I/F
M II
in t e r fa c e
Re c o nc ilia tion lay e r
Port 0 Port 7
M II
in t e r fa c e
Re c o nc ilia tion lay e r
Port 10 Port 17
Per po r t J a bb er ctl,
auto-par titio n S M &
Per po r t C ollisio n ,
Partitio n c ou nters.
........
M UX
Re p ea ter S ta te
M ach in e
Re g iste r s M IB I/F
Ca s c a de
Ar b itratio n
Lo g ic
PH Y
PH Y
M II
I/F
M II
Port 8
Port 9
Elastic ity B u ffer
Co llis ion H and ling L og ic
Fig - 2 Chip Block Diagram(MII mode configuration -- 16 MII + 2 MII)
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ASIX ELECTRONICS CORPORATION
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AX88850 PRELIMINARY
1.4 Pin Connection Diagram for AX88851 (16MII + 2MII mode)
LED_SYN
LED<5>
LED<4>
LED<6>
LED<7>
124
123
125
126
31
3233343536373839404142
122
LED<3>
VSS
121
120
LED<1>
LED<2>
118
119
NC
LED<0>
NC
117
115
116
VSS
NCNCNC
114
112
113
4347464445
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
NC
NC
NC
NC
NC
NC
NC
VDD1
VSS1
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
M0_CRS1
M0_CRS2
M0_CRS3
NC
NC
NC
VSS
M0_RXEN1
M0_RXEN2
M0_RXEN3
M0_TXEN4
M0_TXEN5
M0_CRS4
M0_CRS5
M0_CRS6
M0_CRS7
NC
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDD
156
1
MD
155
IRD_ODIR
/IR_ACTO<6>
/IR_ACTO<7>
VSS
153
151
152
154
56472
3
/IR_ACTO<5>
/IR_ACTO<2>
/IR_ACTO<4>
/IR_ACTO<3>
/IR_ACTO<1>
146
147
150
148
149
8
9
101112131415161718
/IR_ACTI<3>
/IR_ACTI<2>
/IR_ACTI<1>
/IR_ACTI<6>
/IR_ACTI<7>
/IR_ACTI<5>
VSS
/IR_ACTO<0>
145
141
142
144
143
RID<2>
RID<1>
RID<0>
/IR_ACTI<0>
/IR_ACTI<4>
138
136
137
139
140
RID<3>
RID<4>
/DIS_DAISY
/IR_ACT_EN
/TO_ID_CLR
RST_DLY
DAISY_OUT
VDD1
DAISY_IN
133
134
135
132
VSS1
131
MEDIA
OPTION
129
130
VDD
/COLLED
127
128
ASIX
AX 88851
(16 MII Mode)
19
2324222021
25
293028
26
27
111
NC
110
MTX_RDY
RX_DV<1>
CRS<1>
OPT1
106
107
108
109
4849505152
RX_CLK<1>
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
M1_RXEN7
M1_RXEN6
M1_RXEN5
M1_RXEN4
M1_TXEN7
VDD
NC
NC
NC
NC
NC
NC
NC
M1_TXEN6
M1_TXEN5
M1_TXEN4
M1_RXEN3
M1_RXEN2
VSS
M1_RXEN1
NC
NC
M1_CRS7
M1_CRS6
M1_CRS5
M1_CRS4
VDD
NC
M0_RXEN4
M0_RXEN5
M0_TXEN6
M0_TXEN7
M1_TXER
M1_TXD1
M1_TXD2
M1_TXD3
VSS
VSS
M0_RXD0
M0_RXEN6
M0_RXEN7
M0_RXD1
M0_RXD2
M0_RXD3
M0_RXER
VDD
M0_TXD0
M0_TXD1
M0_RXDV
M0_RX_CLK
M0_TXER
M0_TXD2
M0_TXD3
VSS
M1_RXD1
M1_RXD0
VSS1
VDD1
M1_RXD2
M1_RXD3
M1_RXER
M1_RXCLK
VDD
M1_TXD0
M1_RXDV
Fig - 3 Pin Connection Diagram for 16MII Mode
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ASIX ELECTRONICS CORPORATION
M1_CRS0
M1_CRS1
M1_CRS2
NCNCNC
M1_CRS3
M1_TXEN0
M1_TXEN1
M1_TXEN2
M1_TXEN3
VDD
M1_RXEN0
Page 9
AX88850 PRELIMINARY
1.5 Pin Connection Diagram for AX88852 (8MII + 2MII mode)
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
NC
NC
NC
NC
NC
NC
NC
VDD1
VSS1
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
M0_CRS1
M0_CRS2
M0_CRS3
NC
NC
NC
VSS
M0_RXEN1
M0_RXEN2
M0_RXEN3
NC
NC
NC
NC
NC
NC
NC
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDD
156
1
MD
155
IRD_ODIR
/IR_ACTO<7>
/IR_ACTO<6>
VSS
153
151
152
154
56472
3
/IR_ACTO<5>
/IR_ACTO<2>
/IR_ACTO<4>
/IR_ACTO<3>
/IR_ACTO<1>
146
147
150
148
149
8
9
101112131415161718
/IR_ACTI<6>
/IR_ACTI<7>
/IR_ACTI<5>
/IR_ACTO<0>
VSS
145
141
142
144
143
RID<2>
RID<1>
RID<0>
/IR_ACTI<3>
/IR_ACTI<4>
/IR_ACTI<2>
/IR_ACTI<1>
/IR_ACTI<0>
138
136
137
139
140
RID<3>
RID<4>
/DIS_DAISY
/IR_ACT_EN
/TO_ID_CLR
DAISY_OUT
RST_DLY
VDD1
DAISY_IN
133
134
135
132
VSS1
131
MEDIA
VDD
OPTION
129
130
/COLLED
127
128
LED_SYN
LED<6>
LED<7>
124
125
126
LED<5>
LED<4>
122
123
ASIX
AX 88852
(8 MII Mode)
25
293028
19
26
2324222021
31
27
3233343536373839404142
LED<3>
VSS
121
120
LED<1>
LED<0>
LED<2>
117
118
119
NC
116
NC
NCNCNC
114
115
4347464445
VSS
113
112
111
NC
110
RX_DV<1>
MTX_RDY
CRS<1>
OPT1
106
107
108
109
4849505152
RX_CLK<1>
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
NC
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M1_RXEN3
M1_RXEN2
VSS
M1_RXEN1
NC
NC
NC
NC
NC
NC
NC
NCNCNCNCNC
VDD
NC
VSS
M0_RXD0
M0_RXD1
M0_RXD2
M0_RXD3
VDD
M0_RXER
M0_RXDV
M0_RX_CLK
M0_TXD0
M0_TXD1
M0_TXD2
M0_TXD3
VSS
M0_TXER
M1_RXD1
M1_RXD0
VSS1
VDD1
M1_RXD2
M1_RXD3
VDD
M1_RXER
M1_RXDV
M1_RXCLK
M1_TXD0
M1_TXD1
M1_TXD2
M1_TXD3
VSS
M1_CRS0
M1_TXER
Fig - 4 Pin Connection Diagram for 8MII Mode
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ASIX ELECTRONICS CORPORATION
M1_CRS1
M1_CRS3
M1_CRS2
NCNCNC
M1_TXEN3
M1_TXEN0
M1_TXEN1
M1_TXEN2
VDD
M1_RXEN0
Page 10
AX88850 PRELIMINARY
1.6 Pin Connection Diagram for AX88853 (8PCS + 2MII mode)
LED<5>
LED<4>
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
RDATA<0><0>
RDATA<0><1>
RDATA<0><2>
RDATA<0><3>
RDATA<0><4>
TDATA<0><0>
TDATA<0><1>
TDATA<0><2>
TDATA<0><3>
TDATA<0><4>
RDATA<1><0>
RDATA<1><1>
RDATA<1><2>
RDATA<1><3>
RDATA<1><4>
TDATA<1><0>
TDATA<1><1>
TDATA<1><2>
TDATA<1><3>
TDATA<1><4>
RDATA<2><0>
RDATA<2><1>
RDATA<2><2>
RDATA<2><3>
RDATA<2><4>
VSS
RSCLK<0>
RSD<0>
VDD1
VSS1
RSCLK<1>
RSD<1>
VSS
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDD
156
1
MD
155
IRD_ODIR
/IR_ACTO<7>
/IR_ACTO<6>
VSS
153
151
152
154
56472
3
/IR_ACTO<5>
/IR_ACTO<2>
/IR_ACTO<4>
/IR_ACTO<3>
/IR_ACTO<1>
146
147
150
148
149
8
9
101112131415161718
/IR_ACTI<6>
/IR_ACTI<7>
VSS
/IR_ACTI<5>
/IR_ACTO<0>
145
141
142
144
143
RID<2>
RID<1>
RID<0>
/IR_ACTI<4>
140
RID<3>
RST_DLY
/IR_ACTI<3>
/IR_ACTI<2>
/IR_ACTI<1>
/IR_ACTI<0>
135
138
136
137
139
RID<4>
/DIS_DAISY
/IR_ACT_EN
/TO_ID_CLR
DAISY_OUT
MEDIA
VDD1
DAISY_IN
VSS1
133
134
132
131
130
VDD
/COLLED
OPTION
127
128
129
ASIX
AX88853
(PCS Mode)
19
2324222021
25
2930283126
27
LED<6>
LED<7>
LED_SYN
126
VSS
121
122
124
123
125
3233343536373839404142
LED<1>
LED<3>
LED<2>
118
120
119
NC
LED<0>
NCNCNCNCNC
117
115
116
VSS
114
113
4347464445
112
111
110
MTX_RDY
RX_DV<1>
CRS<1>
OPT1
106
107
108
109
4849505152
RX_CLK<1>
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
TDATA<7><4>
TDATA<7><3>
TDATA<7><2>
TDATA<7><1>
TDATA<7><0>
VDD
RSD<7>
RSCLK<7>
RDATA<7><4>
RDATA<7><3>
RDATA<7><2>
RDATA<7><1>
RDATA<7><0>
TDATA<6><4>
TDATA<6><3>
TDATA<6><2>
TDATA<6><1>
TDATA<6><0>
VSS
RSD<6>
RSCLK<6>
RDATA<6><4>
RDATA<6><3>
RDATA<6><2>
RDATA<6><1>
RDATA<6><0>
VDD
RSD<2>
RSCLK<2>
VSS
TDATA<2><2>
TDATA<2><1>
TDATA<2><0>
TDATA<2><4>
TDATA<2><3>
RDATA<3><3>
RDATA<3><0>
RDATA<3><2>
RDATA<3><4>
RDATA<3><1>
VDD
RSD<3>
RSCLK<3>
TDATA<3><0>
VSS
TDATA<3><3>
TDATA<3><1>
TDATA<3><4>
TDATA<3><2>
RDATA<4><0>
VSS1
VDD1
RDATA<4><4>
RDATA<4><2>
RDATA<4><3>
RDATA<4><1>
VDD
RSD<4>
RSCLK<4>
TDATA<4><0>
TDATA<4><1>
Fig - 5 Pin Connection Diagram for 8PCS Mode
10
ASIX ELECTRONICS CORPORATION
VSS
TDATA<4><2>
RDATA<5><1>
RDATA<5><0>
TDATA<4><3>
TDATA<4><4>
RSD<5>
RSCLK<5>
RDATA<5><2>
TDATA<5><0>
RDATA<5><3>
RDATA<5><4>
VDD
TDATA<5><4>
TDATA<5><2>
TDATA<5><3>
TDATA<5><1>
Page 11
AX88850 PRELIMINARY
1.7 Pin Connection Diagram for AX88854 (Management mode)
SMDIO
SMDC
115
116
VSS
/SMDV
114
113
4347464445
BSMDC
112
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
RDATA<0><0>
RDATA<0><1>
RDATA<0><2>
RDATA<0><3>
RDATA<0><4>
TDATA<0><0>
TDATA<0><1>
TDATA<0><2>
TDATA<0><3>
TDATA<0><4>
RDATA<1><0>
RDATA<1><1>
RDATA<1><2>
RDATA<1><3>
RDATA<1><4>
TDATA<1><0>
TDATA<1><1>
TDATA<1><2>
TDATA<1><3>
TDATA<1><4>
RDATA<2><0>
RDATA<2><1>
RDATA<2><2>
RDATA<2><3>
RDATA<2><4>
VSS
RSCLK<0>
RSD<0>
VDD1
VSS1
RSCLK<1>
RSD<1>
VSS
VDD
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
M0_TXEN0
187
M0_TXEN1
188
M0_TXEN2
189
M0_TXEN3
190
M0_RXEN0
191
M0_CRS0
192
M0_CRS1
193
M0_CRS2
194
M0_CRS3
195
196
197
198
199
M0_RXEN1
200
M0_RXEN2
201
M0_RXEN3
202
M0_TXEN4
203
M0_TXEN5
204
M0_CRS4
205
M0_CRS5
206
M0_CRS6
207
M0_CRS7
208
1
IRD_ODIR
MD
VSS
153
154
155
3
LED_SYN
LED<5>
LED<4>
/IR_ACTO<7>
/IR_ACTO<6>
/IR_ACTO<5>
/IR_ACTO<4>
/IR_ACTO<3>
150
148
149
151
152
VSS
/IR_ACTI<7>
/IR_ACTO<2>
/IR_ACTO<1>
/IR_ACTO<0>
145
146
147
144
143
RID<0>
/IR_ACTI<3>
/IR_ACTI<4>
/IR_ACTI<2>
/IR_ACTI<6>
/IR_ACTI<5>
138
141
139
140
142
RID<2>
RID<1>
RID<3>
RID<4>
/DIS_DAISY
RST_DLY
DAISY_OUT
/IR_ACTI<1>
/IR_ACTI<0>
DAISY_IN
133
134
135
136
137
/IR_ACT_EN
/TO_ID_CLR
VDD1
132
131
MEDIA
VSS1
130
OPTION
129
VDD
/COLLED
127
128
LED<7>
125
126
LED<6>
122
124
123
LED<3>
VSS
121
120
LED<1>
LED<0>
LED<2>
117
118
119
ASIX
AX 88854
(Management Mode)
56472
8
9
101112131415161718
19
25
293028
26
2324222021
31
27
3233343536373839404142
MTX_RDY
SMDIR
BSMDIO
OPT1
108
109
110
111
M1_RXEN7
M1_RXEN6
M1_RXEN5
M1_RXEN4
M1_TXEN7
M1_TXEN6
M1_TXEN5
M1_TXEN4
M1_RXEN3
M1_RXEN2
M1_RXEN1
M1_CRS7
M1_CRS6
M1_CRS5
M1_CRS4
4849505152
RX_DV<1>
CRS<1>
RX_CLK<1>
105
106
107
104
103
102
101
100
RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
99
RXD<1><0>
98
TX_EN<1>
TXD<3>
97
96
TXD<2>
TXD<1>
95
TXD<0>
94
VSS
93
TX_ER
92
COL
91
CRS<0>
90
RX_DV<0>
89
RX_CLK<0>
88
RX_ER<0>
87
RXD<0><3>
86
RXD<0><2>
85
RXD<0><1>
84
RXD<0><0>
83
TX_EN<0>
82
OPT0
81
80
VDD1
VSS1
79
TDATA<7><4>
78
TDATA<7><3>
77
TDATA<7><2>
76
TDATA<7><1>
75
TDATA<7><0>
74
VDD
73
RSD<7>
72
RSCLK<7>
71
RDATA<7><4>
70
RDATA<7><3>
69
RDATA<7><2>
68
RDATA<7><1>
67
RDATA<7><0>
66
TDATA<6><4>
65
TDATA<6><3>
64
TDATA<6><2>
63
TDATA<6><1>
62
TDATA<6><0>
61
VSS
60
RSD<6>
59
RSCLK<6>
58
RDATA<6><4>
57
RDATA<6><3>
56
RDATA<6><2>
55
RDATA<6><1>
54
RDATA<6><0>
53
VDD
RSD<2>
RSCLK<2>
M0_TXEN6
VSS
TDATA<2><1>
TDATA<2><0>
TDATA<2><4>
TDATA<2><3>
TDATA<2><2>
M0_RXEN4
M0_RXEN5
M0_RXEN6
M0_RXEN7
M0_TXEN7
RSCLK<3>
RDATA<3><3>
RDATA<3><0>
RDATA<3><2>
RDATA<3><4>
RDATA<3><1>
M0_RXD0
M0_RXD1
M0_RXD2
M0_RXD3
M0_RXER
M0_RX_CLK
VDD
RSD<3>
TDATA<3><0>
M0_TXD0
M0_RXDV
VSS
TDATA<3><3>
TDATA<3><1>
TDATA<3><4>
TDATA<3><2>
RDATA<4><0>
M0_TXER
M0_TXD2
M0_TXD3
M1_RXD0
M0_TXD1
VSS1
VDD1
RDATA<4><4>
RDATA<4><2>
RDATA<4><3>
RDATA<4><1>
M1_RXD1
M1_RXD2
M1_RXD3
M1_RXER
VDD
RSD<4>
RSCLK<4>
TDATA<4><0>
M1_RXCLK
M1_RXDV
M1_TXD0
TDATA<4><2>
TDATA<4><1>
M1_TXD1
M1_TXD2
Fig - 6 Pin Connection Diagram for Management Mode
11
ASIX ELECTRONICS CORPORATION
VSS
RDATA<5><1>
RDATA<5><2>
RDATA<5><0>
TDATA<4><3>
TDATA<4><4>
M1_CRS0
M1_CRS1
M1_TXER
M1_CRS2
M1_TXD3
RSD<5>
RSCLK<5>
RDATA<5><3>
RDATA<5><4>
TDATA<5><1>
TDATA<5><0>
M1_CRS3
M1_TXEN0
M1_TXEN1
VDD
TDATA<5><4>
TDATA<5><2>
TDATA<5><3>
M1_TXEN2
M1_TXEN3
M1_RXEN0
Page 12
AX88850 PRELIMINARY
2.0 Pin Description
2.1A PCS interface
Signal Name Type Pin No. Description
RDATA[0][4:0]
RDATA[1][4:0]
RDATA[2][4:0]
RDATA[3][4:0]
RDATA[4][4:0]
RDATA[5][4:0]
RDATA[6][4:0]
RDATA[7][4:0]
RSCLK[0]
RSCLK[1]
RSCLK[2]
RSCLK[3]
RSCLK[4]
RSCLK[5]
RSCLK[6]
RSCLK[7]
RSD[0]
RSD[1]
RSD[2]
RSD[3]
RSD[4]
RSD[5]
RSD[6]
RSD[7]
TDATA[0][4:0]
TDATA[1][4:0]
TDATA[2][4:0]
TDATA[3][4:0]
TDATA[4][4:0]
TDATA[5][4:0]
TDATA[6][4:0]
TDATA[7][4:0]
* RDATA[1:6][4] are pull up.
** TDATA[3][4] and TDATA[4][4] drive capability are MH
I/PU
I/PD*
I/PD*
I/PD*
I/PD*
I/PD*
I/PD*
I/PU
I
I
I
I
I
I
I
I
I /PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
O/L
O/L
O/L
O/H**
O/H**
O/L
O/L
O/L
181-177,
195-191
208-204
14-10
30,29,26-
24
44-40
57-53
70-66
182
196
2
15
31
45
58
71
183
197
3
16
32
46
59
72
190-186
203-199
8-4
22-18
38-34
51-47
65-61
78-74
Receive Symbol Data : Data is input synchronously with the rising edge of
RSCLK
Receive Symbol Clock : This 25Mhz input signal is phase-locked to the
incoming signal at PHY. RSCLK is used to clock in received data from the
RDATA[4:0] data bus.
Receive Signal Detect : This asynchronous input signal indicates that the
receive signal is above the detection threshold and will be used for link test
state machine.
Transmit Symbol Data : These signals are 4B/5B encoded transmit data
symbol, driven at the rising edge of local 25Mhz clock. LCLK
Note : “Type” has the following attributes
I : Input
O : Output
I/O : Bi-direction
PU : Pull Up
PD : Pull Down
H : Driving High Current 16mA
MH : Driving Middle High Current 12mA
ML : Driving Middle Low Current 8mA
L : Driving Low Current 4mA
12
ASIX ELECTRONICS CORPORATION
Page 13
AX88850 PRELIMINARY
2.1B MII interface (share bus MII group 0 port & MII group 1 port)
M0 -- MII group 0 ; M1 -- MII group 1
Signal Name Type Pin No. Description
M0_TX_ER
M1_TX_ER
M0_TXD[3:0]
M1_TXD[3:0]
M0_TX_EN[7:0]
M1_TX_EN[7:0]
M0_RXD[3:0]
M1_RXD[3:0]
M0_RX_ER
M1_RX_ER
M0_RX_CLK
M1_RX_CLK
M0_RX_DV
M1_RX_DV
M0_CRS[7:0]
M1_CRS[7:0]
M0_RX_EN[7:0]
M1_RX_EN[7:0]
O/ML
O/ML
O/H
O/H
O/L
O/L
I/PU
I/PU
I/PD
I/PD
I
I
I/PD
I/PD
I/PD
I/PD
O/L
O/L
2238Transmit Error : TX_ER is transition synchronously with respect to the rising
edge of TX_CLK . Asserted high when a code violation is request to be send
21-18
37-34
4,3,203,
202,
189-186
74,65-63,
50-47
13-10
29,26-24
207-204,
194-191
56-53,
43-40
8-4,
201-199,
190
78-75,
62,61,59,
Transmit Data : TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
Transmit Enable : TX_EN is transition synchronously with respect to the
rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles
on TXD [3:0] for transmission.
Receive Data : RXD [3:0] is driven by the PHYsynchronously with respectto
RX_CLK.
1430Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is
asserted for one or more RX_CLK periods to indicate to the port that an error
has detected.
1531Receive Clock : RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from
the PHY to the MII port of the repeater.
1632Receive Data Valid : RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either
the transmit or receive medium is non-idle.
Receive Enable : Assert high to the respective PHY chip to enable its receive
data.
51
13
ASIX ELECTRONICS CORPORATION
Page 14
AX88850 PRELIMINARY
2.2 MII interface ( two individual MII ports )
Signal Name Type Pin No. Description
TX_ER
(share)
TXD[3:0]
(share)
TX_EN[0]
TX_EN[1]
RXD[0][3:0]
RXD[1][3:0]
RX_ER[0]
RX_ER[1]
RX_CLK[0]
RX_CLK[1]
RX_DV[0]
RX_DV[1]
CRS[0]
CRS[1]
COL
(share)
O/ML 92 Transmit Error : TX_ER is transition synchronously with respect to the rising
edge of TX_CLK . Asserted high when a code violation is request to be send
O/ML 97-94 Transmit Data : TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
O/L
O/L
I/PU
I/PU
I/PD
I/PD
I
I
I/PD
I/PD
I/PD
I/PD
O/ML 91 Collision Signal :This pin indicates collision(s) , that occurred at the collision
8298Transmit Enable : TX_EN is transition synchronously with respect to the
rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles
on TXD [3:0] for transmission.
86-83
102-99
104
105
106
107
Receive Data : RXD [3:0] is driven by the PHYsynchronously with respectto
RX_CLK.
87
Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is
asserted for one or more RX_CLK periods to indicate to the port that an error
has detected.
88
Receive Clock : RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from
the PHY to the MII port of the repeater.
89
Receive Data Valid : RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].
90
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either
the transmit or receive medium is non-idle.
domain of the hub, to MII interface devices. Both the MII port use this signal
commonly.
OPT0
OPT1
I/PU
I/PU
81
108
Option for external device type : Default ‘high’ is for PHY type device.
Otherwise, ‘low’ for MAC type device.
14
ASIX ELECTRONICS CORPORATION
Page 15
AX88850 PRELIMINARY
2.3 Station Management Interface
Signal Name Type Pin No. Description
SMDC I 116 Station Management Data Clock : The timing reference for MDIO. All data
transfers on MDIO are synchronized to the rising edge of this clock. MDC is
limited to a maximum frequency of 2.5MHz.
SMDIO I/O/L
/PU
/SMDV I/PU 114 Station Management Data Valid : Asserted when a valid read/write command
SMDIR O/L 110 Station Management Data Direction : Direction signal for an external bi-
BSMDC O/L 112 Buffered Station Management Data Clock : Buffered MDC signal. Allow
BSMDIO I/O/L
/PU
115 Station Management Data Input / Output : Serial data input/output transfers
from/to the internal registers or PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
is present.
directional buffer on the MDIO signal.
0 = MDIO data flows into the AX88850
1 = MDIO data flows out of the AX88850
Defaults to 0 when no register access is present.
more devices to be chained on the MII serial bus.
111 Buffered Station Management Data Input /Output : Buffered MDIO signal.
When the “PHY_access” bit in the CONFIG register is set High, the MDIO
signal is passed through to BMDIO for accessing the physical device chips.
2.4 Management Information Base (MIB) Interface
Signal Name Type Pin No. Description
MD I/O/Z
/MH
/PU
MTX_RDY O/L 109 Repeated Packet Ready : Repeated packet data ready to copy to MIB chip
155 Management Data : Outputs management information for the AX88856 MIB
chip. This signal carries with RID_CH signal and port number of the in-
coming packet and is synchronous to IRD_CK signal.
indicator.
15
ASIX ELECTRONICS CORPORATION
Page 16
AX88850 PRELIMINARY
2.5 Expansion Bus Interface
Signal Name Type Pin No. Description
IRD[3:0] I/O/Z
/MH
/PU
/IRD_ER I/O/Z
/MH
/PU
/IRD_V I/O/Z
/MH
/PU
IRD_CK I/O/Z
/MH
IRD_ODIR O/L 154 INTER REPEATER DATA IN/OUT DIRECTION : This pin indicates the
/IR_ACTO
[7:0]
/IR_ACTI[7:0]
I/O/OC/H152-145 INTER REPEATER ACTIVITY IN/OUT: Then the local repeater activity
I/PU
164-161 INTER REPEATER DATA : Nibble data input/output. Transfer data from
the “active” AX88850 to all other “inactive” AX88850s. The bus-master of
the IRD bus is determined by IR_VECT bus arbitration.
159 INTER REPEATER DATA ERROR: This signal reflect the RX_ER status
of the active port across the inter repeater bus. Used to track receive errors
from the PHY in real time.
158 INTER REPEATER DATA VALID : This signal reflect the RX_DV status
of the active port across the inter repeater bus. Used to frame good packets.
157 INTER REPEATER CLOCK VALID : All inter repeater signals are
synchronized to the rising edge of this clock.
direction of data for external transceiver.
“High” = IRD[3:0], /IRD_ER, /IRD_V , IRD_CK are Output.
“Low” = IRD[3:0], /IRD_ER, /IRD_V , IRD_CK are Input.
appearance, the signalof the related RID (Repeater ID) willbe asserted andas
a output pin. All other pins serve as input pins but except the collision
conditions. When collision occurred all of the signal of related (RID-1) pins
will served as outputs and will active during local collision period. The
exception case is when RID = 0, then (RID-1) is replaced with (RID+1)=1.
143-136
INTER REPEATER ACTIVITY IN: These pins perform the same function
as /IR_ACTO[7:0] when they serve as input function. Then the
/IR_ACTO[7:0] insert external buffers the input function must be replaced
with /IR_ACTI [7:0].
or
RID[4:0]
/IR_ACTI[4:0]
/DIS_DAISY
/IR_ACTI[5]
/TO_ID_CLR
/IR_ACTI[6]
/IR_ACT_EN
/IR_ACTI[7]
I/PU
I/PU
I/PU
I/PU
140-136
141
142
143
The /IR_ACTI[7:0] also serve as power-on configuration input:
Repeater Identification Number Parallel In RID[4:0]: When power on reset
these pin as inputs to setup the repeater ID of the chip. RID[2:0] indicate the
repeater ID from 0 to 7. RID[4:3] defines the group code in the cascade
system and must keep difference with PHY ID address definition.
Disable RID Daisy-chain Input. No matter what kind of data input from
DAISY_IN pin ,the repeater ID will never be changed from DAIST_IN.
Time Out to Clear repeater ID : Within the time out period, if no daisy chain
repeater ID input. The repeater ID will be clear to RID=0 . Otherwise, the
repeater ID will remain the previous value ( power on configured value ,
previous daisy chainreconfigured value or the configuration value writtenvia
station management port).The tome out period is about 4 to 5 second.
/IR_ACTI[7:0] pins function is enable when IR_ACT_EN is pulled “low”
when power on. Otherwise , it is disable.
16
ASIX ELECTRONICS CORPORATION
Page 17
AX88850 PRELIMINARY
2.6 LED Display
Signal Name Type Pin No. Description
LED[7:0] O/L 125-122,
120-117
LED Display Information : Those signals indicate each port‘s Partition,
Jabber, Link/Activity, Utilization % (global), Collision % (global) in
sequence. For detail , see the LED timing specification
The Utilization % display define as following :
Group0 [ U4 :U0 ]
Utilization % LED4 LED3 LED2 LED1 LED0
0 1 1 1 1 1
1 1 1 1 1 0
5 1 1 1 0 0
15 1 1 0 0 0
30 1 0 0 0 0
60 0 0 0 0 0
Group1 [ UU4 :UU0 ]
Utilization % LED4 LED3 LED2 LED1 LED0
0 1 1 1 1 1
2 1 1 1 1 0
10 1 1 1 0 0
20 1 1 0 0 0
40 1 0 0 0 0
80 0 0 0 0 0
The Collision % display define as following :
Group0 [ C4 :C0 ]
Collision % LED4 LED3 LED2 LED1 LED0
0 1 1 1 1 1
1 1 1 1 1 0
2 1 1 1 0 0
5 1 1 0 0 0
10 1 0 0 0 0
15 0 0 0 0 0
Group1 [ CC4 :CC0 ]
Collision % LED4 LED3 LED2 LED1 LED0
0 1 1 1 1 1
4 1 1 1 1 0
8 1 1 1 0 0
20 1 1 0 0 0
30 1 0 0 0 0
60 0 0 0 0 0
LED_SYN O/L 126 LED status synchronous signal : The signal is a LED_CK period width signal
and repeated every 16 cycle. When high indicate the next cycle on the
LED[7:0] bus show the Partition status of port 8 to 0 respectively.
/COLLED O/MH 127 Collision LED Display : When Collision occur, the signal will
be “LOW” about 52.4 ms.
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2.7 Miscellaneous
Signal Name Type Pin No. Description
LCLK or
TX_CLK
/RST I 165 Reset : The chip is reset when this signal is asserted Low.
RST_DLY O/L 135 Reset Delay : The signal is active high when reset and delay /RST signal
DAISY_IN I/PU 133 Repeater Identification Number Daisy-Chain In : This pin is a daisy chain
DAISY_OUT O/L 134 Repeater Identification Number Daisy-Chain Out : This pin is periodically
TEST I/PD 166 Test Pin : The pin is just for test mode setting purpose only. Must be pull low
GEP[3:0] I/O/L
MEDIA I/PD 130 Media selection :
OPTION I/PU 129 Option : Option for repeater state machine. User must pull this pin up.
VDD I 1,17,27,
VSS I 9,23,28,
I 168 Local Clock : Must be run at 25Mhz . Used for transmit data to PHY devices,
about 2 LCLK cycle. It is useful for power on configuration setup control of
/IR_ACTI[7:0].
serial input for Repeater ID. A state machine always monitor the input if a
correct data (RID) present at the pin, the (RID+1) will be written to RID
register and override the power on setup RID for the chip.
shift out the RID of itself to the next chained chip to inform that this ID has
already been occupied. The RID is shift out periodically every about 200us.
when normal operation. When in test mode , GEP pins will be force to test
input signals.
175-172 General Purpose I/O Pins : Those pins just for system application usage. I.e.
/PU
33,52,73,
80,103,
128,132,
156,171,
184
39,60,79,
93,113,
121,131,
144,153,
160,167,
176,185,
198
for output control or input status report.
When reset the default function is for inputs.
External pull-down for AX88853 with 4.7K ohm resister.
External pull-up for AX88851, AX88852 and AX88854 with 4.7K ohm
resister.
POWER : +5V +/-5%
POWER: 0V
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3.0 Functional Description
3.1 PCS interface logic
The PCS logic performs PCS / MII receiving / transmitting interface. When it receives, first deciphers thesignals from
RDATA<4:0>, then do symbol alignment after detecting /J/K/ codes, then data is aligned to do 5B/4B decoding.
When it transmits, first do 4B/5B encoding to convert MII signals to PCS signals, then enciphers and send to
TDATA<4:0>.
When RSD is high from low, then link fail counter will count for 330u sec, then the port can receive packet normally.
During 330u sec that link fail counter counts, then receiving packet will be ignored. Cipher / No-cipher is selected by
station management access logic.
3.2 Carrier Integrity Monitor State Machine ( AX88853 PCS mode only )
For 100BASE-X systems,it is necessary that the repeater set protect the network from some transient fault conditions
that would disrupt network communications. Potential likely causes of such conditions are DTE and repeater powerup and power-down transients, cable disconnects, and faulty wiring.
The AX88853 support CIM state machine with self-interrupt capability to prevent a segment’s spurious carrier
activity from reaching the repeater unit and hence propagating through the network.
3.3 Repeater State Machine
The repeater state machine is used to control repeater behavior, generates right signal in corresponding states. The
repeater state machine is in Idle state when there is no carrier . When there is carrier , the repeater state machine
goes to Data Forwarding State to ensure correct data forwarding. If collision happens anytime, The repeater state
machine detects collision then send jam pattern until collision ceases.
idle State
The idle state happens when these conditions exists:
a. /RST is low.
b. Reset emitted by station management access logic(RST_RSM).
c. There is no any carrier in M0_CRS[7:0], M1_CRS[7:0], and CRS{1:0] in MII mode. Or
receive IDLE code inPCS mode. If in cascade application, repeater receive no inter repeater
active signal.
In this state,M0_RXEN[7:0],M1_RXEN[7:0],M0_TXEN[7:0],M1_TXEN[7:0] are all low in MII
mode.
Data Forwarding State
When there is only one carrier in M0_CRS[7:0], M1_CRS[7:0]or CRS[0], CRS[1] in MII mode, or
only one of eight ports receives /J/K/ codes in PCS mode ,or only one of IR_ACTO[7:0] become low,
The repeater state machine stores receiving packet and transmits to all other ports. Exception for
a. The port is jabbered.
b. The port is partitioned.
c. There exists collision.
In this state, only one of M0_RXEN[7:0] and M1_RXEN[7:0] is high, or M0_RXEN[7:0] or
M1_RXEN[7:0] are all low because either packetis from two dedicated MII port or frominter-repeater
cascade interface in MII mode.
The repeater send packet from receiving port to all ports exclusive of the receiving that is
M0_TXEN[7:0] and M1_TXEN[7:0] all becomes high, and one may below if that port isthe receiving
port in MII mode. The repeater forwards data to TDATA[7:0] except for the receiving RDATA port in
PCS mode.
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Collision State
The Collision State happens when these conditions exists:
a. There are two or more signals high among M0_CRS[7:0],M1_CRS[7:0],CRS[1:0]. Or receive
collision messages from /IR_ACTO[7:0] in MII mode.
b. At least two ports of PCS ports receive /J/K/ code group or receive collision message from
/IR_ACTO[7:0] in PCS mode.
c. Only one carrier exists but RXDV still low exceeds 5 clock cycles. The repeater sends collision
pattern to all ports, that is, M0_TXEN[7:0] and M1_TXEN[7:0] all become high during collision
state.
3.4 Jabber State Machine
To prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. If a
reception exceeds this duration(64K bit times for AX88850), the jabber condition will be detected. In this condition,
repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal
operation.
When the carrier is no longer detected for the jabbered port or reset the repeater, the jabber function will be clear and
re-enable reception and transmission.
3.5 Partition State Machine
The partition state machine is used to protect network frombe upset by a port suffering continuous collision, each port
uses a partition state machine to detect and prevent this condition. When a port is suffering from continuous 32 or
64 times of collisions by CCLimits. Then it goes to Partition State. The port entering Partition State will be released
until a packet without collision more than 512 bit times or after power-on reset.
Partition function is enabled by default, and CCLimits is 64 by default. Enable/Disable partition function
(DIS_PART) and option of CCLimits to be 64 or 32 (COL_LIMIT32) are selected by station management access
logic.
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3.6 Expansion Logic(Cascade Interface)
The expansion logic is used to stack numerous repeaters. The expansion logic can be divided into two types:
Expansion Logic with Buffer (maximum mode
In this mode, use /IR_ACTO[7:0] and /IR_ACTI[7:0] to cascade repeaters. Buffers are used both in
/IR_ACTO[7:0] and /IR_ACTI[7:0]. This mode is supposed to cascade repeaters on difference boards via cables.
There is a configuration bit /IR_ACT_EN to decide cascade signals are judges by /IR_ACTI[7:0](/IR_ACT_EN
= 0) or /IR_ACTO[7:0](/IR_ACT_EN = 1).
Expansion Logic without Buffer (minimum mode)
In this mode, use /IR_ACTO[7:0] to cascade repeaters. Just connect /IR_ACTO[7:0] without using buffer in this
part. This mode is supposed to cascade repeaters on the same board.
/IR_ACTO<7:0>
RPTR_ID<2:0> Idle Active Collision
0 FFh FEh FBh
1 FFh FDh FCh
2 FFh FBh F9h
3 FFh F7h F3h
4 FFh EFh E7h
5 FFh DFh CFh
6 FFh BFh 9Fh
7 FFh 7Fh 3Fh
In this table:
a. All /IR_ACTO[7:0] will be in open-drain state when repeater chip is idle. These signals are all high via
external pull high resister.
b. One signal of /IR_ACTO[7:0] is low in data forwarding state corresponding to different RPTR_ID[2:0].
c. Two signals of /IR_ACTO[7:0] are low in collision state corresponding to different RPTR_ID[2:0].
3.7 Management Logic
AX88850 provides the required management information associated with a packet for management chip which
statistics processed on a per packet basis. Transmit ready signal TX_RDY is used as a framing signal for management
data MD. Thenmanagement chip uses this data to determinethe source of the current packet. MD data issynchronized
to the rising edge of IRD_CK. When collision occur, MD will be tri-state and becomes invalid.
MD frame format
idle start bit data0 data1 data2 data3 data4 data5 data6
1 0 PID[0] PID[1] PID[2] PID[3] PID[4] RID_CH PARITY
Notes:
a. PID[4:0] is the number of the receiving port.
b. RID_CH indicates change in RID.
c. PARITY = 1 when sum of 1‘s among PID[4:0] and RID_CH is even
PARITY = xnor (PID[4],PID[3],PID[2],PID[1],PID[0],RID_CH)
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3.8 Management Counters
There are four management counters in each port. These 16-bit-wide management counters keep track of the
following events:
Collision Event Counter
It indicates the number of times that collision occurrences on a port.
Partition Event Counter
It indicates the number of times that a port has been partition.
Short Event Counter
It indicates the number of packets that is shorter than 76 BT.
Late Event Counter
It indicates the number of collision occurrences time after 512 BT when carrier presents.
Fault Carrier Event Counter (AX88853 only)
It indicates the number of times that fault carrier occurrences on a port.
These counters can be read out by MIB serial access interface and will be clear after read operation.
3.9 Station Management Access Interface
The AX88850 provides 128 registers held in 4 pages of 32(Page 0 ~ 3 Register).These registers are 16 bits wide. Only
one register of one page can be access at the same time through the MII serial management bus. After power on
reset, Page 0 Register is the default setting. Change the value of PAGE REGISTER which exists in all pages, then
switches to any page. For example: Page 3 Register can be accessed by writing 03h to the PAGE REGISTER.
AX88850 can thus be managed through SMDC and SMDIO pins. The SMDC clock with maximum 2.5M Hz is used
to sample data train on SMDIO. The interface follows the serial management protocol defined by IEEE 802.3u clause
22.
Management frame format
PREAM START OPCODE DEV_AD REG_AD TA DATA IDLE
READ 1.......1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD Z
WRITE 1.......1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Z
For the protocol to work, all serial data must be “synchronized” to incoming data. To ensure data locked, a preamble
of 32 consecutive 1‘s present before the start code, then the receive logic know the beginning of the data frame.
With the setting of PHY_ACCESS = 1(stored in CONFIGURATION REGISTER), the target access device may be
physical layer devices. In this mode, SMDIO is gated to BSMDIO. SMDIO and BSMDIO must turn on in the
appropriate direction for read/write access. In the cascade system, only one repeater chip has the set of
PHY_ACCESS at a time to avoid contention problems.
3.10 RID Receive-Transmit Interface(Daisy Chain Logic)
In the cascade system, repeater ID of each chip will be re-arranged by serial in/out daisy chain logic. The DAISY_IN
pin always monitor RID of the previous chained chip, and the value of (RID+1) will override the original RID of the
current chip. Then the DAISY_OUT pin will periodically (about 200us) send out the exact RID of current chip to
inform the next chained chip. By this way, each repeater chip in 8 AX88850 hub (maximum application) will keep
unique ID of itself. The RID is used in inter repeater bus arbitration and uniquely identify station management
accesses.
Note that only RID[2:0] can be changed and RID[4:3] must be the same value for all repeaters in the cascade system.
In this way, repeater ID won‘t be confused with PHY device ID during station management access.
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DAISY_IN/OUT frame format
idle start bit data0 data1 data2 data3
1 0 RID[0] RID[1] RID[2] PARITY
Notes: PARITY = 1 when sum of 1‘s in RID[2:0] is even
There are two flag : /DIS_DAISY and /TO_ID_CLR which control daisy-chain access. If disable daisy-chain input
(/DIS_DAISY = 0), the RID of current chip can‘t be override and don‘t care the present data on DAISY_IN. If no
daisy-chain input, the RID of current chip can be clear to 0 during time out period with the setting of /TO_ID_CLR =
0. The timer is done about 4sec.
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3.11 LED Interface
AX88850 provides per-port LED status indication for partition, jabber, link/activity and support rate-based LED for
global utilization (%) and global collision frequency (%). Detail function is described on previous pin description
(LED interface). LED[7:0] are all active low.
3.11.1 LED Status Driver wave-form for AX88851
LED_SYN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 ~ D15 D0 D1 D2 D3
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
P0 J0 A0 C4 C0 P10 J10 A10 RID0 CC0 no useful phase
P1 J1 A1 U4 C1 P11 J11 A11 RID1 CC1 no useful phase
P2 J2 A2 A8 C2 P12 J12 A12 RID2 CC2 no useful phase
P3 J3 A3 A9 C3 P13 J13 A13 RID3 CC3 no useful phase
P4 J4 A4 J8 U0 P14 J14 A14 RID4 UU0 no useful phase
P5 J5 A5 J9 U1 P15 J15 A15 UU1 no useful phase
P6 J6 A6 P8 U2 P16 J16 A16 CC4 UU2 no useful phase
P7 J7 A7 P9 U3 P17 J17 A17 UU4 UU3 no useful phase
"0"
P0 J0 A0 C4
P1 J1 A1 U4
P2 J2 A2 A8
P3 J3 A3 A9
P4 J4 A4 J8
P5 J5 A5 J9
P6 J6 A6 P8
P7 J7 A7 P9
Note 1 :
a. P17~0 indicates partition status for each port
b. J17~0 indicates jabber status for each port
c. L17~0 indicates link status for each port
d. A17~0 indicates activity status for each port
e. RID4~0 is the ID number of repeater chip
f. The LED display support two estimations:C4~0 and CC4~0 which indicate global collision rate for
each 104.8ms sampling period. Users can choose any one presentation.
g. The LED display support two estimations:U4~0 and UU4~0 which indicate global utilization rate for
each 104.8ms sampling period. Users can choose any one presentation.
Note 2 : Reference port map as following table (Using per port Carrier Sense / Receive Signal Detect to identify port
number).
AX88851 Port[7:0] == M0_CRS[7:0] Port[9:8] == CRS[1:0] Port[17:10] == M1_CRS[7:0]
AX88852 Port[3:0] == M0_CRS[3:0] Port[9:8] == CRS[1:0] Port[7:4] == M1_CRS[3:0]
AX88853 Port[7:0] == RSD[7:0] Port[9:8] == CRS[1:0]
AX88854 Reference to AX88851/AX88853 depended on MEDIA setting.
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3.11.2 LED Status Driver wave-form for AX88852
LED_SYN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 ~ D15 D0 D1 D2 D3
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
P0 J0 A0 C4 C0 P4 J4 A4 RID0 CC0 no useful phase
P1 J1 A1 U4 C1 P5 J5 A5 RID1 CC1 no useful phase
P2 J2 A2 A8 C2 P6 J6 A6 RID2 CC2 no useful phase
P3 J3 A3 A9 C3 P7 J7 A7
J8 U0 RID4 UU0 no useful phase
J9 U1 UU1 no useful phase
P8 U2 CC4 UU2 no useful phase
P9 U3 UU4 UU3 no useful phase
UU1
"0"
3.11.3 LED Status Driver wave-form for AX88853
CC3 no useful phase
P0 J0 A0 C4
P1 J1 A1 U4
P2 J2 A2 A8
P3 J3 A3 A9
J8
J9
P8
P9
LED_SYN
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 ~ D15 D0 D1 D2 D3
P0 J0
P1 J1
P2 J2
P3 J3
P4 J4
P5 J5
P6 J6
P7 J7
L0/
C4 C0 RID0 CC0 no useful phase
A0
L1/
U4 C1 RID1 CC1 no useful phase
A1
L2/
A8 C2 RID2 CC2 no useful phase
A2
L3/
A9 C3
A3
L4/
J8 U0 RID4 UU0 no useful phase
A4
L5/
J9 U1 UU1 no useful phase
A5
L6/
P8 U2 CC4 UU2 no useful phase
A6
L7/
P9 U3 UU4 UU3 no useful phase
A7
UU1
CC3 no useful phase
"0"
P0 J0
P1 J1
P2 J2
P3 J3
P4 J4
P5 J5
P6 J6
P7 J7
L0/
A0
L1/
A1
L2/
A2
L3/
A3
L4/
A4
L5/
A5
L6/
A6
L7/
A7
C4
U4
A8
A9
J8
J9
P8
P9
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3.11.4 LED Status Driver wave-form for AX88854
LED_SYN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 ~ D15 D0 D1 D2 D3
LED[0]
P0 J0
L0/
C4 C0 P10 J10 A10 RID0 CC0 no useful phase
A0
P0 J0
L0/
A0
C4
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
P1 J1
P2 J2
P3 J3
P4 J4
P5 J5
P6 J6
P7 J7
L1/
U4 C1 P11 J11 A11 RID1 CC1 no useful phase
A1
L2/A2L8/
L3/A3L9/
L4/
A4
L5/
A5
L6/
A6
L7/
A7
C2 P12 J12 A12 RID2 CC2 no useful phase
A8
C3 P13 J13 A13
A9
J8 U0 P14 J14 A14 RID4 UU0 no useful phase
J9 U1 P15 J15 A15 UU1 no useful phase
P8 U2 P16 J16 A16 CC4 UU2 no useful phase
P9 U3 P17 J17 A17 UU4 UU3 no useful phase
UU1
CC3 no useful phase
"0"
P1 J1
P2 J2
P3 J3
P4 J4
P5 J5
P6 J6
P7 J7
L1/
U4
A1
L2/A2L8/
A8
L3/A3L9/
A9
L4/
J8
A4
L5/
J9
A5
L6/
P8
A6
L7/
P9
A7
3.12 Power on Configuration(Initial Setting)
During power-on reset, /IR_ACTI[[7:0] are used as some configuration setting. These include inter repeater active
input pin enable/disable (/IR_ACT_EN); time out to clear repeater ID(/TO_ID_CLR); daisy-chain input
disable/enable (/DIS_DAISY); and repeater ID(RPTR_ID[4:0]). Detail function is described on previous pin
description (expansion bus interface). After reset, these setting are stored in DEVICE ID REGISTER which can be
modified by station management write commands.
Default setting Function
/IR_ACT_EN pull high DISABLE inter repeater active in
/TO_ID_CLR pull high DISABLE time out to clear repeater ID
/DIS_DAISY pull high ENABLE daisy-chain input
RPTR_ID pull high RPTR_ID = 11111
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4.0 REGISTERS
The AX88850 has 128 16-bit registers which are separated into four pages with each page 32 words. At
power-on or reset , the default value is page 0 registers. The register page can be changed by writing to the register
address 1 on all the four pages .
4.1 Page 0 Register MAP
Address (hex) Name Access Description
0 CONFIG R/W Set AX88850 configuration
1 PAGE R/W Selects register from page 0 to page 3.
2 PARTITION RO Indicates Auto-Partitioning status.(port0 - port9)
3 JABBER RO Indicates Jabber status. (port0 - port9)
4 ADMIN R/W Port enable / disable, administration control/status(port0 - port9)
5 DEVICE-ID R/W Accesses 1) the AX88850 ID number configured externally on the
RID[4:0] pins. 2) the last receiving port number.
The device number of AX88850 may be overwritten after it has been
latched at the end of reset.
6 Reserved
7 Reserved
8 P8-SE R/W Port 8 : 16-bit ShortEvent Counter (dedicated MII port 0)
9 P8-LE R/W Port 8 : 16-bit LateEvent Counter
A P8-COL R/W Port 8 : 16-bit Collision Counter
B P8-PART R/W Port 8 : 16-bit Auto-partition Counter
C P9-SE R/W Port 9 : 16-bit ShortEvent Counter (dedicated MII port 1)
D P9-LE R/W Port 9 : 16-bit LateEvent Counter
E P9-COL R/W Port 9 : 16-bit Collision Counter
F P9-PART R/W Port 9 : 16-bit Auto-partition Counter
10-13 P0-SE …
P0-PART
14-17 P1-SE …
P1-PART
18-1B P2-SE …
P2-PART
1C-1F P3-SE …
P3-PART
R/W Port 0 management counters ( as per ports 8,9 as above )
R/W Port 1 management counters ( as per ports 8,9 as above )
R/W Port 2 management counters ( as per ports 8,9 as above )
R/W Port 3 management counters ( as per ports 8,9 as above )
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4.2 Page 1 Register MAP
Address (hex) Name Access Description
0 CONFIG R/W Set AX88850 configuration ( same as page 0 )
1 PAGE R/W Selects register from page 0 to page 3. ( same as page 1 )
2 PARTITION RO Indicates Auto-Partitioning status.(port10 - port17)
3 JABBER RO Indicates Jabber status. (port10 - port17)
4 ADMIN R/W Port enable / disable, administration control/status(port10 - port17)
5 SI_REV RO Silicon revision code.
6-7 Reserved
8-F P0-FCRS …
P7-FCRS
10-13 P4-SE …
P4-PART
14-17 P5-SE …
P5-PART
18-1B P6-SE …
P6-PART
1C-1F P7-SE …
P7-PART
R/W Port 0 false carrier counters (address 8) to
Port 7 false carrier counters (address F)
Those counters are valid just for PCS mode port 0 to port 7.
As for MII mode , the false carrier counter will be available on PHY, but
some PHY chip manufacturer not support those functions.
R/W Port 4 management counters ( as per ports 8,9 as above )
R/W Port 5 management counters ( as per ports 8,9 as above )
R/W Port 6 management counters ( as per ports 8,9 as above )
R/W Port 7 management counters ( as per ports 8,9 as above )
4.3 Page 2 Register MAP
Address (hex) Name Access Description
0 CONFIG R/W Set AX88850 configuration
1 PAGE R/W Selects register from page 0 to page 3.
2-F Reserved
10-13 P10-SE …
P10-PART
14-17 P11-SE …
P11-PART
18-1B P12-SE …
P12-PART
1C-1F P13-SE …
P13-PART
R/W Port 10 management counters ( as per ports 8,9 as above )
R/W Port 11 management counters ( as per ports 8,9 as above )
R/W Port 12 management counters ( as per ports 8,9 as above )
R/W Port 13 management counters ( as per ports 8,9 as above )
4.4 Page 3 Register MAP
Address (hex) Name Access Description
0 CONFIG R/W Set AX88850 configuration ( same as page 0 )
1 PAGE R/W Selects register from page 0 to page 3.. ( same as page 1 )
2-F Reserved
10-13 P14-SE …
P14-PART
14-17 P15-SE …
P15-PART
18-1B P16-SE …
P16-PART
1C-1F P17-SE …
P17-PART
R/W Port 14 management counters ( as per ports 8,9 as above )
R/W Port 15 management counters ( as per ports 8,9 as above )
R/W Port 16 management counters ( as per ports 8,9 as above )
R/W Port 17 management counters ( as per ports 8,9 as above )
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4.5 Configuration Register (CONFIG)
Page 0 to Page 3 Address 0h
Bit Bit Name Access Bit Description
D15-D8 Reserved Written as “0” for future compatibility concern.
Undefined by read.
D7 RST_FLAG RO Reset Flag : The bit is set when power on reset and is clear after read
CONFIG register.
D6 RID_CH RO Repeater ID Changed : The bit is set when Daisy-Chain RID input
override the current RID or after power on reset. When read CONFIG
register will clear the bit.
D5 DIS_CIPHER R/W Disable Cipher Function : Then set the bit at PCS mode, the 5bit symbol
scramble and descrambler function are disable. Default is enable.
D4 MGTEN R/W Management Enable : This bit enable all the management counters.
0 : Management Counters disabled. (default)
1 : Management Counters enabled.
D3 COL_LIMIT32 R/W Collision limit : This bit configures the collision limit for Auto-
Partitioning.
0 : Consecutive Collision limit set to 64 (default). A port will
be partitioned on the 65th consecutive collision.
1 : Consecutive Collision limit set to 32 . A port will
be partitioned on the 33rd consecutive collision.
D2 DIS_PART R/W Disable Auto-Partition : Set this bit disable the Auto-Partition
algorithm.
0 : Auto-Partition is not disabled (default)
1 : Auto-Partition is disabled .
D1 PHY_ACCESS R/W PHY access enable : This bit enable to access PHY register via MII serial
protocol.
0 : PHY access disabled (default)
1 : PHY access enabled .
D0 RST_RSM R/W Reset Repeater State Machines : Setting the bit holds the RSM in reset.
The management event flags and counters are unaffected by this bit.
Setting this bit while a reception is in progress may truncate the packet.
0 : AX88850 in normal operation (default)
1 : AX88850 held in reset .
4.6 Page Register (PAGE)
Page 0 to Page 3 Address 1h
Bit Bit Name Access Bit Description
D15-D8 GEP[3:0] R/W D11-D8 : GEP I/O control. Default = 0h for input mode. Otherwise, =1h,
enable output.
D15-D12 : GEP Data . Default = 0h.
When write, D15-D12 value present to GEP[3:0] if enabled.
When read, D15-D12 reflect the GEP[3:0] value.
D7-D2 Reserved Written as “0” for future compatibility concern.
undefined by read.
D1-D0 PAGE[1:0] R/W Those bits setting the register page to be accessed.
PAGE[1:0] PAGE
0h 0 (default)
1h 1
2h 2
3h 3
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4.7 Partition Status Register (PARTITION)
Page 0 Address 2h
Bit Bit Name Access Bit Description
D15-D10 Reserved undefined when read.
D9-D0 PART[9: 0] RO The respective port‘s PART bit is set to “1” when Partitioning is sensed
on that port. After reset, these bits are cleared to “0”.
Page 1 Address 2h
Bit Bit Name Access Bit Description
D15-D8 Reserved undefined when read.
D7-D0 PART[17: 10] RO The respective port‘s PART bit is set to “1” when Partitioning is sensed
on that port. After reset, these bits are cleared to “0”.
4.8 Jabber Status Register (JABBER)
Page 0 Address 3h
Bit Bit Name Access Bit Description
D15-D10 Reserved undefined when read.
D9-D0 JAB[9: 0] RO The respective port‘s JAB bit is set to “1” when Jabber condition is
detected on that port. After reset, these bits are cleared to “0”.
Page 1 Address 3h
Bit Bit Name Access Bit Description
D15-D8 Reserved undefined when read.
D7-D0 JAB[17: 10] RO The respective port‘s JAB bit is set to “1” when Jabber condition is
detected on that port. After reset, these bits are cleared to “0”.
4.9 Administration Register (ADMIN)
Page 0 Address 4h
Bit Bit Name Access Bit Description
D15-D10 Reserved Written as “0” for future compatibility concern.
undefined by read.
D9-D0 ADMIN[9: 0] R/W Administration Disable : Setting these bits to “0” enable the respective
port (TX and RX). Writing a 1to any bit will disablethat port. After reset,
these bits default to “0” ( all ports enable ). Note that port enable/disable
action will occur at the next network idle period.
Page 1 Address 4h
Bit Bit Name Access Bit Description
D15-D8 Reserved Written as “0” for future compatibility concern.
undefined by read.
D7-D0 ADMIN[17: 10] R/W Administration Disable : Setting these bits to “0” enable the respective
port (TX and RX). Writing a 1to any bit will disablethat port. After reset,
these bits default to “0” ( all ports enable ). Note that port enable/disable
action will occur at the next network idle period.
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4.10 Device ID Register (DEVICEID)
Page 0 Address 5h
Bit Bit Name Access Bit Description
D15-D13 Temp R/W Temporary Registers : reserved for system programer used.
D12-D8 PORT_NUM *R/W Port Number : These bit indicate the last or currentreceiving port number.
D7 /IR_ACT_EN *R/W Inter Repeater Active Input Pin Enable : This bit active low to enable
/IR_ACTI[7:0] pin as inter-repeater carrier sense detection input.
Otherwise, /IR_ACTI[7:0] pins is disable and only perform power-on
configuration inputs.
D6 /TO_ID_CLR R/W Time Out to Clear repeater ID : Within the time out period, if no daisy
chain repeater ID input. The repeater ID will be clear to RID=0 .
Otherwise, the repeater ID will remain the previous value ( power on
configured value or previous daisy chain reconfigured value).The tome
out period is about 4 to 5 second.
D5 /DIS_DAISY R/W Disable RID Daisy-chain Input: No matter what kind of data input from
DAISY_IN pin the RPTR_ID can’t be override.
D4-D0 RPTR_ID R/W Repeater ID : At the rising edge of /RST , the value of RID[4:0] are
latched in this register as D[4:0]. The setting of RID[2:0]can be override
according to the data from serial daisy-chain DAISY_IN pin input except
/DIS_DAISY is configured to “low” .
Note that in system application, the maximum of 8 devices can be
cascade. Therefore only RID[2:0] can be variation and the RID[4:3] must
be keep the same value in the same systemand avoid conflicted with PHY
device ID.
* Note : Host can’t override these signals.
4.11 Silicon Revision Register
Page 1 Address 5h
Bit Bit Name Access Bit Description
D15-D0 SI_REV[15:0] RO Silicon Reversion : Currently reads all 1‘s
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4.12 Port Management Counter Registers
Each of the 18 ports of the AX88850 has a set of 4 event counters whose values can be read or pre-set (written)
through the Port Management Counter Registers. When PCS (symbol) mode is selected, there is a set of false carrier
counter / per port build-in on the chip. As for MII mode , the false carrier counter will be available on PHY, note that
some PHY chip manufacturer not support those functions.
4.12.1 Short Event Counter Registers
Per port (“n” =port number) counters that indicate the number of Carrier Events that were active for less than the
ShortEventMaxTime, which is defined as between 74 and 82 (76 nominal) bit times.
Bit Bit Name Access Bit Description
D15-D0 P“n”_SE[15:0] R/W P“n”_SE[15:0]
4.12.2 Late Event Counter Registers
Per port (“n”= port number) counters that indicate the number of collision that occurred after the
LateEventThreshold, , which is defined as between 480 and 565 (512 nominal) bit times. Both the Late Event and
collisions will be incremented when this event occurs.
Bit Bit Name Access Bit Description
D15-D0 P“n”_LE[15:0] R/W P“n”_LE[15:0]
4.12.3 Collision Counter Registers
Per port (“n”= port number) counters that indicate the number of collisions (COL asserted) .
Bit Bit Name Access Bit Description
D15-D0 P“n”_CO[15:0] R/W P“n”_CO[15:0]
4.12.4 Auto-Partition Counter Registers
Per port (“n”= port number) counters that indicate the number of times the port was auto-partitioned.
Bit Bit Name Access Bit Description
D15-D0 P“n”_PART[15:0]R/W P“n”_PART[15:0]
4.12.5 False Carrier Counter Registers
Per port (“n”= port number) counters that indicate the number of times the port was false carrier occurred.
Those counters are valid just for PCS mode port 0 to port 7. As for MII mode , the false carrier counter will be
available on PHY, but some PHY chip manufacturer not support those functions.
Bit Bit Name Access Bit Description
D15-D0 P“n”_FCRS[15:0]R/W P“n”_FCRS[15:0]
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5.0 ELECTRICAL SPECIFICATION AND TIMING
5.1 Absolute Maximum Ratings
Description SYM Min Max Units
Operating Temperature Ta 0 +70
Storage Temperature Ts -55 +150
Supply Voltage Vcc -0.5 +7 V
Input Voltage Vin Vss-0.5 Vdd+0.5 V
Output Voltage Vout Vss-0.5 Vdd+0.5 V
Lead Temperature (soldering 10 seconds maximum) Tl -55 +250
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability
5.2 General Operation Conditions
Description SYM Min Max Units
Operating Temperature Ta 0 +70
Supply Voltage Vdd +4.75 +5.25 V
°C
°C
°C
°C
5.3 DC Characteristics
(Vdd=4.75V to 5.25V, Vss=0V, Ta=0°C to 70°C)
Description SYM Min Max Units
Low Input Voltage Vil Vss-0.5 0.8 V
High Input Voltage Vih 2 Vdd+0.5 V
Low Output Voltage Vol 0.4 V
High Output Voltage Voh 2.4 V
Input Leakage Current 1 (Note 1) Iil1 10 uA
Input Leakage Current 2 (Note 2) Iil1 500 uA
Output Leakage Current Iol 10 uA
Note :
1. All the input pins without pull low or pull high.
2. Those pins had been pull low or pull high.
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5.4 AC specifications
5.4.1 MII Interface Timing Tx & Rx
T0 T1
LCLK
T2 T2
TX_EN
(MTX_RDY)
T3 T3
TX_ER
TXD
Symbol Description Min Typ. Max Units
T0 Local Clock Cycle Time 39.996 40 40.004 ns
T1 Local Clock High Time 14 20 26 ns
T2 TX_EN or MTX_RDY Delay from LCLK High 4 14 19 ns
T3 TX_ER or TXD Delay from LCLK High 4 14 19 ns
RX_CLK
CRS
RXE
RXDV
RXD
RXER
T4 T5
T6 T7
T8
T9
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Symbol Description Min Typ. Max Units
T4 RX_CLK Clock Cycle Time 39.996 40 40.004 ns
T5 RX_CLK Clock High Time 14 20 26 ns
T6 CRS to RXE Assertion Delay 20 ns
T7 CRS to RXE De-assertion Delay 120 200 ns
T8 CRS to RXDV Delay Requirement 40 160 ns
T9 RXD or RXDV setup to RX_CLK rise time 10 - ns
5.4.2 Station Management
T1 T2
SMDC
T3 T4
T5
SMDIO Write Write
T6 T7
/SMDV
Read
SMDIR
Write
T8
BSMDC
BSMDIO
Symbol Description Min Typ. Max Units
T1 SMDC Period 400 - ns
T2 SMDC High Time 40 - ns
T3 SMDIO Setup Time to SMDC High(Write) 10 - ns
T4 SMDIO Hold Time to SMDC High(Write) 10 - ns
T5 SMDIO Valid from SMDC High(Read) 50 ns
T6 /SMDV Setup Time to SMDC High 10 - ns
T7 /SMDV Hold Time to SMDC High 10 - ns
T8 BSMDIO Buffer Delay Time 20 ns
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5.4.3 PCS Interface Timing
TX
LCLK
T0
TDATA
RX T1 T2
RSCLK
T3 T4
RDATA
Symbol Description Min Typ. Max Units
T0 TDATA Valid From LCLK High 12 35 ns
T1 RSCLK Clock Cycle Time 39.996 40 40.004 ns
T2 RSCLK Clock High Time 14 20 26 ns
T3 RDATA Setup Time 13 - ns
T4 RDATA Hold Time 10 - ns
5.4.4 LED DISPLAY
LCLK
T1 T2
LED[7:0 D15 D0 D1 D2 D3 D4 D15 D0
T3 T4
LED-SYN
T5
Symbol Description Min Typ. Max Units
T1 LED Valid from LCLK Low 7 24 ns
T2 LED Data Width 40 ns
T3 LED_SYN Valid from LCLK Low 6 13 ns
T4 LED-SYN Pulse Width 40 ns
T5 LED-SYN Cycle Time 640 ns
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5.4.5 LED Display After Reset
/Reset
T1 T2 T2 T2 T3
LED[7:0]
T4
LED_SYN ………………………………… ………………
Symbol Description Min Typ. Max Units
T1 Repeater reset time 1000 ns
T2 LED Blink Time After Reset 838.4 ms
T3 LED Dark Time Before Normal Display 419.2 ms
5.4.6 Repeater ID Daisy Chain
T1
T2 T2
Daisy-Out ID0 ID1 ID2 ID0 ID1 ID2
T3
Daisy-In ID0 ID1 ID2 ID0 ID1 ID2
Symbol Description Min Typ. Max Units
T1 Daisy Chain One Burst period 204.8 us
T2 Start Bit Period or Data Width 12.8 us
T3 Daisy Chain Data In Time-out * 3.8 s
Note : Daisy-Chain Data-In Time-out stands for no input data (always high level) for the specific time.
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5.4.7 Expansion Bus
CRS
IRD-ODIR
IRD_CK
IRD[3:0]
/IRD_ER
/IRD_V
T1 T2
T3
T4
T5 T6
MD ID0 ID1 ID2
T7 T8
Symbol Description Min Max Units
T1 CRS Assertion to IRD-ODIR Assertion - 42 ns
T2 CRS De-Assertion to IRD-ODIR De-Assertion 160 240 ns
T3 IRD[3:0] Setup Time to IRD-CK High 10 - ns
T4 /IRD_ER Setup Time to IRD-CK High 10 - ns
T5 /IRD_V Setup Time to IRD-CK High 5 - ns
T6 /IRD_V Hold Time from IRD-CK High 5 - ns
T7 MD Setup Time to IRD-CK High 3 13 ns
T8 MD Hold Time from IRD-CK High 3 13 ns
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6.0 PACKAGE INFORMATION
Hd
D
pin 1
He
E
b
e
A2 A1
L1
L
θ
MILIMETERSYMBOL
MIN. NOM MAX
A1 0.05 0.25 0.5
A2 3.17 3.32 3.47
b 0.10 0.20 0.30
D 27.90 28.00 28.10
E 27.90 28.00 28.10
e 0.50
Hd 30.35 30.60 30.85
He 30.35 30.60 30.85
L 0.45 0.60 0.75
L1 1.30
θ
0 10
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