Page 1
ASIX ELECTRONICS CORPORATION First Released Date : Dec/13/1999
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
AX88196 L
10/100BASE Local CPU Bus Fast Ethernet MAC Controller
with Embedded SRAM, SNI interface and Parallel Port
Document No.: AX196-14 / V1.4 / Nov. 21 ’00
Features
• IEEE 802.3u 100BASE-T, TX, and T4 Compatible
• Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
• Embedded 8K * 16 bit SRAM
• NE2000 register level compatible instruction
• Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
• Support both 10Mbps and 100Mbps data rate
• Support both full-duplex or half-duplex operation
• Provides a MII port for both 10/100Mbps operation
• Provides SNI I/F for Home LAN PHY or 10M
transceiver option
• Support EEPROM interface to store MAC address
• External and internal loop-back capability
• Support Standard Print Port, can also used as
general I/O port
• 128-pin LQFP low profile package
• 20MHz to 25MHz Operation, Dual 5V and 3.3V
CMOS process with 5V I/O tolerance. Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of
Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are the
property of their respective holders.
Product description
The AX88196 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet
Controller with embedded 8K*16 bit SRAM. The AX88196 supports both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88196 implements both 10Mbps and
100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and supports both 10Mbps/100Mbps
media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the design. Using Serial
Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be supported.
As well as, the chip also provides Standard Print Port (parallel port interface), can be used for printer server device or
treat as simple general I/O port.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
8051 CPU
LATCH
AX88196
AD BUS
Addr L
Addr H
Ctl BUS
10/100M
PHY/TxRx
RJ45
Home LAN
PHY
Or 10M
PHY/TxRx
RJ11
or
BNC
Print Port
Or General I/O Ports
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AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
2
CONTENTS
1.0 INTRODUCTION...............................................................................................................................................4
1.1 GENERAL DESCRIPTION: ..................................................................................................................................... 4
1.2 AX88196 BLOCK DIAGRAM:...............................................................................................................................4
1.3 AX88196 PIN CONNECTION DIAGRAM................................................................................................................5
1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode.................................................................................6
1.3.2 AX88196 Pin Connection Diagram for 80x86 Mode....................................................................................7
1.3.3 AX88196 Pin Connection Diagram for MC68K Mode .................................................................................8
1.3.4 AX88196 Pin Connection Diagram for MCS-51 Mode................................................................................9
2.0 SIGNAL DESCRIPTION..................................................................................................................................10
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP.................................................................................................... 10
2.2 MII INTERFACE SIGNALS GROUP ........................................................................................................................ 11
2.3 EEPROM SIGNALS GROUP...............................................................................................................................12
2.4 SNI INTERFACE PINS GROUP..............................................................................................................................12
2.5 STANDARD PRINTER PORT INTERFACE PINS GROUP.............................................................................................12
2.6 POWER ON CONFIGURATION SETUP SIGNALS PINS GROUP ..................................................................................... 13
2.7 MISCELLANEOUS PINS GROUP ............................................................................................................................ 13
3.0 MEMORY AND I/O MAPPING ......................................................................................................................15
3.1 EEPROM MEMORY MAPPING ..........................................................................................................................15
3.2 I/O MAPPING....................................................................................................................................................15
3.3 SRAM MEMORY MAPPING...............................................................................................................................15
4.0 REGISTERS OPERATION ..............................................................................................................................16
4.1 COMMAND REGISTER (CR) OFFSET 00H (READ/WRITE) ...................................................................................18
4.2 INTERRUPT STATUS REGISTER (ISR) OFFSET 07H (READ/WRITE)......................................................................18
4.3 INTERRUPT MASK REGISTER (IMR) OFFSET 0FH (WRITE)..................................................................................19
4.4 DATA CONFIGURATION REGISTER (DCR) OFFSET 0EH (WRITE)........................................................................ 19
4.5 TRANSMIT CONFIGURATION REGISTER (TCR) OFFSET 0DH (WRITE)................................................................. 19
4.6 TRANSMIT STATUS REGISTER (TSR) OFFSET 04H (READ).................................................................................20
4.7 RECEIVE CONFIGURATION (RCR) OFFSET 0CH (WRITE)...................................................................................20
4.8 RECEIVE STATUS REGISTER (RSR) OFFSET 0CH (READ)...................................................................................20
4.9 INTER-FRAME GAP (IFG) OFFSET 16H (READ/WRITE).......................................................................................21
4.10 INTER-FRAME GAP SEGMENT 1(IFGS1) OFFSET 12H (READ/WRITE)................................................................21
4.11 INTER-FRAME GAP SEGMENT 2(IFGS2) OFFSET 13H (READ/WRITE)................................................................21
4.12 MII/EEPROM MANAGEMENT REGISTER (MEMR) OFFSET 14H (READ/WRITE)...............................................21
4.13 TEST REGISTER (TR) OFFSET 15H (WRITE)....................................................................................................21
4.14 SPP DATA PORT REGISTER (SPP_DPR) OFFSET 18H (READ/WRITE)...............................................................22
4.15 SPP STATUS PORT REGISTER (SPP_SPR) OFFSET 19H (READ)........................................................................ 22
4.16 SPP COMMAND PORT REGISTER (SPP_CPR) OFFSET 1AH (READ/WRITE) ...................................................... 22
5.0 CPU I/O READ AND WRITE FUNCTIONS..................................................................................................23
5.1 ISA BUS TYPE ACCESS FUNCTIONS.....................................................................................................................23
5.2 80186 CPU BUS TYPE ACCESS FUNCTIONS. ........................................................................................................23
5.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS.......................................................................................................24
5.4 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................24
6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................25
6.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................25
6.2 GENERAL OPERATION CONDITIONS ................................................................................................................... 25
6.3 DC CHARACTERISTICS...................................................................................................................................... 25
6.4 A.C. TIMING CHARACTERISTICS........................................................................................................................26
6.4.1 XTAL / CLOCK......................................................................................................................................... 26
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AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
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6.4.2 Reset Timing.............................................................................................................................................26
6.4.3 ISA Bus Access Timing..............................................................................................................................27
6.4.4 80186 Type I/O Access Timing..................................................................................................................28
6.4.5 68K Type I/O Access Timing.....................................................................................................................29
6.4.6 8051 Bus Access Timing ...........................................................................................................................30
6.4.7 MII Timing................................................................................................................................................31
6.4.8 SNI Timing................................................................................................................................................32
7.0 PACKAGE INFORMATION........................................................................................................................... 33
APPENDIX A: APPLICATION NOTE................................................................................................................. 34
A.1 USING CRYSTAL 25MHZ OR 20MHZ.................................................................................................................34
A.2 USING OSCILLATOR 25MHZ OR 20MHZ............................................................................................................34
A.3 USING 60MHZ OSCILLATOR/CRYSTAL..............................................................................................................34
A.4 DUAL POWER (5V AND 3.3V/3.0V) APPLICATION ..............................................................................................35
A.5 SINGLE POWER (3.3V/3.0V) APPLICATION......................................................................................................... 35
A.6 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY .............................................................................36
ERRATA OF AX88196 VERSION ED2................................................................................................................. 37
DEMONSTRATION CIRCUIT : AX88196 + ETHERNET PHY + HOMEPNA 1M8 PHY..............................38
FIGURES
FIG - 1 AX88196 BLOCK DIAGRAM ..............................................................................................................................4
FIG - 2 AX88196 PIN CONNECTION DIAGRAM...............................................................................................................5
FIG - 3 AX88196 PIN CONNECTION DIAGRAM FOR ISA BUS MODE................................................................................ 6
FIG - 4 AX88196 PIN CONNECTION DIAGRAM FOR 80X86 MODE...................................................................................7
FIG - 5 AX88196 PIN CONNECTION DIAGRAM FOR MC68K MODE ................................................................................8
FIG - 6 AX88196 PIN CONNECTION DIAGRAM FOR MCS-51 MODE................................................................................9
TABLES
TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP................................................................................................... 11
TAB - 2 MII INTERFACE SIGNALS GROUP......................................................................................................................11
TAB - 3 EEPROM BUS INTERFACE SIGNALS GROUP...................................................................................................... 12
TAB - 4 SERIAL NETWORK INTERFACE PINS GROUP ......................................................................................................12
TAB - 5 STANDARD PRINTER PORT INTERFACE PINS GROUP ..........................................................................................13
TAB - 6 POWER ON CONFIGURATION SETUP PINS GROUP................................................................................................13
TAB - 7 MISCELLANEOUS PINS GROUP..........................................................................................................................14
TAB - 8 I/O ADDRESS MAPPING..................................................................................................................................15
TAB - 9 LOCAL MEMORY MAPPING.............................................................................................................................15
TAB - 10 PAGE 0 OF MAC CORE REGISTERS MAPPING.................................................................................................16
TAB - 11 PAGE 1 OF MAC CORE REGISTERS MAPPING.................................................................................................17
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AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
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1.0 Introduction
1.1 General Description:
The AX88196 provides industrial standard NE2000 registers level compatable instruction set. Various
drivers are easy acquired, maintenance and usage. No much additional effort to be paid. Software is easily
port to various embedded system with no pain and tears
The AX88196 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet
Controller with embedded 8K*16 bit SRAM. The AX88196 supports both 8 bit and 16 bit local CPU
interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88196 implements
both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and
supports both 10Mbps/100Mbps media-independent interface (MII) and legacy pure 10Mbps SNI interface
to simplify the design. Using Serial Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC
type media can be supported.
As well as, the chip also provides Standard Print Port ( parallel port interface ), can be used for printer server
device or treat as simple general I/O port.
The main difference between AX88196 and AX88195 are : 1) Replace memory I/F with SNI and SPP I/F. 2)
Canceling SAX address decoding. 3) Fix interrupt status can’t always clean up problem of AX88195.
AX88196 use 128-pin LQFP low profile package, 25MHz operation, dual 5V and 3.3V CMOS process with
5V I/O tolerance or pure 3.3V operation.
1.2 AX88196 Block Diagram:
Fig - 1 AX88196 Block Diagram
MAC
Core
8K* 16 SRAM
and Memory Arbiter
Remote
DMA
FIFOs
NE2000
Registers
Host Interface
STA
SEEPROM
I/F
SD[15:0]
SA[9:0]
Ctl BUS
MII I/F
EECS
EECK
EEDI
EEDO
SNI I/F
SPP
/ GIO
Print Port
or
General
I/O
SMDC
SMDIO
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AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
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1.3 AX88196 Pin Connection Diagram
The AX88196 is housed in the 128-pin plastic light quad flat pack. Fig - 2 AX88196 Pin Connection
Diagram shows the AX88196 pin connection diagram.
Fig - 2 AX88196 Pin Connection Diagram
123
118
122
78
70
54
41
32
24
12
8
LVDD
117
75
57
42
26
31
21
SA[1]
VSS
107
105
66
65
63
60
25
16
13
3
7
VSS
LCLK/XTALIN
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
28
22
9
HVDD
NC
126
119
110
121
797480
72
46
29
52
10
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
VSS
40
37
50
18
14
AX88196
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
103
104
829181
86
93
94
84
87
95
96
90
8892858983
98
97
99
100
102
101
VSS
LVDD
SD[0]
SD[1]
SD[2]
SD[3]
SA[0]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
/IOWR
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[6]
SD[4]
SD[5]
SD[7]
RESET
/BHE
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
/RESET
RDY/DTACK
IRQ
/CS
SAL[0]
SAL[1]
SAL[2]
SAH[1]
SAH[2]
/IOCS16
AEN/PSEN
/IORD
R/W
/LDS
/UDS
64
CLKO
SAH[0]
NC
NC
NC
/IRQ
HVDD
PD0
/ERR
SLCT
PE
/ACK
BUSY
/STRB
/ATFD
/INIT
/SLIN
LVDD
LVDD
VSS
VSS
IO_BASE[2]
IO_BASE[1]
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SCRS
TX_EN
TX_CLK
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
SRXD
SRXC
/SLINK
STXE
STXD
STXC
SCOL
RX_ER
TXD[0]
VSS
VSS
VSS
HVDD
IO_BASE[0]
CPU[1]
CPU[0]
NC
TEST
NC
NC
NC
NC
/CLK_DIV3
Page 6
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
6
1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode
Fig - 3 AX88196 Pin Connection Diagram for ISA Bus Mode
123
118
122
78
70
54
41
32
24
12
8
LVDD
117
75
57
42
26
31
21
SA[1]
VSS
107
105
66
65
63
60
25
16
13
3
7
VSS
LCLK/XTALIN
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
28
22
9
HVDD
NC
126
119
110
121
797480
72
46
29
52
10
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
VSS
40
37
50
18
14
AX88196
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
(for ISA Bus I/F)
103
104
829181
86
93
94
84
87
95
96
90
8892858983
98
97
99
100
102
101
VSS
LVDD
SD[0]
SD[1]
SD[2]
SD[3]
SA[0]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
/IOWR
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[6]
SD[4]
SD[5]
SD[7]
RESET
/BHE
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
/RESET
RDY
IRQ
/CS
SAL[0]
SAL[1]
SAL[2]
SAH[1]
SAH[2]
/IOCS16
AEN
/IORD
64
CLKO
SAH[0]
NC
NC
NC
HVDD
PD0
/ERR
SLCT
PE
/ACK
BUSY
/STRB
/ATFD
/INIT
/SLIN
LVDD
LVDD
VSS
VSS
IO_BASE[2]
IO_BASE[1]
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SCRS
TX_EN
TX_CLK
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
SRXD
SRXC
/SLINK
STXE
STXD
STXC
SCOL
RX_ER
TXD[0]
VSS
VSS
VSS
HVDD
IO_BASE[0]
CPU[1]
CPU[0]
NC
TEST
NC
NC
NC
NC
/CLK_DIV3
Page 7
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
7
1.3.2 AX88196 Pin Connection Diagram for 80x86 Mode
Fig - 4 AX88196 Pin Connection Diagram for 80x86 Mode
123
118
122
78
70
54
41
32
24
12
8
LVDD
117
75
57
42
26
31
21
SA[1]
VSS
107
105
66
65
63
60
25
16
13
3
7
VSS
LCLK/XTALIN
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
28
22
9
HVDD
NC
126
119
110
121
79
748072
46
29
52
10
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
VSS
40
37
50
18
14
AX88196
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
(for x86 Interface)
103
104
829181
86
93
94
84
87
95
96
90
8892858983
98
97
99
100
102
101
VSS
LVDD
SD[0]
SD[1]
SD[2]
SD[3]
SA[0]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
/IOWR
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[6]
SD[4]
SD[5]
SD[7]
RESET
/BHE
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
/RESET
RDY
IRQ
/CS
SAL[0]
SAL[1]
SAL[2]
SAH[1]
SAH[2]
/IORD
64
CLKO
SAH[0]
NC
NC
NC
HVDD
PD0
/ERR
SLCT
PE
/ACK
BUSY
/STRB
/ATFD
/INIT
/SLIN
LVDD
LVDD
VSS
VSS
IO_BASE[2]
IO_BASE[1]
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SCRS
TX_EN
TX_CLK
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
SRXD
SRXC
/SLINK
STXE
STXD
STXC
SCOL
RX_ER
TXD[0]
VSS
VSS
VSS
HVDD
IO_BASE[0]
CPU[1]
CPU[0]
NC
TEST
NC
NC
NC
NC
/CLK_DIV3
NC
NC
Page 8
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
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1.3.3 AX88196 Pin Connection Diagram for MC68K Mode
Fig - 5 AX88196 Pin Connection Diagram for MC68K Mode
123
118
122
78
70
54
41
32
24
12
8
LVDD
117
75
57
42
26
31
21
SA[1]
VSS
107
105
66
65
63
60
25
16
13
3
7
VSS
LCLK/XTALIN
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
28
22
9
HVDD
NC
126
119
110
121
797480
72
46
29
52
10
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
VSS
40
37
50
18
14
AX88196
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
(for 68K Interface)
103
104
829181
86
93
94
84
87
95
96
90
8892858983
98
97
99
100
102
101
VSS
LVDD
SD[0]
SD[1]
SD[2]
SD[3]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[6]
SD[4]
SD[5]
SD[7]
RESET
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
/RESET
/DTACK
/CS
SAL[0]
SAL[1]
SAL[2]
SAH[1]
SAH[2]
R/W
/LDS
/UDS
64
CLKO
SAH[0]
NC
NC
NC
/IRQ
HVDD
PD0
/ERR
SLCT
PE
/ACK
BUSY
/STRB
/ATFD
/INIT
/SLIN
LVDD
LVDD
VSS
VSS
IO_BASE[2]
IO_BASE[1]
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SCRS
TX_EN
TX_CLK
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
SRXD
SRXC
/SLINK
STXE
STXD
STXC
SCOL
RX_ER
TXD[0]
VSS
VSS
VSS
HVDD
IO_BASE[0]
CPU[1]
CPU[0]
NC
TEST
NC
NC
NC
NC
/CLK_DIV3
NC
NC
NC
Page 9
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
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1.3.4 AX88196 Pin Connection Diagram for MCS-51 Mode
Fig - 6 AX88196 Pin Connection Diagram for MCS-51 Mode
123
118
122
78
70
54
41
32
24
12
8
LVDD
117
75
57
42
26
31
21
SA[1]
VSS
107
105
66
65
63
60
25
16
13
3
7
VSS
LCLK/XTALIN
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
28
22
9
HVDD
NC
126
119
110
121
797480
72
46
29
52
10
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
VSS
40
37
50
18
14
AX88196
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
(for MCS-51 Interface)
103
104
829181
86
93
94
84
87
95
96
90
8892858983
98
97
99
100
102
101
VSS
LVDD
SD[0]
SD[1]
SD[2]
SD[3]
SA[0]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
/IOWR
SD[6]
SD[4]
SD[5]
SD[7]
RESET
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
/RESET
/CS
SAL[0]
SAL[1]
SAL[2]
SAH[1]
SAH[2]
/PSEN
/IORD
64
CLKO
SAH[0]
NC
NC
NC
/IRQ
HVDD
PD0
/ERR
SLCT
PE
/ACK
BUSY
/STRB
/ATFD
/INIT
/SLIN
LVDD
LVDD
VSS
VSS
IO_BASE[2]
IO_BASE[1]
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SCRS
TX_EN
TX_CLK
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
SRXD
SRXC
/SLINK
STXE
STXD
STXC
SCOL
RX_ER
TXD[0]
VSS
VSS
VSS
HVDD
IO_BASE[0]
CPU[1]
CPU[0]
NC
TEST
NC
NC
NC
NC
/CLK_DIV3
NC
NC
NC
NCNCNCNCNC
NCNCNC
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2.0 Signal Description
The following terms describe the AX88196 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I Input PU Pull Up
O Output PD Pull Down
I/O Input/Output P Power Pin
OD Open Drain
2.1 Local CPU Bus Interface Signals Group
SIGNAL TYPE PIN NO. DESCRIPTION
SAL[2:0] I/PD 113 – 111 System Address Select Low : Signals SAL[2:0] are additional address
signal input lines which active low enable higher I/O address decoder
on chip.
SAH[2:0] I/PU 116 – 114 System Address Select High : Signals SAH[2:0] are additional
address signal input lines which active high enable higher I/O
address decoder on chip.
SA[9:1],
SA[0]/UDS
I 10 – 1 System Address : Signals SA[9:0] are address bus input lines which
lower I/O spaces on chip. SA[0] also means Upper Data Strobe
(/UDS) active low signal in 68K application mode
/BHE
or
/LDS
I 18 Bus High Enable or Lower Data Strobe : Bus High Enable is active
low signal in some 16 bit application mode which enable high bus
(SD[15:8]) active. The signal also name as Lower Data Strobe (LDS)
for 68K application mode.
SD[15:0] I/O 20 – 23,
25 – 28,
30 – 33,
35 – 38
System Data Bus : Signals SD[15:0] constitute the bi-directional data
bus.
IREQ/IREQ O 12 Interrupt Request : When ISA BUS or 80186 CPU mode is select.
IREQ is asserted high to indicate the host system that the chip
requires host software service. When MC68K or MCS-51 CPU mode
is select. /IREQ is asserted low to indicate the host system that the
chip requires host software service.
RDY/DTACK OD 125 Ready : This signal is set low to insert wait states during Remote
DMA transfer.
/Dtack : When Motorola CPU type is select, the pin is active low
inform CPU that data is accepted.
/CS I 123 Chip Select
When the /CS signal is asserted, the chip is selected.
/IORD I 15 I/O Read :The host asserts /IORD to read data from AX88196 I/O
space. When Motorola CPU type is select , the pin is useless.
/IOWR
or
R/W
I 14 I/O Write :The host asserts /IOWR to write data into AX88196 I/O
space. When Motorola CPU type is select, the pin is active high for
read operation at the same time.
/OCS16 OD 120 I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the
range corresponds to an I/O address to which the chip responds, and
the I/O port addressed is capable of 16-bit access.
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AEN
or
/PSEN
I/PD 124 Address Enable : The signal is asserted when the address bus is
available for DMA cycle. When negated (low), AX88196 an I/O slave
device may respond to addresses and I/O command.
PSEN : This signal is active low for 8051 program access. For I/O
device, AX88196, this signal is active high to access the chip. This
signal is for 8051 bus application only.
Tab - 1 Local CPU bus interface signals group
2.2 MII interface signals group
SIGNAL TYPE PIN NO. DESCRIPTION
RXD[3:0] I 90 – 87 Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
CRS I 85 Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
RX_DV I 83 Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
RX_ER I 82 Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
RX_CLK I 86 Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
COL I 84 Collision : this signal is driven by PHY when collision is detected.
TX_EN O 95 Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
TXD[3:0] O 99 – 96 Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
TX_CLK I 94 Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
MDC O 92 Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
MDIO I/O/PU 91 Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
Tab - 2 MII interface signals group
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2.3 EEPROM Signals Group
SIGNAL TYPE PIN NO. DESCRIPTION
EECS O 106 EEPROM Chip Select : EEPROM chip select signal.
EECK O 107 EEPROM Clock : Signal connected to EEPROM clock pin.
EEDI O 108 EEPROM Data In : Signal connected to EEPROM data input pin.
EEDO I/PU 109 EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 3 EEPROM bus interface signals group
2.4 SNI Interface pins group
SIGNAL TYPE PIN NO. DESCRIPTION
STXC I 66 Transmit Clock : this signal is driven by PHY with 20MHz clock.
STXD O 68 Transmit Data : STXD is transition synchronously with respect to the
rising edge of STXC. For each STXC period in which STXE is
asserted, STXD is accepted for transmission by the PHY.
STXE O 70 Transmit Enable : STXE is transition synchronously with respect to
the rising edge of STXC. STXE indicates that the port is presenting
data on STXD for transmission.
SCOL I 76 Collision : this signal is driven by PHY when collision is detected.
SRXC I 78 Receive Clock : SRXC is driven by PHY for received data
synchronization.
SRXD I 79 Receive Data : SRXD is driven by the PHY synchronously with respect
to SRXC.
SCRS I 80 Carrier Sense : Asynchronous signal SCRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
/SLINK I/PU 74 Link indicator : Active low indicate the SNI interface is link to
network. When SNI is not used must keep the pin no connection or
pull high the signal.
Tab - 4 Serial Network Interface pins group
2.5 Standard Printer Port Interface pins group
SIGNAL TYPE PIN NO. DESCRIPTION
PD[7:0] I/O/PU 52, 53
55-58
60, 61
Parallel Data :The bi-directional parallel data bus is used to transfer
information between CPU and peripherals. Default serve as input,
using /DOE bit of register offset x1Ah to set the direction.
BUSY I 46 Busy : This is a status input from the printer, high indicating that the
printer is not ready to receive new data.
/ACK I 47 Acknowledge : A low active input from the printer indicating that it
has received the data and is ready to accept new data.
PE I 48 Paper Empty : A status input from the printer, high indicating that the
printer is out of paper.
SLCT I 50 Slect : This high active input from the printer indicating that it has
power on.
/ERR I 51 Error : A low active input from the printer indicating that there is an
error condition at the printer.
/SLCTIN O 41 Slect In : This active low output selects the printer.
/INIT O 42 Init : This signal is used to initiate the printer when low.
/ATFD O 43 Auto Feed :This output goes low to cause the printer to automatically
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feed one line after each line is printed.
/STRB O 45 Strobe : A low active pulse on this output is used to strobe the print
data into the printer.
Tab - 5 Standard Printer Port Interface pins group
2.6 Power on configuration setup signals pins group
SIGNAL TYPE PIN NO. DESCRIPTION
IO_BASE[2:0] I /PU 62, 63,65 IO_BASE[2] IO_BASE[1] IO_BASE[0] IO_BASE
0 0 0 300h
0 0 1 320h
0 1 0 340h
0 1 1 360h
1 0 0 380h
1 0 1 3A0h
1 1 0 200h
1 1 1 220h
CPU[1:0] I/PU 71, 72 CPU[1] CPU[0] CPU TYPE
0 0 ISA BUS
0 1 80186
1 0 MC68K
1 1 MCS-51 (805X)
Tab - 6 Power on configuration setup pins group
2.7 Miscellaneous pins group
SIGNAL TYPE PIN NO. DESCRIPTION
LCLK/XTALIN I 103 CMOS Local Clock : A 25Mhz clock, +/- 100 ppm, 40%-60% duty
cycle.
Crystal Oscillator Input : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT.
XTALOUT O 104 Crystal Oscillator Output : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
CLKO O 101 Clock Output : This clock is source from LCLK/XTALIN.
/CLK_DIV3 I/PU 67 Clock Devide 3 Enable : Active low to enable the devided 3 circuit.
That internally devides LCLK/XTALIN input frequeny by 3 and then
feed into internal circuit for system clock used.
Default value set to logic high, this function is disabled.
RESET I/PD 127 Reset :
Reset is active high then place AX88196 into reset mode immediately.
During Falling edge the AX88196 loads the power on setting data.
User can select either RESET or /RESET for applications.
/RESET I/PU 126 /Reset :
Reset is active low then place AX88196 into reset mode immediately.
During rising edge the AX88196 loads the power on setting data.
User can select either RESET or /RESET for applications.
/TEST I/PU 77
Test Pin : Active LOW
The pin is just for test mode setting purpose only. Must be pull high
when normal operation.
NC N/A 13, 16, 17,
39, 73, 117,
No Connection : for manufacturing test only.
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118, 121, 122
LVDD P 44, 54,
100, 110,
128
Power Supply : +3.3V DC.
HVDD P 19, 29, 64,75Power Supply : +5V DC.
Note : for pure 3.3V single power solution, all the HVDD pin can
connect to +3.3V. Care should be taken that HVDD input power must
be greater or equal ( > = ) than LVDD.
VSS P 11, 24, 34,
40, 49,59,
69, 81,93,
102, 105,
119
Power Supply : +0V DC or Ground Power.
Tab - 7 Miscellaneous pins group
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3.0 Memory and I/O Mapping
There are four memory or I/O mapping used in AX88196.
1. EEPROM Memory Mapping
2. I/O Mapping
3. Local Memory Mapping
3.1 EEPROM Memory Mapping
User can define by themselves and can access via I/O address offset 14H MII/EEPROM registers
3.2 I/O Mapping
SYSTEM I/O OFFSET FUNCTION
0000H
001FH
MAC CORE REGISTER
Tab - 8 I/O Address Mapping
3.3 SRAM Memory Mapping
OFFSET FUNCTION
4000H
7FFF
NE2000 COMPATABLE MODE
8K X 16 SRAM BUFFER
Tab - 9 Local Memory Mapping
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4.0 Registers Operation
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the
Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET READ WRITE
00H Command Register
( CR )
Command Register
( CR )
01H Page Start Register
( PSTART )
Page Start Register
( PSTART )
02H Page Stop Register
( PSTOP )
Page Stop Register
( PSTOP )
03H Boundary Pointer
( BNRY )
Boundary Pointer
( BNRY )
04H Transmit Status Register
( TSR )
Transmit Page Start Address
( TPSR )
05H Number of Collisions Register
( NCR )
Transmit Byte Count Register 0
( TBCR0 )
06H Current Page Register
( CPR )
Transmit Byte Count Register 1
( TBCR1 )
07H Interrupt Status Register
( ISR )
Interrupt Status Register
( ISR )
08H Current Remote DMA Address 0
( CRDA0 )
Remote Start Address Register 0
( RSAR0 )
09H Current Remote DMA Address 1
( CRDA1 )
Remote Start Address Register 1
( RSAR1 )
0AH Reserved Remote Byte Count 0
( RBCR0 )
0BH Reserved Remote Byte Count 1
( RBCR1 )
0CH Receive Status Register
( RSR )
Receive Configuration Register
( RCR )
0DH Frame Alignment Errors
( CNTR0 )
Transmit Configuration Register ( TCR )
0EH CRC Errors
( CNTR1 )
Data Configuration Register
( DCR )
0FH Missed Packet Errors
( CNTR2 )
Interrupt Mask Register
( IMR )
10H, 11H Data Port Data Port
12H IFGS1 IFGS1
13H IFGS2 IFGS2
14H MII/EEPROM Access MII/EEPROM Access
15H - Test Register
16H Inter-frame Gap (IFG) Inter-frame Gap (IFG)
17H Reserved Reserved
18H - 1AH Standard Printer Port (SPP) Standard Printer Port (SPP)
1BH - 1EH Reserved Reserved
1FH Reset Reserved
Tab - 10 Page 0 of MAC Core Registers Mapping
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PAGE 1 (PS1=0,PS0=1)
OFFSET READ WRITE
00H Command Register
( CR )
Command Register
( CR )
01H Physical Address Register 0
( PARA0 )
Physical Address Register 0
( PAR0 )
02H Physical Address Register 1
( PARA1 )
Physical Address Register 1
( PAR1 )
03H Physical Address Register 2
( PARA2 )
Physical Address Register 2
( PAR2 )
04H Physical Address Register 3
( PARA3 )
Physical Address Register 3
( PAR3 )
05H Physical Address Register 4
( PARA4 )
Physical Address Register 4
( PAR4 )
06H Physical Address Register 5
( PARA5 )
Physical Address Register 5
( PAR5 )
07H Current Page Register
( CPR )
Current Page Register
( CPR )
08H Multicast Address Register 0
( MAR0 )
Multicast Address Register 0
( MAR0 )
09H Multicast Address Register 1
( MAR1 )
Multicast Address Register 1
( MAR1 )
0AH Multicast Address Register 2
( MAR2 )
Multicast Address Register 2
( MAR2 )
0BH Multicast Address Register 3
( MAR3 )
Multicast Address Register 3
( MAR3 )
0CH Multicast Address Register 4
( MAR4 )
Multicast Address Register 4
( MAR4 )
0DH Multicast Address Register 5
( MAR5 )
Multicast Address Register 5
( MAR5 )
0EH Multicast Address Register 6
( MAR6 )
Multicast Address Register 6
( MAR6 )
0FH Multicast Address Register 7
( MAR7 )
Multicast Address Register 7
( MAR7 )
10H, 11H Data Port Data Port
12H Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 1
IFGS1
13H Inter-frame Gap Segment 2
IFGS2
Inter-frame Gap Segment 2
IFGS2
14H MII/EEPROM Access MII/EEPROM Access
15H - Test Register
16H Inter-frame Gap (IFG) Inter-frame Gap (IFG)
17H Reserved Reserved
18H - 1AH Standard Printer Port (SPP) Standard Printer Port (SPP)
1BH - 1EH Reserved Reserved
1FH Reset Reserved
Tab - 11 Page 1 of MAC Core Registers Mapping
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4.1 Command Register (CR) Offset 00H (Read/Write)
FIELD NAME DESCRIPTION
7:6 PS1,PS0 PS1,PS0 : Page Select
The two bit selects which register page is to be accessed.
PS1 PS0
0 0 page 0
0 1 page 1
5:3 RD2,RD1
,RD0
RD2,RD1,RD0 : Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88196 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address are not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0 0 0 Not allowed
0 0 1 Remote Read
0 1 0 Remote Write
0 1 1 Not allowed
1 X X Abort / Complete Remote DMA
2 TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
1 START START :
This bit is used to active AX88196 operation.
0 STOP STOP : Stop AX88196
This bit is used to stop the AX88196 operation.
4.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD NAME DESCRIPTION
7 RST Reset Status :
Set when AX88196 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
6 RDC Remote DMA Complete
Set when remote DMA operation has been completed
5 CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
4 OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
3 TXE Transmit Error
Set when packet transmitted with one or more of the following errors
n Excessive collisions
n FIFO Underrun
2 RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
1 PTX Packet Transmitted
Indicates packet transmitted with no error
0 PRX Packet Received
Indicates packet received with no error.
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4.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD NAME DESCRIPTION
7 - Reserved
6 RDCE DMA Complete Interrupt Enable. Default “low” disabled.
5 CNTE Counter Overflow Interrupt Enable. Default “low” disabled.
4 OVWE Overwrite Interrupt Enable. Default “low” disabled.
3 TXEE Transmit Error Interrupt Enable. Default “low” disabled.
2 RXEE Receive Error Interrupt Enable. Default “low” disabled.
1 PTXE Packet Transmitted Interrupt Enable. Default “low” disabled.
0 PRXE Packet Received Interrupt Enable. Default “low” disabled.
4.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD NAME DESCRIPTION
7 RDCR Remote DMA always completed
6:2 - Reserved
1 BOS Byte Order Select
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80186).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(MC68K)
0 WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
4.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD NAME DESCRIPTION
7 FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
6 PD Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
5 RLO Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
4:3 - Reserved
2:1 LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0 0 0 Normal operation
Mode 1 0 1 Internel NIC loop-back
Mode 2 1 0 PHYcevisor loop-back
0 CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
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4.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD NAME DESCRIPTION
7 OWC Out of window collision
6:4 - Reserved
3 ABT Transmit Aborted
Indicates the AX88196 aborted transmission because of excessive collision.
2 COL Transmit Collided
Indicates that the transmission collided at least once with another station on the network.
1 - Reserved
0 PTX Packet Transmitted
Indicates transmission without error.
4.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD NAME DESCRIPTION
7 - Reserved
6 INTT Interrupt Trigger Mode for ISA and 80186 modes
0 : Low active
1 : High active (default)
Interrupt Trigger Mode for MCS-51 and MC68K modes
0 : High active
1 : Low active (default)
5 MON Monitor Mode
0 : Normal Operation
1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
4 PRO PRO : Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
3 AM AM : Accept Multicast
Enable the receiver to accept packets with a multicast address. That multicast address must
pass the hashing array.
2 AB AB : Accept Broadcast
Enable the receiver to accept broadcast packet.
1 AR AR : Accept Runt
Enable the receiver to accept runt packet.
0 SEP SEP : Save Error Packet
Enable the receiver to accept and save packets with error.
4.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD NAME DESCRIPTION
7 - Reserved
6 DIS Receiver Disabled
5 PHY Multicast Address Received.
4 MPA Missed Packet
3 FO FIFO Overrun
2 FAE Frame alignment error.
1 CR CRC error.
0 PRX Packet Received Intact
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4.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD NAME DESCRIPTION
7 - Reserved
6:0 IFG Inter-frame Gap. Default value 15H.
4.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD NAME DESCRIPTION
7 - Reserved
6:0 IFG Inter-frame Gap Segment 1. Default value 0cH.
4.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD NAME DESCRIPTION
7 - Reserved
6:0 IFG Inter-frame Gap Segment 2. Default value 11H.
4.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
FIELD NAME DESCRIPTION
7 EECLK EECLK
EEPROM Clock
6 EEO EEO
EEPROM Data Out
5 EEI EEI
EEPROM Data In
4 EECS EECS
EEPROM Chip Select
3 MDO MDO
MII Data Out
2 MDI MDI
MII Data In
1 MDIR MII STA MDIO signal Direction
MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
0 MDC MDC
MII Clock
4.13 Test Register (TR) Offset 15H (Write)
FIELD NAME DESCRIPTION
7 - Reserved
6 MPSEL Media Priority Select : default value is logic 0
MPSEL /SLINK Media Selected
0 0 SNI
0 1 MII
1 x Depand on MPSET bit
5 MPSET Media Set by Program : The signal is valid only when MPSEL is set to high.
When MPSET is logic 0 , SNI is selected.
When MPSET is logic 1 , MII is selected.
4 TF16T Test for Collision, default value is logic 0
3 TPE Test pin Enable, default value is logic 0
2:0 IFG Select Test Pins Output, default value is logic 0
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4.14 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write)
FIELD NAME DESCRIPTION
7:0 DP Printer Data Port
4.15 SPP Status Port Register (SPP_SPR) Offset 19H (Read)
FIELD NAME DESCRIPTION
7 /BUSY Reading a ‘0’ indicates that the printer is not ready to receive new data.
6 /ACK Reading a ‘0’ indicates that the printer has received the data and is ready to accept new data.
5 PE Reading a ‘ 1’ indicates that the printer is out of paper.
4 SLCT Reading a ‘ 1’ indicates that the printer has power on.
3 /ERR Reading a ‘0’ indicates that there is an error condition at the printer.
2:0 - Reserved
4.16 SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write)
FIELD NAME DESCRIPTION
7:6 - Reserved
5 /DOE Seting to ‘ 0’ enable print data output to printer. Default sets to ‘ 1’ .
4 IRQEN IRQ enable : printer port interrupt is not supportted.
3 SLCTIN Seting to ‘1’ selects the printer.
2 /INIT Seting to ‘ 0’ initiates the printer
1 ATFD Seting to ‘ 1’ causes the printer to automatically feed one line after each line is printed.
0 STRB Seting a low-high-low pulse on this register is used to strobe the print data into the printer.
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5.0 CPU I/O Read and Write Functions
The AX88196 supports four kinds of CPU/BUS types access function, including ISA, 80186, MC68000 and MCS-
51. These Access methods are described as the following sections.
5.1 ISA bus type access functions.
ISA bus I/O Read function
Function Mode /CS /BHE A0 /IORD /IOWR SD[15:8] SD[7:0]
Standby Mode H X X X X High-Z High-Z
Byte Access L
L
H
H
L
H
L
L
H
H
Not Valid
Not Valid
Even-Byte
Odd-Byte
Word Access L L L L H Odd-Byte Even-Byte
ISA bus I/O Write function
Function Mode /CS /BHE A0 /IORD /IOWR SD[15:8] SD[7:0]
Standby Mode H X X X X X X
Byte Access L
L
H
H
L
H
H
H
L
L
X
X
Even-Byte
Odd-Byte
Word Access L L L H L Odd-Byte Even-Byte
5.2 80186 CPU bus type access functions.
80186 CPU bus I/O Read function
Function Mode /CS /BHE A0 /IORD /IOWR SD[15:8] SD[7:0]
Standby Mode H X X X X High-Z High-Z
Byte Access L
L
H
L
L
H
L
L
H
H
Not Valid
Odd-Byte
Even-Byte
Not Valid
Word Access L L L L H Odd-Byte Even-Byte
80186 CPU bus I/O Write function
Function Mode /CS /BHE A0 /IORD /IOWR SD[15:8] SD[7:0]
Standby Mode H X X X X X X
Byte Access L
L
H
L
L
H
H
H
L
L
X
Odd-Byte
Even-Byte
X
Word Access L L L H L Odd-Byte Even-Byte
Page 24
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
24
5.3 MC68K CPU bus type access functions.
68K bus I/O Read function
Function Mode /CS /UDS /LDS R/W SD[15:8] SD[7:0]
Standby Mode H X X X High-Z High-Z
Byte Access L
L
H
L
L
H
H
H
Not Valid
Even-Byte
Odd-Byte
Not Valid
Word Access L L L H Even-Byte Odd-Byte
68K bus I/O Write function
Function Mode /CS /UDS /LDS R/W SD[15:8] SD[7:0]
Standby Mode H X X X X X
Byte Access L
L
H
L
L
H
L
L
X
Even-Byte
Odd-Byte
X
Word Access L L L L Even-Byte Odd-Byte
5.4 MCS-51 CPU bus type access functions.
8051 bus I/O Read function
Function Mode /CS /PSEN SA0 /IORD /IOWR SD[15:8] SD[7:0]
Standby Mode H
X
X
L
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Byte Access L
L
H
H
L
H
L
L
H
H
Not Valid
Not Valid
Even-Byte
Odd-Byte
8051 bus I/O Write function
Function Mode /CS /PSEN SA0 /IORD /IOWR SD[15:8] SD[7:0]
Standby Mode H
X
X
L
X
X
X
X
X
X
X
X
X
X
Byte Access L
L
H
H
L
H
H
H
L
L
X
X
Even-Byte
Odd-Byte
Page 25
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
25
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description SYM Min Max Units
Operating Temperature Ta 0 +85
°C
Storage Temperature Ts -55 +150
°C
Supply Voltage HVdd -0.3 +6 V
Supply Voltage LVdd -0.3 +4.6 V
Input Voltage HVin
LVin
-0.3
-0.3
HVdd+0.5
LVdd+0.5
V
V
Output Voltage HVout
LVin
-0.3
-0.3
HVdd+0.5
LVdd+0.5
V
V
Lead Temperature (soldering 10 seconds maximum) Tl -55 +220
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.2 General Operation Conditions
Description SYM Min Tpy Max Units
Operating Temperature Ta 0 25 +75
°C
Supply Voltage HVdd
LVdd
+4.75V
+2.70
+3.00
+5.00V
+3.00
+3.30
+5.25V
+3.30
+3.60
V
V
V
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.3 DC Characteristics
(Vdd=5.0V, Vss=0V, Ta=0°C to 75°C)
Description SYM Min Tpy Max Units
Low Input Voltage Vil - 0.8 V
High Input Voltage Vih 2 - V
Low Output Voltage Vol - 0.4 V
High Output Voltage Voh Vdd-0.4 - V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C)
Description SYM Min Tpy Max Units
Low Input Voltage Vil - 0.8 V
High Input Voltage Vih 1.9 - V
Low Output Voltage Vol - 0.4 V
High Output Voltage Voh Vdd-0.4 - V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA
Description SYM Min Tpy Max Units
Power Consumption (Dual power) DPt5v
DPt3v
20
32
mA
mA
Power Consumption (Single power 3.3V) SPt3v 50 mA
Page 26
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
26
6.4 A.C. Timing Characteristics
6.4.1 XTAL / CLOCK
LCLK/XTALIN
Tr Tf Tlow
CLKO Tod
Symbol Description Min Typ. Max Units
Tcyc CYCLE TIME
40* ns
Thigh CLK HIGH TIME
16 20 24 ns
Tlow CLK LOW TIME
16 20 24 ns
Tr/Tf CLK SLEW RATE
1 - 4 ns
Tod LCLK/XTALIN TO CLKO OUT DELAY
10
* Note : The Tcyc can be from 16.6ns to 50ns, that is frequency from 60MHz to 20MHz.
6.4.2 Reset Timing
LCLK/XTALIN
RESET
/RESET
Symbol Description Min Typ. Max Units
Trst Reset pulse width
100 - - LClk
Tcyc
Thigh
Page 27
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
27
6.4.3 ISA Bus Access Timing
Tsu(AEN) Th(AEN)
AEN
Tsu(A) Th(A)
/BHE
SA[9:0],SAL,SAH
Tv(CS16-A) Tdis(CS16-A)
/IOCS16
Ten(RD)
/IOWR,/IORD
Tv(RDY) Tdis(RDY)
RDY
Tdis(RD)
Read Data
SD[15:0](Dout) DATA Valid
Tsu(WR) Th(WR)
Write Data
SD[15:0](Din) DATA Input Establish
Symbol Description Min Typ. Max Units
Tsu(A) ADDRESS SETUP TIME
0 - - ns
Th(A) ADDRESS HOLD TIME
5 - - ns
Tsu(AEN) AEN SETUP TIME
0 - - ns
Th(AEN) AEN HOLD TIME
5 - - ns
Tv(CS16-A) /IOCS16 VALID FROM ADDRESS CHANGE
- - 20 ns
Tdis(CS16-A) /IOCS16 DISABLE FROM ADDRESS CHANGE
- - 6 ns
Tv(RDY) RDY VALID FROM /IORD OR /IOWR
- - 20 ns
Tdis(RDY) RDY DISABLE FROM /IORD OR /IOWR
0 - - ns
Ten(RD) OUTPUT ENABLE TIME FROM /IORD
- - 20 ns
Tdis(RD) OUTPUT DISABLE TIME FROM /IORD
0.5 - 4 ns
Tsu(WR) DATA SETUP TIME
5 - - ns
Th(WR) DATA HOLD TIME
5 - - ns
Page 28
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
28
6.4.4 80186 Type I/O Access Timing
Tsu(A) Th(A)
/BHE
SA[9:0],SAL,SAH
Tw(RW)
/IOWR,/IORD
Tv(RDY) Tdis(RDY)
RDY
Ten(RD) Tdis(RD)
Read Data
SD[15:0](Dout) DATA Valid
Tsu(WR) Th(WR)
Write Data
SD[15:0](Din) DATA Input Establish
Symbol Description Min Typ. Max Units
Tsu(A) ADDRESS SETUP TIME
0 - - ns
Th(A) ADDRESS HOLD TIME
5 - - ns
Tv(RDY) RDY VALID FROM /IORD OR /IOWR
- - 20 ns
Tdis(RDY) RDY DISABLE FROM /IORD OR /IOWR
0 - - ns
Ten(RD) OUTPUT ENABLE TIME FROM /IORD
- - 20 ns
Tdis(RD) OUTPUT DISABLE TIME FROM /IORD
0.5 - 4 ns
Tsu(WR) DATA SETUP TIME
5 - - ns
Th(WR) DATA HOLD TIME
5 - - ns
Tw(RW) /IORD OR /IOWR WIDTH TIME
*60 ns
*Note : 60 ns at internal operation clock is 20MHz.
50 ns at internal operation clock is 25MHz.
Page 29
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
29
6.4.5 68K Type I/O Access Timing
Tsu(A) Th(A)
SA[9:1],SAL,SAH
Tv(DS-WR) Tw(DS) Tdis(WR-DS)
/UDS,/LDS
(Read)
R/W
Ten(DS)
(Write)
R/W
Tv(DTACK) Tdis(DTACK)
/DTACK
Tdis(DS)
(Read Data)
SD[15:0](Dout) DATA Valid
Tsu(DS) Th(DS)
(Write Data)
SD[15:0](Din) DATA Input Establish
Symbol Description Min Typ. Max Units
Tsu(A) ADDRESS SETUP TIME
0 - - ns
Th(A) ADDRESS HOLD TIME
5 - - ns
Tv(DS-WR) /UDS OR /LDS VALID FROM /W
0 - - ns
Tdis(WR-DS) /W DISABLE FROM /UDS OR /LDS
5 - - ns
Tv(DTACK) DACK VALID FROM /UDS OR /LDS
- - 20 ns
Tdis(DTACK) DACK DISABLE FROM /UDS OR /LDS
0 - - ns
Ten(DS) OUTPUT ENABLE TIME FROM /UDS OR /LDS
- - 20 ns
Tdis(DS) OUTPUT DISABLE TIME FROM /UDS OR /LDS
0.5 - 4 ns
Tsu(DS) DATA SETUP TIME
5 - - ns
Th(DS) DATA HOLD TIME
5 - - ns
Tw(DS) /UDS OR /LDS WIDTH TIME
*60 ns
*Note : 60 ns at internal operation clock is 20MHz.
50 ns at internal operation clock is 25MHz.
Page 30
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
30
6.4.6 8051 Bus Access Timing
/PSEN
Tsu(PSEN) Th(PSEN)
Tsu(A) Th(A)
SA[9:0],SAL,SAH
Ten(RD)
/IOWR,/IORD Tw(RW)
Tv(RDY) Tdis(RDY)
(For Reference)
RDY
Tdis(RD)
Read Data
SD[7:0](Dout) DATA Valid
Tsu(WR) Th(WR)
Write Data
SD[7:0](Din) DATA Input Establish
Symbol Description Min Typ. Max Units
Tsu(A) ADDRESS SETUP TIME
0 - - ns
Th(A) ADDRESS HOLD TIME
5 - - ns
Tsu(PSEN) /PSEN SETUP TIME
0 - - ns
Th(PSEN) /PSEN HOLD TIME
5 - - ns
Ten(RD) OUTPUT ENABLE TIME FROM /IORD
- - 20 ns
Tdis(RD) OUTPUT DISABLE TIME FROM /IORD
0.5 - 4 ns
Tsu(WR) DATA SETUP TIME
5 - - ns
Th(WR) DATA HOLD TIME
5 - - ns
Tw(RW) /IORD OR /IOWR WIDTH TIME
*60 ns
Note : 60 ns at internal operation clock 20MHz.
50 ns at internal operation clock 25MHz.
Page 31
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
31
6.4.7 MII Timing
Ttclk Ttch Ttcl
TXCLK
Ttv Tth
TXD<3:0>
TXEN
Trclk Trch Trcl
RXCLK
Trs Trh
RXD<3:0>
RXDV
Trs1
RXER
Symbol Description Min Typ. Max Units
Ttclk Cycle time(100Mbps)
- 40 - ns
Ttclk Cycle time(10Mbps)
- 400 - ns
Ttch high time(100Mbps)
14 - 26 ns
Ttch high time(10Mbps)
140 - 260 ns
Trch low time(100Mbps)
14 - 26 ns
Trch low time(10Mbps)
140 - 260 ns
Ttv Clock to data valid
- - 20 ns
Tth Data output hold time
5 - - ns
Trclk Cycle time(100Mbps)
- 40 - ns
Trclk Cycle time(10Mbps)
- 400 - ns
Trch high time(100Mbps)
14 - 26 ns
Trch high time(10Mbps)
140 - 260 ns
Trcl low time(100Mbps)
14 - 26 ns
Trcl low time(10Mbps)
140 - 260 ns
Trs data setup time
6 - - ns
Trh data hold time
10 - - ns
Trs1 RXER data setup time
10 - - ns
Page 32
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
32
6.4.8 SNI Timing
Ttclk Ttch Ttcl
STXC
Ttv Tth
STXD
STXE
Trclk Trch Trcl
SRXC
Trs Trh
SRXD
SCRS
Symbol Description Min Typ. Max Units
Ttclk Cycle time(10Mbps)
- 100 - ns
Ttch high time(10Mbps)
45 - 55 ns
Trch low time(10Mbps)
45 - 55 ns
Ttv Clock to data valid
- - 26 ns
Tth Data output hold time
5 - - ns
Trclk Cycle time(10Mbps)
- 100 - ns
Trch high time(10Mbps)
45 - 55 ns
Trcl low time(10Mbps)
45 - 55 ns
Trs data setup time
10 - - ns
Trh data hold time
5 - - ns
Page 33
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
33
7.0 Package Information
b
e
D
Hd
E
He
pin 1
A2 A1
L
L1
θ
A
MILIMETERSYMBOL
MIN. NOM MAX
A1 0.1
A2 1.3 1.4 1.5
A 1.7
b 0.155 0.16 0.26
D 13.90 14.00 14.10
E 13.90 14.00 14.10
e 0.40
Hd 15.60 16.00 16.40
He 15.60 16.00 16.40
L 0.30 0.50 0.70
L1 1.00
θ
0 10
Page 34
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
34
Appendix A: Application Note
A.1 Using Crystal 25MHz or 20MHz
AX88196 To PHY
CLKO 25MHz
XTALIN XTALOUT
25MHz
Crystal
8pf 2Mohm 8pf
Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing,
please refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator 25MHz or 20MHz
AX88190A To PHY
CLKO 20MHz
XTALIN XTALOUT
NC
3.3V Power OSC 20MHz
A.3 Using 60MHz Oscillator/Crystal
AX88196 To PHY
CLKO 60MHz
/CLK_DIV3
Pull Low 20MHz
XTALIN XTALOUT
NC
3.3V Power OSC 60MHz
Devided
By 3
Page 35
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
35
A.4 Dual power (5V and 3.3V/3.0V) application
+5V +5V
+5V HVdd +5V
+3.3V LVdd
A.5 Single power (3.3V/3.0V) application
+3.3V +3.3V
+3.3V HVdd +3.3V
+3.3V LVdd
AX88196
PHY/TxRx
MAGNETIC
RJ45
+5V CPU I/F
Optional
EEPROM
AX88196
PHY/TxRx
MAGNETIC
RJ45
+3.3V CPU I/F
Optional
EEPROM
Page 36
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
36
A.6 Dual power (5V and 3.3V) application with 3.3V PHY
The 510 and 1K Ohm resisters are just for voltage adjustment
AX88196
PHY
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
510 ohm 1k ohm
Page 37
AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
37
Errata of AX88196 Version ED2
1. SNI (Serial Network Interface) has bug for HomePNA application.
Solution: Using MII interface for HomePNA solution. Refer to “Demonstration
Circuit” on page 37 to 41.
2. SPP command port readback value is from internal registers instead of
external pins
Solution: ASIX will not fix the problem at this moment. Care must be taken
when doing the external pins diagnostic.
3. DTACK can’t fit 68K CPU timing in 68K mode
Solution : Using the DTACK automatic insertion function in 68K CPU.
Page 38
AX88196 10/100BASE Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
38
Demonstration Circuit : AX88196 + Ethernet PHY + HomePNA 1M8 PHY
C5
0.1u
C8
0.1u
SD0
U1B
74HC04
3 4
SD10
RST1#
U1A
74HC04
1 2
5V
SD9
5V
3.3V
IOCS16#
SD5
5V
SA9
+
C6
47u/16v
C10
0.1u
+
C1
47u/16v
U1C
74HC04
5 6
196NS2A.SCH 1.1
ISA BUS
ASIX ELECTRONICS CORPORATION
A
1 5Thursday, September 21, 2000
Title
Size Document Number Rev
Date: Sheet of
+
C11
47u/16v
GND
IRQ7
SA2
C7
0.1u
SA7
RESET
SA6
U1E
74HC04
11 10
SA[0..9]
SA3
IRQ5
SD15
C2
0.1u
IRQ7
SD12
U2
LT1086
1
2
34
ADJ/GND
OUT
INOUT
+
C9
47u/16v
SD13
IOWR#
SD2
AX88196 L 10BASE-T/100BASE-TX & 1M HomePNA APPLICATION WITH DP83846 & DP83851 (FOR ISA MODE)(REFERENCE ONLY)
SD8
5V
3.3V
SA8
IORD#
VCC
IRQ
BHE#
5V
SA5
SA0
RST2#
GND
SD6
JP1
JUMP
1
3
5
7
9
2
4
6
8
10
C4
0.1u
RDY
SA4
+
C3
47u/16v
GND
SD3
U1F
74HC04
13 12
U1D
74HC04
9 8
GND
ISA1
ISA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D12
D13
D14
D15
D16
D17
D18
D10
IOCHK#
D<7>
D<6>
D<5>
D<4>
D<3>
D<2>
D<1>
D<0>
CHRDY
AEN
SA<19>
SA<18>
SA<17>
SA<16>
SA<15>
SA<14>
SA<13>
SA<12>
SA<11>
SA<10
SA<9>
SA<8>
SA<7>
SA<6>
SA<5>
SA<4>
SA<3>
SA<2>
SA<1>
SA<0>
SBHE#
LA<23>
LA<22>
LA<21>
LA<20>
LA<19>
LA<18>
LA<17>
MRDC#
MWTC#
D<8>
D<9>
D<10>
D<11>
D<12>
D<13>
D<14>
D<15>
GND
RESDRV
+5V
IRQ<9>
-5V
DRQ<2>
-12V
NOWS#
+12V
GND
SMWTC#
SMRDC
LOWC#
LORC#
DAK<3>#
DRQ<3>
DAK<1>#
DRQ<1>
REFRSH#
BCLK
IRQ<7>
IRQ<6>
IRQ<5>
IRQ<4>
IRQ<3>
DAK<2>#
T/C
BALE
+5V
OSC
GND
M16#
IO16#
IRQ<10>
IRQ<11>
IRQ<12>
IRQ<13>
IRQ<14>
DAK<0>#
DRQ<0>
DRQ<5>
DAK<6>#
DRQ<6>
DAK<7>#
DRQ<7>
+5V
MASTER16#
GND
DAK<5>#
AEN
RESET
IRQ3
SD7
5V
SA1
SD11
SD4
SD1
IRQ5
GND
5V
SD14
IRQ3
IRQ11
GND
SD[0..15]
JP1 is setting IRQ
RESET
IRQ11
IRQ12
IRQ12
Page 39
AX88196 10/100BASE Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
39
SD15
SD14
MDC
SD6
C26
0.1u
BHE#
0
SA6
+
C15
47u/16v
COL
CRS
R4 10K
AEN
SD13
3A0h
MC68K
SD5
0
0
C19
0.1u
C20
0.1u
8051
0
0
R3 10K
R5 10K
3.3V
R6 10K
TXD3
CPU0
XIN
SA[0..9]
IORD#
RXD1
SD12
RXD0
0
TXEN
ISA BUS
C23
0.1u
U4
93C56
1
2
3
4 5
6
7
8
CS
SK
DI
DO GND
NC
NC
VCC
C22
0.1u
0
C14
8p
SD11
5V
R1 20
IOBASE2
1
RXD2
1
XIN
C16
0.1u
IOBASE0
C24
0.1u
SD9
SD7
SA7
C25
0.1u
SA9
CPU0
0
0
SA3
5V
1
GND
SD4
SD3
25MHZ
option
SA5
IOCS16#
1
380h
SA1
SD0
J1
IO/BASE SELECT
1
3
5
2
4
6
SD2
EEDO
220h1
5V
360h
1
0
1
CPU TYPE & IO BASE SELECT
EECS
XOUT
C13
8p
1
1
1
196NS2A1.SCH 1.1
AX88195 MAC CONTROLL
ASIX ELECTRONICS CORPORATION
B
2 5Thursday, September 21, 2000
Title
Size Document Number Rev
Date: Sheet of
Y1
25MHZ-CRYSTAL
1
GND
0
1
RXD3
0
R7 10K
TXCK
0
GND
EEDO
IO BASE
CPU1
1
EEDI
GEP1
1
C12
0.1u
IOBASE0
MODE
80186
IRQ
RXCK
IOBASE1
RESET
RXER
MDIO
300h
EEDI
R2
2M
C27
0.1u
0
RXDV
SD10
R8 10K
320h
RDY
1
EESK
EECS
XOUT
IOBASE2
0
SA8
IOBASE1
GEP0
SA4
C17
0.1u
SD8
U3
AX88196
1
2
3
4
5
6
7
8
9
10
11
12
14
15
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
69
71
72
74
75
77
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
119
120
123
124
125
126
127
128
SA<0> /UDS
SA<1>
SA<2>
SA<3>
SA<4>
SA<5>
SA<6>
SA<7>
SA<8>
SA<9>
VSS
IRQ /IRQ
/IOWR R/W
/IORD
/BHE /LDS
HVDD
SD<15>
SD<14>
SD<13>
SD<12>
VSS
SD<11>
SD<10>
SD<9>
SD<8>
HVDD
SD<7>
SD<6>
SD<5>
SD<4>
VSS
SD<3>
SD<2>
SD<1>
SD<0>
VSS
/SLIN
/INIT
/ATFD
LVDD
/STRB
BUSY
/ACK
PE
VSS
SLCT
/ERR
PD7
PD6
LVDD
PD5
PD4
PD3
PD2
VSS
PD1 GEP1
PD0 GEP0
IO_BASE<2>
IO_BASE<1>
HVDD
IO_BASE<0>
VSS
CPU<1>
CPU<0>
/SLINK
HVDD
TEST
VSS
RX_ER
RX_DV
COL
CRS
RX_CLK
RXD<0>
RXD<1>
RXD<2>
RXD<3>
MDIO
MDC
VSS
TX_CLK
TX_EN
TXD<0>
TXD<1>
TXD<2>
TXD<3>
LVDD
CLKO25M
VSS
LCLK/XTALIN
XTALOUT
VSS
EECS
EECK
EEDI
EEDO
LVDD
SAL<0>
SAL<1>
SAL<2>
SAH<0>
SAH<1>
SAH<2>
VSS
/IOCS16
/CS
AEN/PSEN
RDY/DTACK
/RESET
RESET
LVDD
3.3V
0
C18
0.1u
340h
200h
EESK
TXD0
SA2
SA0
SD1
TXD1
+
C21
47u/16v
R9 10K
IOWR#
SD[0..15]
CPU1
TXD2
1
Page 40
AX88196 10/100BASE Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
40
RDP
3.3V
C29
10p
3.3V
U5
HR008
5
4
3
2
1
7
8
6
12
13
14
15
16
11
10
9
TD+
TD-
CT_TD
RD+
RD-
HRTRXP+
HRTRXN-
GND
TX+
TX-
NC2
RX+
RX-
NC1
RING
TIP
TDN
RING
R17
49.9
1%
R13
75
3.3V
C28
0.1u
GND
TDN
C31
10p
RDN
TIP
Transmit 1CT : 1CT
RX 1CT : 1CT
HomePNA 1CT : 1CT
R12
75
C32
0.01u/2KV
R15
49.9
1%
R16
49.9
1%
TDP
GND_CH
TDP
J2
RJ45N
1
2
3
6
4
5
7
8
U6
DUAL-RJ11-6P
1
2
3
4
5
6
7
8
9
10
11
12
NC
A1
TIP_A
RING_A
A2
NC
NC
B1
TIP_B
RING_B
B2
NC
C34
0.01u
C30
10p
R14
49.9
1%
C35
0.1u
C33
0.1u
RDN
R11
49.9
1%
R10
49.9
1%
GND_CH
196NS2A4.SCH 1.1
RJ45 & RJ11
ASIX ELECTRONICS CORPORATION
A
3 5Thursday, September 21, 2000
Title
Size Document Number Rev
Date: Sheet of
TIP
RDP
RING
Page 41
AX88196 10/100BASE Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
41
COLLED
TXD1
U7
DP83851B
36
35
34
33
32
31
23
24
25
26
27
28
37
38
21
22
45
46
19
29
39
5
11
20
7
8
4
17
18
16
15
44
14
42
43
48
30
40
41
47
3
6
10
1
2
9
12
13
TXD3
TXD2
TXD1
TXD0/TXD
TX_EN
TX_CLK
RXD3/PHYAD0
RXD2/CMDDIS#
RXD1/HI_POWER_EN#
RXD0/RXD/LOW_SPEED_EN#
RX_DV/GPSI_SEL#
RX_CLK
COL/MDIO_INT_EN#
CRS/PIN_INTRP_EN#
MDIO
MDC
X1
X2
IO_VDD1
IO_VDD2
CORE_VDD
ANA_VDD2
ANA_VDD3
IO_GND1
TIP
RING
RBIAS
LED_COL/PHYAD2
LED_ACT/PHYAD1
LED_SPEED/PHYAD3
LED_POWER/PHYAD4
RESET#
RESERVED
RESERVED
RESERVED
ANA_VDD1
IO_GND2
CORE_GND
CORE_SUB(0V)
ANA_GND1
ANA_GND2
ANA_GND3
ANA_GND4
SUB_GND1
SUB_GND2
SUB_GND3
RESERVED
RESERVED
TIP
L1 F.B.
RXDV
D1 LED
3.3V
Activity LED
R29
510
PWRLED
RXD2
MDIO
R18 20
RXDV
TXEN
C41
0.1u
R22
4.7K
C44
0.1u
C43
0.1u
COLLED
ACTLED
RXD1
R27
510
RING
COL
D3 LED
CRS
R21
9.31K
1%
TXD3
R20 4.7K
RXCK
TXD0
3.3V
Speed LED
TXD0
196NS2A2.SCH 1.1
DP83851B HomePNA PHYceiver
A4
4 5Thursday, September 21, 2000
ASIX ELECTRONICS CORPORATION
Title
Size Document Number Rev
Date: Sheet of
RXD3
TXCK
R23
4.7K
RXD0
RESET#
RXD3
TXEN
RST1#
3.3V
TXD2
Cillision LED
C39
0.1u
SPDLED
GND
RXD3
C37
0.1u
RING
+
C36
47uF/16V
COLLED
RXD2
ACTLED
RXD1
SPDLED
RXD0
R19 20
CRS
MDC
ACTLED
TXD1
R25
4.7K
C38
0.1u
25MHZ
PWRLED R26
4.7K
GND
TIP
3.3VA2
PCLK
C40
0.1u
TXD2
C42
0.1u
L2 F.B.
Set PHY address to 00000.
R24
4.7K
R28
510
D2 LED
COL
SPDLED
TXD3
MDIO
3.3V
3.3VA1
3.3V
MDC
Page 42
AX88196 10/100BASE Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
42
C47
0.1u
3.3V
MDC
RESET#
TXD2
C49
0.1u
R42 510
U8
DP83846A
59
58
55
54
52
51
38
39
40
41
44
45
60
61
36
37
67
66
57
65
12
14
64
3
7
23
73
2
9
13
15
18
19
76
79
50
46
16
17
11
10
1
5
8
20
21
22
47
63
68
69
70
71
74
75
77
78
80
6
48
34
42
53
56
4
24
49
72
43
35
62
33
32
31
30
29
28
27
26
25
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
COL
CRS/LED_CFG#
MDIO
MDC
X1
X2
IO_VDD
IO_VDD
ANA_VDD2
ANA_VDD3
IO_GND
RBIAS
ANA_VDD1
CORE_GND
CORE_GND
ANA_GND
ANA_GND
ANA_GND
ANA_GND
ANA_GND
SUB_GND
SUB_GND
SUB_GND
TX_ER
RX_ER/PAUSE_EN#
TD+
TD-
RD+
RD-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ANA_GND
CORE_GND
IO_GND
IO_GND
IO_GND
IO_GND
ANA_VDD
CORE_VDD
CORE_VDD
CORE_VDD
IO_VDD
IO_VDD
RESET#
LED_DPLX/PHY0
LED_COL/PHY1
LED_GDLNK/PHY2
LED_TX/PHY3
LED_RX/PHY4
LED_SPEED
AN_EN
AN_1
AN_0
FLED
PHYAD4
RLED
RXD1
3.3V
R35 4.7K
LLED
PCLK
C46
0.1u
RLED
RXD1
RXDV
RXD0
RXD3
C51
0.1u
RXDV
Transmit Activity : used R42.
Receive Activity : used R44.
Transmit/Receive Activity : D6 & D8 & R43.
TXEN
CRS
L4 F.B.
TDN
R40 510
TLED
D4
LED
R36 4.7K
TDP
PHYAD2
TXD1
D7
LED
FLED
TXEN
C54
0.1u
RLED
R43 510
TLED
TLED
CRS
L3 F.B.
D5
LED
+
C45
47uF/16V
R39 4.7K
R31 20
Set PHY ADDRESS TO 00011
R32 20
R37 4.7K
COL
RDN
C52
0.1u
CLED
LLED
COL
R38
9.31K
RST2#
25MHZ
Link LED
R33 4.7K
TXCK
MDC
RDN
RDP
RXD3
R34 4.7K
TXD0
3.3VA1
GND
RXCK
196NS2A3.SCH 1.1
DP83846A
A4
5 5Thursday, September 21, 2000
ASIX ELECTRONICS CORPORATION
Title
Size Document Number Rev
Date: Sheet of
RDP
PHYAD0
SLED
TXD3
GND
D8 1N4148
PHYAD3
3.3V
R44 510
C53
0.1u
TXD1
CLED
RXER
TXD3
3.3V
D6 1N4148
RXER
MDIO
TDN
MDIO
3.3VA2
GND
C48
0.1u
RXD2
TDP
R41 510
PHYAD1
TXD2
C50
0.1u
Activity LED
Speed LED
LLED
3.3V
RXD0
SLED
TXD0
3.3V
R30 20
RXD2
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