Datasheet AX88190P Datasheet (ASIX)

Features

DAA

MAGNETIC

EEPROM

SRAM

AX88190P

10/100BASE PCMCIA Fast Ethernet MAC Controller

Document No.: AX190-16 / V1.6 / May. 12 ’00

• IEEE 802.3u 100BASE-T, TX, and T4 Compatible

• Single chip PCMCIA bus 10/100Mbps Fast

Ethernet MAC Controller

• NE2000 register level compatible instruction

• Compliant with 16 bit PC Card Standard -

February 1995

• Support both 10Mbps and 100Mbps data rate

• Support both full-duplex or half-duplex operation

• Provides a MII port for both 10/100Mbps operation

• Support 256/512 bytes EEPROM (used for saving

CIS)

• Support automatic loading of Ethernet ID, CIS and

Adapter Configuration from EEPROM on power­on initialization

• External and internal loop-back capability

• 128-pin LQFP low profile package

• 25MHz Operation, Dual 5V and 3.3V CMOS

process with 5V I/O tolerance. Or pure 3.3V
operation

*IEEE is a registered trademark of the Institute of Electrical and Electronic

Engineers, Inc.

*All other trademarks and registered trademark are the property of their

respective holders.

Product description

The AX88190 Fast Ethernet Controller is a high performance PCMCIA bus Ethernet Controller. The AX88190
contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card Standard – February 1995. The
AX88190 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN
standard. The AX88190 supports 10Mbps/100Mbps media-independent interface (MII) to simplify the design. The
AX88190 is built in interface to connect FAX/MODEM chipset with parallel bus interface.

System Block Diagram

RJ45RJ11

PHY/TxRxMODEM

AX88190

PCMCIA I/F

This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

Always contact ASIX for possible updates before starting a design.

ASIX ELECTRONICS CORPORATION Frist Released Date : Oct/02/1998

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: [phone] FAX: [phone] http://www.asix.com.tw

AX88190 PCMCIA Fast Ethernet MAC Controller

CONTENTS

1.0 INTRODUCTION...............................................................................................................................................5

1.1 GENERAL DESCRIPTION: ..................................................................................................................................... 5

1.2 AX88190 BLOCK DIAGRAM:...............................................................................................................................5

1.3 AX88190 PIN CONNECTION DIAGRAM................................................................................................................6

2.0 SIGNAL DESCRIPTION.................................................................................................................................... 7

2.1 PCMCIA BUS INTERFACE SIGNALS GROUP .........................................................................................................7

2.2 EEPROM SIGNALS GROUP.................................................................................................................................8

2.3 MII INTERFACE SIGNALS GROUP ..........................................................................................................................8

2.4 MODEM INTERFACE PINS GROUP .......................................................................................................................... 9

2.5 SRAM INTERFACE PINS GROUP ........................................................................................................................... 9

2.6 MISCELLANEOUS PINS GROUP ............................................................................................................................ 10

2.7 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE.................................................................10

3.0 MEMORY AND I/O MAPPING .....................................................................................................................11

3.1 EEPROM MEMORY MAPPING ..........................................................................................................................11

3.2 ATTRIBUTE MEMORY MAPPING......................................................................................................................... 11

3.3 I/O MAPPING....................................................................................................................................................12

3.4 SRAM MEMORY MAPPING...............................................................................................................................12

4.0 REGISTERS OPERATION ..............................................................................................................................13

4.1 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF LAN............................................................................13

4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)...............................................14

4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)..........................................15

4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write).......................................15

4.2 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF MODEM.....................................................................16

4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write)....................................... 16

4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write).................................. 17

4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write)...............................17

4.3 REGISTERS OPERATION..................................................................................................................................... 18

4.3.1 Command Register (CR) Offset 00H (Read/Write) ....................................................................................20

4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)........................................................................... 20

4.3.3 Interrupt mask register (IMR) Offset 0FH (Write) ....................................................................................21

4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)...........................................................................21

4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write).....................................................................21

4.3.6 Transmit Status Register (TSR) Offset 04H (Read) ...................................................................................22

4.3.7 Receive Configuration (RCR) Offset 0CH (Write) ....................................................................................22

4.3.8 Receive Status Register (RSR) Offset 0CH (Read)....................................................................................22

4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)........................................................................................22

4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)..................................................................23

4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)..................................................................23

4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) ................................................. 23

4.3.13 Test Register (TR) Offset 15H (Write)..................................................................................................... 23

5.0 PCMCIA DEVICE ACCESS FUNCTIONS....................................................................................................24

5.1 ATTRIBUTE MEMORY ACCESS FUNCTION FUNCTIONS..........................................................................................24

5.2 I/O ACCESS FUNCTION FUNCTIONS..................................................................................................................... 24

6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................25

6.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................25

6.2 GENERAL OPERATION CONDITIONS ................................................................................................................... 25

6.3 DC CHARACTERISTICS...................................................................................................................................... 25

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AX88190 PCMCIA Fast Ethernet MAC Controller

6.4 A.C. TIMING CHARACTERISTICS........................................................................................................................26

6.4.1 XTAL / CLOCK......................................................................................................................................... 26

6.4.2 Reset Timing.............................................................................................................................................26

6.4.3 Attribute Memory Read Timing.................................................................................................................27

6.4.4 Attribute Memory Write Timing ................................................................................................................28

6.4.5 I/O Read Timing ....................................................................................................................................... 29

6.4.6 I/O Write Timing.......................................................................................................................................30

6.4.7 MII Timing................................................................................................................................................31

6.4.8 Asynchronous Memory I/F Access Timing .................................................................................................32

7.0 PACKAGE INFORMATION........................................................................................................................... 33

APPENDIX A: APPLICATION NOTE 1..............................................................................................................34

A.1 USING CRYSTAL ..............................................................................................................................................34

A.2 USING OSCILLATOR .........................................................................................................................................34

A.3 DUAL POWER (5V AND 3.3V) APPLICATION.......................................................................................................35

A.4 SINGLE POWER (3.3V) APPLICATION ................................................................................................................. 35

A.5 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY .............................................................................36

APPENDIX B: APPLICATION NOTE 2 ..............................................................................................................37

B.1 ADVANCE APPLICATION FOR USING CRYSTAL ...................................................................................................37

ERRATA OF AX88190 V1 .....................................................................................................................................38

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AX88190 PCMCIA Fast Ethernet MAC Controller

FIGURES

FIG - 1 AX88190 BLOCK DIAGRAM ..............................................................................................................................5

FIG - 2 AX88190 PIN CONNECTION DIAGRAM...............................................................................................................6

TABLES

TAB - 1 PCMCIA BUS INTERFACE SIGNALS GROUP ........................................................................................................7

TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP........................................................................................................8

TAB - 3 MII INTERFACE SIGNALS GROUP........................................................................................................................8

TAB - 4 MODEM INTERFACE SIGNALS GROUP..................................................................................................................9

TAB - 5 SRAM INTERFACE PINS GROUP.........................................................................................................................9

TAB - 6 MISCELLANEOUS PINS GROUP..........................................................................................................................10

TAB - 7 POWER ON CONFIGURATION SETUP TABLE ...................................................................................................... 10

TAB - 8 EEPROM MEMORY MAPPING........................................................................................................................ 11

TAB - 9 ATTRIBUTE MEMORY MAPPING......................................................................................................................11

TAB - 10 I/O ADDRESS MAPPING................................................................................................................................ 12

TAB - 11 LOCAL MEMORY MAPPING........................................................................................................................... 12

TAB - 12 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF LAN............................................................... 13

TAB - 13 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF MODEM........................................................16

TAB - 14 PAGE 0 OF MAC CORE REGISTERS MAPPING.................................................................................................18

TAB - 15 PAGE 1 OF MAC CORE REGISTERS MAPPING.................................................................................................19

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AX88190 PCMCIA Fast Ethernet MAC Controller

Registers

LOADER I/F

SD[15:0]

SA[9:0]

Ctl BUS

MII I/F

SMDIO

MEMD[15:0]

MEMA[15:1]

EEDO

1.0 Introduction

1.1 General Description:

The AX88190 provides industrial standard NE2000 registers level compatable instruction set. Various
drivers are easy acquired, maintenance and usage with no pain and tears

The AX88190 Fast Ethernet Controller is a high performance PCMCIA bus Ethernet Controller. The
AX88190 contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card Standard –
February 1995. The AX88190 implements both 10Mbps and 100Mbps Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard. The AX88190 supports 10Mbps/100Mbps media-independent
interface (MII) to simplify the design. The AX88190 is built in interface to connect FAX/MODEM chipset
with parallel bus interface.

AX88190A use 128-pin LQFP low profile package, 25MHz operation frequency, dual 5V and 3.3V CMOS
process with 5V I/O tolerance or pure 3.3V operation.

1.2 AX88190 Block Diagram:

EECS
EECK
EEDI

Fig - 1 AX88190 Block Diagram

MODEM

I/F

SEEPROM

NE2000

SRAM
Arbiter

Remote

DMA

FIFOs

PCMCIA Interface

SMDC

STA

MAC

Core

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AX88190 PCMCIA Fast Ethernet MAC Controller

SA[1]

HVDD

HVDD

SA[0]

SA[3]

SA[2]

SA[5]

SA[4]

SA[6]

SA[7]

SA[9]

SA[8]

IREQ#

IORD#

IOWR#

SD[15]

SD[14]

SD[13]

SD[12]

SD[11]

SD[10]

SD[9]

SD[8]

SD[6]

SD[5]

SD[7]

CE2#

CE1#

1.3 AX88190 Pin Connection Diagram

The AX88190 is housed in the 128-pin plastic light quad flat packFig - 2 AX88190 Pin Connection

Diagram shows the AX88190 pin assignment.

TX_EN

TXD[1]

TXD[2]

TXD[3]

LVDD

CLKO25M

VSS

LCLK/XTALIN

XTALOUT

VSS

EECS

EECK

EEDI
EEDO
LVDD

MDCS#

MINT

MAUDIO

PPWDN

MRIN#

MPWDN

MRESET#

MRDY

VSS

IOIS16#

STSCHG#

SPKR#

REG#

INPACK#

WAIT#

LVDD

RESET

LVDD

97
98

99
100
101

102

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

TXD[0]

TX_CLK

94

95

96

3

1

2

VSS

93

MDC

MDIO

RXD[3]

RXD[2]

RXD[1]

90

8892858983

RXD[0]

RX_CLK

CRS

86

87

COL

84

AX88190
PCMCIA
10/100BASE MAC
CONTROLLER

8

7

4

6

5

9

12

13

11

10

RX_DV

RX_ER

VSS

829181

16

15

14

MEMD[0]

MEMD[1]

MEMD[2]

MEMD[3]

78

77

797480

19

17

20

18

MEMD[4]

MEMD[5]

MEMD[6]

HVDD

75

73

76

24

21

23

22

MEMD[7]

MEMD[8]

MEMD[9]

VSS

71

72

70

69

26

25

28

27

MEMD[12]

MEMD[10]

MEMD[11]

MEMD[13]

66

65

68

67

32

31

29

30

64
63
62
61
60
59
58
57
56
55
54
53
52

51
50
49
48
47
46
45
44
43
42

41

40
39
38
37
36
35
34
33

HVDD
MEMD[14]
MEMD[15]
MEMA[1]
MEMA[2]

VSS
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
LVDD
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]

VSS

MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
LVDD

MEMA[15]
MEMRD#
MEMWR#
VSS
VSS
SD[0]
SD[1]
SD[2]
SD[3]
VSS
SD[4]

Fig - 2 AX88190 Pin Connection Diagram

VSS

WE#

6

OE#

VSS

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AX88190 PCMCIA Fast Ethernet MAC Controller

2.0 Signal Description

The following terms describe the AX88190 pin-out:
All pin names with the “#” suffix are asserted low.
The following abbreviations are used in following Tables.

I Input PU Pull Up

O Output PD Pull Down

I/O Input/Output P Power Pin

OD Open Drain

2.1 PCMCIA Bus Interface Signals Group

SIGNAL TYPE PIN NO. DESCRIPTION

SA[9:0] I 10 – 1 System Address : Signals SA[9:0] are address bus input lines which

enable direct address of up to 64K memory and I/O spaces on card.

SD[15:0] I/O 20 – 23,

25 – 38,

30 – 33,

35 – 38

IREQ# O 12 Interrupt Request : IREQ# is asserted to indicate the host system that

WAIT# O 125 Wait : This signal is set low to insert wait states during Remote DMA

REG# I 123 Attribute Memory and I/O Space Select : When the REG# signal is

IORD# I 15 I/O Read : The host asserts IORD# to read data from AX88190 I/O

IOWR# I 14 I/O Write : The host asserts IOWR# to write data into AX88190 I/O

OE# I 16 Output Enable : The OE# line is used to gate Memory Read data from

WE# I 13 Write Enable : The WE# signal is used for strobing Memory Write

IOIS16# O 120 I/O is 16 Bit Port : The IOIS16# is asserted when the address at the

INPACK# O 124 Input Port Acknowledge : The signal is asserted when the AX88190 is

CE1#-CE2# I 18, 17 Card Enable : The CE1# enables even numbered address bytes and

BVD1_STSCHG# O 121 Battery Voltage Detect 1 / Status Change
BVD2_SPKR# O 122 Battery Voltage Detect 2 / Audio speaker out

System Data Bus : Signals SD[15:0] constitute the bi-directional data
bus.

the PC Card device requires host software service.

transfer.

asserted, access is limited to Attribute Memory and to the I/O space.

space.

space.

memory on PC Card

data into the memory on PC Card.

socket corresponds to an I/O address to which the card responds, and
the I/O port addressed is capable of 16-bit access.

selected and can respond to and I/O read cycle at the address on the
address bus.

CE2# enables odd numbered address bytes

Tab - 1 PCMCIA bus interface signals group

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AX88190 PCMCIA Fast Ethernet MAC Controller

2.2 EEPROM Signals Group

SIGNAL TYPE PIN NO. DESCRIPTION

EECS O 106 EEPROM Chip Select : EEPROM chip select signal.
EECK O 107 EEPROM Clock : Signal connected to EEPROM clock pin.
EEDI O 108 EEPROM Data In : Signal connected to EEPROM data input pin.
EEDO I/PU 109 EEPROM Data Out : Signal connected to EEPROM data output pin.

Tab - 2 EEPROM bus interface signals group

2.3 MII interface signals group

SIGNAL TYPE PIN NO. DESCRIPTION

RXD[3:0] I 90 – 87 Receive Data : RXD[3:0] is driven by the PHY synchronously with

respect to RX_CLK.

CRS I 85 Carrier Sense : Asynchronous signal CRS is asserted by the PHY

when either the transmit or receive medium is non-idle.

RX_DV I 83 Receive Data Valid : RX_DV is driven by the PHY synchronously

with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].

RX_ER I 82 Receive Error : RX_ER ,is driven by PHY and synchronous to

RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.

RX_CLK I 86 Receive Clock : RX_CLK is a continuous clock that provides the

timing reference for the transfer of the RX_DV,RXD[3:0] and

RX_ER signals from the PHY to the MII port of the repeater.
COL I 84 Collision : this signal is driven by PHY when collision is detected.
TX_EN O 95 Transmit Enable : TX_EN is transition synchronously with respect to

the rising edge of TX_CLK. TX_EN indicates that the port is

presenting nibbles on TXD [3:0] for transmission.
TXD[3:0] O 99 – 96 Transmit Data : TXD[3:0] is transition synchronously with respect to

the rising edge of TX_CLK. For each TX_CLK period in which

TX_EN is asserted, TXD[3:0] are accepted for transmission by the

PHY.
TX_CLK I 94 Transmit Clock : TX_CLK is a continuous clock from PHY. It

provides the timing reference for the transfer of the TX_EN and

TXD[3:0] signals from the MII port to the PHY.
MDC O 92 Station Management Data Clock : The timing reference for MDIO.

All data transfers on MDIO are synchronized to the rising edge of this

clock. MDC is a 2.5MHz frequency clock output.
MDIO I/O/PU 91 Station Management Data Input / Output : Serial data input/output

transfers from/to the PHYs . The transfer protocol conforms to the

IEEE 802.3u MII specification.
Tab - 3 MII interface signals group

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AX88190 PCMCIA Fast Ethernet MAC Controller

2.4 Modem interface pins group

Signal Name Type Pin No. Description

MRDY I/PU 118 Modem Ready : MRDY low indicates that modem is initializing the

modem after reset signal asserted or the modem is at SLEEP/STOP

mode.
MRESET# O 117 Modem Reset :This signal asserts low to reset the modem chipset.
MDCS# O 111 Modem Chip Select : This signal connected to modem chip select pin.
MPWDN O 116 Modem Power Down : Rockwell modem chipset, this signal asserts

low to let modem chipset into power down mode. AT&T modem

chipset, this signal asserts high to let modem chipset into power down

mode.
MINT I/PD 112 Modem Interrupt : This signal driven by modem chipset to active

interrupt.
MRIN# I/PU 115 Ring Input :This signal is driven by DAA’s ring detect circuit. When

a telephone ringing signal is being received.
MAUDIO I/PD 113 Modem Audio : This signal is passed to PCMCIA interface via SPKR.

Tab - 4 Modem interface signals group

2.5 SRAM Interface pins group

SIGNAL TYPE PIN NO. DESCRIPTION

MEMA[15:1] O 43, 45 – 48,

50 –53’

55 – 58,

60 – 61

MEMD[15:0] I/O/PU 62 – 63,

65 – 68,
70 – 74,

76 – 80
MEMRD# O 42 SRAM Read
MEMWR# O 41 SRAM Write

Tab - 5 SRAM Interface pins group

SRAM Address :

SRAM Data :

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AX88190 PCMCIA Fast Ethernet MAC Controller

2.6 Miscellaneous pins group

SIGNAL TYPE PIN NO. DESCRIPTION

LCLK/XTALIN I 103 CMOS Local Clock : A 25Mhz clock, +/- 100 ppm, 40%-60% duty

cycle.
Crystal Oscillator Input : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT.

XTALOUT O 104 Crystal Oscillator Output : A 25Mhz crystal, +/- 25 ppm can be

connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should

be left floating.
CLKO25M O 101 Clock Output 25MHz : This clock is source from LCLK/XTALIN.
PPWDN O 114 Phy Power Down : This pin connects to PHY chip power down mode

control input.
RESET I/PD 127 Reset

Reset is active high then place AX88190 into reset mode immediately.

During Falling edge the AX88190 loads the EEPROM data.
LVDD P 44, 54,

100, 110,

126, 128

HVDD P 19, 29, 64,75Power Supply : +5V DC.

VSS P 11, 24, 34,

39, 40, 49,
59, 69, 81,

93, 102, 105,

119

Power Supply : +3.3V DC.

Note : for pure 3.3V single power solution, all the HVDD pin can

connect to +3.3V. Care should be taken that HVDD input power must

be greater or equal ( > = ) than LVDD.

Power Supply : +0V DC or Ground Power.

Tab - 6 Miscellaneous pins group

2.7 Power on configuration setup signals cross reference table

Signal Name Share with Description

EEPROM SIZE MEMD[6] EEPROM SIZE = 0 : Test mode.

EEPROM SIZE = 1 : Normal operation. (Default)

MPD_SET MEMD[5] MPD_SET = 0 : MPWDN pin active high.

MPD_SET = 1 : MPWDN pin active low.

PPD_SET MEMD[4] PPD_SET = 0 : PPWDN pin active high.

PPD_SET = 1 : PPWDN pin active low.

TEST MEMD[3] TEST = 0 : Test mode.

TEST = 1 : Normal operation. (Default)

All of the above signals are pull-up for default values.

Tab - 7 Power on Configuration Setup Table

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AX88190 PCMCIA Fast Ethernet MAC Controller

3.0 Memory and I/O Mapping

There are four memory or I/O mapping used in AX88190.

1. EEPROM Memory Mapping

2. Attribute Memory Mapping

3. I/O Mapping

4. Local Memory Mapping

3.1 EEPROM Memory Mapping

EEPROM OFFSET HIGH BYTE LOW BYTE

00H RESERVED WORD COUNT
01H CFH CFL
02H NODE-ID1 NODE ID 0
03H NODE ID 3 NODE ID 2
04H NODE ID 5 NODE ID 4
05H CHECKSUM RESERVED

06H – 10H RESERVED RESERVED

10H – FFH CIS CIS

Tab - 8 EEPROM Memory Mapping

3.2 Attribute Memory Mapping

ATTRIBUTE MEMORY

OFFSET

0000H
03BFH
03C0H LCOR
03C2H LCCSR
03C4H ­03C6H -

03CAH LIOBASE0
03CCH LIOBASE1
03CEH
03DFH

03E0H MCOR
03E2H MCCSR
03E4H ­03E6H -

03EAH MIOBASE0
03ECH MIOBASE1

03EEH
03FFH

CONTENTS

CIS

RESERVED

RESERVED

Tab - 9 Attribute Memory Mapping

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AX88190 PCMCIA Fast Ethernet MAC Controller

3.3 I/O Mapping

SYSTEM I/O OFFSET FUNCTION

0000H

001FH

Tab - 10 I/O Address Mapping

3.4 SRAM Memory Mapping

OFFSET FUNCTION

0000H
03BFH
03C0H LCOR *1
03C2H LCCSR *1
03C4H ­03C6H -

03CAH LIOBASE0 *1
03CCH LIOBASE1 *1
03CEH
03DFH

03E0H MCOR *1
03E2H MCCSR *1
03E4H ­03E6H -

03EAH MIOBASE0 *1
03ECH MIOBASE1 *1

03EEH
03FFH

0400H NODE ID 0

0401H NODE ID 1

0402H NODE ID 2

0403H NODE ID 3

0404H NODE ID 4

0405H NODE ID 5

0406H
07FFH

0800H
FFFFH

MAC CORE REGISTER

CIS *1

RESERVED

RESERVED

RESERVED

62K X 8

SRAM BUFFER

Tab - 11 Local Memory Mapping

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.0 Registers Operation

There are four register sets in AX88190 :

1. The PCMCIA function configuration registers of LAN.

2. The PCMCIA function configuration registers of MODEM.

3. The MAC core register.

4. The special registers.

4.1 PCMCIA Function Configuration Register Set of LAN

REGISTER NAME OFFSET

LCOR CONFIGURATION OPTION REGISTER 3C0H

LCSR CONFIGURATION AND STATUS REGISTER 3C2H
LIOBASE0 I/O BASED REGISTER 0 3CAH
LIOBASE1 I/O BASED REGISTER 1 3CCH

Tab - 12 PCMCIA Function Configuration Register Mapping of LAN

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)

FIELD R/W/C DESCRIPTION

7 R/W Software Reset

Assert this bit will reset the LAN function of AX88190. Return a 0 to this bit will leave the
LAN function of AX88190 in a post-reset state as same as that following a hardware reset.
The value of this bit is 0 at power-on.

6 R/W Level IRQ

This bit should be set to 1, the AX88190 always generates Level Mode Interrupt.

5:0 R/W Function Configuration Index

These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.

On multifunction PC Card,
Bit 5, Bit 4 : MODEM I/O base registers
Bit 5 Bit 4 MODEM I/O base
0 0 Decided by MIOBASE registers ( See section 4.2.3 )
0 1 2f8H
1 0 3e8H
1 1 2e8H
Bit 3 : Enable Power Down mode

If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will go into power down
mode. At power down mode AX88190 will disable MAC transmitting and receiving
operation. But the host interface will not be affected.

Bit 2 : Enable IREQ# Routing

If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will generate interrupt request
via IREQ# signal. If this bit is set to 0, the LAN will not generate interrupt request via
IREQ# line.

Bit 1 : Enable Base and Limit Registers

If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified by
the Base and Limit registers are passed to LAN function. If this bit is set to 0,all I/O
addresses are passed to LAN function.

Bit 0 : Enable Function

If this bit is set to 0, the LAN function is disabled.
If this bit is set to 1, the LAN function is enabled.

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)

FIELD R/W/C DESCRIPTION

7:3 - Reserved

2 R/W PPwrDwn : PHY power down setting

While this bit set to 1, PPWDN pin (pin 114) will be active to force PHY chip into power
down mode. As for PPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.

1 R Intr : Interrupt Request

The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.

0 R IntrAck : Interrupt Acknowledge

This bit will be 0. The Intr will reflect the status of interrupt requesting.

4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)

The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to
access the LAN specific registers (MAC Core Registers).

I/O Base Register 0

FIELD R/W/C DESCRIPTION

7:0 R/W Base I/O address bit 7 – 0.

I/O Base Register 1

FIELD R/W/C DESCRIPTION

7:0 R/W Base I/O address bit 15 – 8.

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.2 PCMCIA Function Configuration Register Set of MODEM

REGISTER NAME OFFSET

MCOR CONFIGURATION OPTION REGISTER 3E0H

MCSR CONFIGURATION AND STATUS REGISTER 3E2H
MIOBASE0 I/O BASED REGISTER 0 3EAH
MIOBASE1 I/O BASED REGISTER 1 3ECH

Tab - 13 PCMCIA Function Configuration Register Mapping of MODEM

4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write)

FIELD R/W/C DESCRIPTION

7 R/W Software Reset

Assert this bit will reset the MODEM function of AX88190. Return a 0 to this bit will
leave the MODEM function of AX88190 in a post-reset state as same as that following a
hardware reset. The value of this bit is 0 at power-on.

6 R/W Level IRQ

This bit should be set to 1, the AX88190 always generates Level Mode Interrupt.

5:0 R/W Function Configuration Index

These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.

On multifunction PC Card,
Bit 5, Bit4 : Reserved
Bit 3 : IREQ# route to STSCHG#

If bit 0 of MCOR is set to 0, this bit is ignored.
If both bit 0 and bit 2 of MCOR are set to 1 and this bit is set to 1, the MODEM will route
interrupt request to STSCHG# signal. If this bit is set to 0, the MODEM will generate
interrupt request via IREQ# line.

Bit 2 : Enable IREQ# Routing

If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1, the MODEM will generate interrupt
request via IREQ# signal. If this bit is set to 0, the MODEM will not generate interrupt
request via IREQ# line.

Bit 1 : Enable Base and Limit Registers

If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified
by the Base and Limit registers are passed to MODEM function. If this bit is set to 0,all
I/O addresses are passed to LAN function.

Bit 0 : Enable Function

If this bit is set to 0, the MODEM function is disabled.
If this bit is set to 1, the MODEM function is enabled.

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write)

FIELD R/W/C DESCRIPTION

7:3 - Reserved

2 R/W MPwrDwn : Modem power down setting

While this bit set to 1, MPWDN pin (pin 116) will be active to force modem chip into power
down mode. As for MPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.

1 R Intr : Interrupt Request

The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.

0 R IntrAck : Interrupt Acknowledge

This bit will be 0. The Intr will reflect the status of interrupt requesting.

4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH
(Read/Write)

The I/O Base registers (MIOBASE0 and MIOBASE1) determine the base address of the I/O range used to
access the MODEM specific registers.

I/O Base Register 0

FIELD R/W/C DESCRIPTION

7:0 R/W Base I/O address bit 7 – 0.

I/O Base Register 1

FIELD R/W/C DESCRIPTION

7:0 R/W Base I/O address bit 15 – 8.

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.3 Registers Operation

All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the
Command Register.

PAGE 0 (PS1=0,PS0=0)

OFFSET READ WRITE

00H Command Register

( CR )

01H Page Start Register

( PSTART )

02H Page Stop Register

( PSTOP )

03H Boundary Pointer

( BNRY )

04H Transmit Status Register

( TSR )

05H Number of Collisions Register

( NCR )

06H Current Page Register

( CPR )

07H Interrupt Status Register

( ISR )

08H Current Remote DMA Address 0

( CRDA0 )

09H Current Remote DMA Address 1

( CRDA1 )

0AH Reserved Remote Byte Count 0

0BH Reserved Remote Byte Count 1

0CH Receive Status Register

( RSR )

0DH Frame Alignment Errors

( CNTR0 )

0EH CRC Errors

( CNTR1 )

0FH Missed Packet Errors

( CNTR2 )
10H
11H
12H IFGS1 IFGS1
13H IFGS2 IFGS2
14H MII/EEPROM Access MII/EEPROM Access
15H - Test Register
16H Inter-frame Gap (IFG) Inter-frame Gap (IFG)
17H

to
1EH
1FH Reset Reserved

Data Port Data Port

Reserved Reserved

Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )

( RBCR0 )

( RBCR1 0
Receive Configuration Register
( RCR )
Transmit Configuration Register ( TCR )

Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )

Tab - 14 Page 0 of MAC Core Registers Mapping

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AX88190 PCMCIA Fast Ethernet MAC Controller

PAGE 1 (PS1=0,PS0=1)

OFFSET READ WRITE

00H Command Register

( CR )

01H Physical Address Register 0

( PARA0 )

02H Physical Address Register 1

( PARA1 )

03H Physical Address Register 2

( PARA2 )

04H Physical Address Register 3

( PARA3 )

05H Physical Address Register 4

( PARA4 )

06H Physical Address Register 5

( PARA5 )

07H Current Page Register

( CPR )

08H Multicast Address Register 0

( MAR0 )

09H Multicast Address Register 1

( MAR1 )

0AH Multicast Address Register 2

( MAR2 )

0BH Multicast Address Register 3

( MAR3 )

0CH Multicast Address Register 4

( MAR4 )

0DH Multicast Address Register 5

( MAR5 )

0EH Multicast Address Register 6

( MAR6 )

0FH Multicast Address Register 7

( MAR7 )
10H
11H
12H Inter-frame Gap Segment 1

13H Inter-frame Gap Segment 2

14H MII/EEPROM Access MII/EEPROM Access
15H - Test Register
16H Inter-frame Gap (IFG) Inter-frame Gap (IFG)
17H

to
1EH
1FH Reset Reserved

Data Port Data Port

IFGS1

IFGS2

Reserved Reserved

Command Register
( CR )
Physical Address Register 0
( PAR0 )
Physical Address Register 1
( PAR1 )
Physical Address Register 2
( PAR2 )
Physical Address Register 3
( PAR3 )
Physical Address Register 4
( PAR4 )
Physical Address Register 5
( PAR5 )

Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )

Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2

Tab - 15 Page 1 of MAC Core Registers Mapping

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.3.1 Command Register (CR) Offset 00H (Read/Write)

FIELD NAME DESCRIPTION

7:6 PS1,PS0 PS1,PS0 : Page Select

The two bit selects which register page is to be accessed.

PS1 PS0

0 0 page 0
0 1 page 1

5:3 RD2,RD1

,RD0

2 TXP TXP : Transmit Packet

1 START START :

0 STOP STOP : Stop AX88190

RD2,RD1,RD0 : Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88190 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address are not restored to the starting address if the
Remote DMA is aborted.

RD2 RD1 RD0
0 0 0 Not allowed
0 0 1 Remote Read
0 1 0 Remote Write
0 1 1 Not allowed
1 X X Abort / Complete Remote DMA

This bit could be set to initiate transmission of a packet

This bit is used to active AX88190 operation.

This bit is used to stop the AX88190 operation.

4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)

FIELD NAME DESCRIPTION

7 RST Reset Status :

Set when AX88190 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.

6 RDC Remote DMA Complete

Set when remote DMA operation has been completed

5 CNT Counter Overflow

Set when MSB of one or more of the Tally Counters has been set.
4 OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
3 TXE Transmit Error

Set when packet transmitted with one or more of the following errors

n Excessive collisions
n FIFO Under-run

2 RXE Receive Error

Indicates that a packet was received with one or more of the following errors

CRC error

Frame Alignment Error

FIFO Overrun

Missed Packet
1 PTX Packet Transmitted

Indicates packet transmitted with no error
0 PRX Packet Received

Indicates packet received with no error.

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.3.3 Interrupt mask register (IMR) Offset 0FH (Write)

FIELD NAME DESCRIPTION

7 - Reserved
6 RDCE DMA Complete Interrupt Enable. Default “low” disabled.
5 CNTE Counter Overflow Interrupt Enable. Default “low” disabled.
4 OVWE Overwrite Interrupt Enable. Default “low” disabled.
3 TXEE Transmit Error Interrupt Enable. Default “low” disabled.
2 RXEE Receive Error Interrupt Enable. Default “low” disabled.
1 PTXE Packet Transmitted Interrupt Enable. Default “low” disabled.
0 PRXE Packet Received Interrupt Enable. Default “low” disabled.

4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)

FIELD NAME DESCRIPTION

7 RDCR Remote DMA always completed

6:2 - Reserved

1 BOS Byte Order Select

0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80X86).

1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(68K)
0 WTS Word Transfer Select

0 : Selects byte-wide DMA transfers.

1 : Selects word-wide DMA transfers.

4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write)

FIELD NAME DESCRIPTION

7 FDU Full Duplex :

This bit indicates the current media mode is Full Duplex or not.

0 : Half duplex

1 : Full duplex
6 PD Pad Disable

0 : Pad will be added when packet length less than 60.

1 : Pad will not be added when packet length less than 60.
5 RLO Retry of late collision

0 : Don’t retransmit packet when late collision happens.

1 : Retransmit packet when late collision happens.

4:3 - Reserved
2:1 LB1,LB0 Encoded Loop-back Control

These encoded configuration bits set the type of loop-back that is to be performed.

LB1 LB0

Mode 0 0 0 Normal operation

Mode 1 0 1 Internal NIC loop-back

Mode 2 1 0 PHYcevisor loop-back
0 CRC Inhibit CRC

0 : CRC appended by transmitter.

1 : CRC inhibited by transmitter.

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.3.6 Transmit Status Register (TSR) Offset 04H (Read)

FIELD NAME DESCRIPTION

7 OWC Out of window collision

6:4 - Reserved

3 ABT Transmit Aborted

Indicates the AX88190 aborted transmission because of excessive collision.
2 COL Transmit Collided

Indicates that the transmission collided at least once with another station on the network.
1 - Reserved
0 PTX Packet Transmitted

Indicates transmission without error.

4.3.7 Receive Configuration (RCR) Offset 0CH (Write)

FIELD NAME DESCRIPTION

7 - Reserved
6

5 MON Monitor Mode

4 PRO PRO : Promiscuous Mode

3 AM AM : Accept Multicast

2 AB AB : Accept Broadcast

1 AR AR : Accept Runt

0 SEP SEP : Save Error Packet

INTT Interrupt Trigger Mode

Must be setting to “1”.

0 : Normal Operation

1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not

buffered into memory.

Enable the receiver to accept all packets with a physical address.

Enable the receiver to accept packets with a multicast address. That multicast address must

pass the hashing array.

Enable the receiver to accept broadcast packet.

Enable the receiver to accept runt packet.

Enable the receiver to accept and save packets with error.

4.3.8 Receive Status Register (RSR) Offset 0CH (Read)

FIELD NAME DESCRIPTION

7 - Reserved
6 DIS Receiver Disabled
5 PHY Multicast Address Received.
4 MPA Missed Packet
3 FO FIFO Overrun
2 FAE Frame alignment error.
1 CR CRC error.
0 PRX Packet Received Intact

4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)

FIELD NAME DESCRIPTION

7 - Reserved

6:0 IFG Inter-frame Gap. Default value 15H.

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AX88190 PCMCIA Fast Ethernet MAC Controller

4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)

FIELD NAME DESCRIPTION

7 - Reserved

6:0 IFG Inter-frame Gap Segment 1. Default value 0cH.

4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)

FIELD NAME DESCRIPTION

7 - Reserved

6:0 IFG Inter-frame Gap Segment 2. Default value 11H.

4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)

FIELD NAME DESCRIPTION

7 EECLK EECLK:

EEPROM Clock
6 EEO EEO : (Read only)

EEPROM Data Out value. That reflects Pin-109 EEDO value.
5 EEI EEI

EEPROM Data In. That output to Pin-108 EEDI as EEPROM data input value.
4 EECS EECS

EEPROM Chip Select
3 MDO MDO

MII Data Out
2 MDI MDI: (Read only)

MII Data In. That reflects Pin-91 MDIO value.
1 MDIR MII STA MDIO signal Direction

MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit

let MDIO as output signal.
0 MDC MDC

MII Clock

4.3.13 Test Register (TR) Offset 15H (Write)

FIELD NAME DESCRIPTION

7:5 - Reserved

4 TF16T Test for Collision
3 TPE Test pin Enable

2:0 IFG Select Test Pins Output

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AX88190 PCMCIA Fast Ethernet MAC Controller

5.0 PCMCIA Device Access Functions

The AX88190 , as a PCMCIA I/O device , needs support both Attribute Memory access function
and I/O access function. The Access methods are described as the following sections.

5.1 Attribute Memory access function functions.

Attribute Memory Read function

Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode X H H X X X High-Z High-Z
Byte Access (8 bits) L

L
Word Access (16 bits) L L L X L H Not Valid Even-Byte
Odd Byte Only Access L L H X L H Not Valid High-Z

Attribute Memory Write function

Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode X H H X X X X X
Byte Access (8 bits) L

L
Word Access (16 bits) L L L X H L X Even-Byte
Odd Byte Only Access L L H X H L X X

H
H

H
H

L
L

L
L

L
H

L
H

L
L

H
H

H
H

L
L

High-Z
High-Z

X
X

Even-Byte

Not Valid

Even-Byte

X

5.2 I/O access function functions.

I/O Read function

Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode X H H X X X High-Z High-Z
Byte Access (8 bits) L

L
Word Access (16 bits) L L L L L H Odd-Byte Even-Byte
I/O Inhibit H X X X L H High-Z High-Z
Odd Byte Only Access L L H X L H Odd-Byte High-Z

I/O Write function

Function Mode REG# CE2# CE1# SA0 IORD# IOWR# SD[15:8] SD[7:0]
Standby Mode X H H X X X X X
Byte Access (8 bits) L

L
Word Access (16 bits) L L L L H L Odd-Byte Even-Byte
I/O Inhibit H X X X H L X X
Odd Byte Only Access L L H X H L Odd-Byte X

H
H

H
H

L
L

L
L

L
H

L
H

L
L

H
H

H
H

L
L

High-Z
High-Z

X
X

Even-Byte

Odd-Byte

Even-Byte

Odd-Byte

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AX88190 PCMCIA Fast Ethernet MAC Controller

6.0 Electrical Specification and Timings

6.1 Absolute Maximum Ratings

Description SYM Min Max Units

Operating Temperature Ta 0 +85
Storage Temperature Ts -55 +150
Supply Voltage HVdd -0.3 +6 V
Supply Voltage LVdd -0.3 +4.6 V
Input Voltage HVin

LVin

Output Voltage HVout

LVin
Lead Temperature (soldering 10 seconds maximum) Tl -55 +220
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.

-0.3

-0.3

-0.3

-0.3

HVdd+0.5
LVdd+0.5
HVdd+0.5
LVdd+0.5

6.2 General Operation Conditions

Description SYM Min Tpy Max Units

Operating Temperature Ta 0 25 +75
Supply Voltage HVdd

LVdd

+4.75V

+2.70

+3.00

+5.00V
+3.00
+3.30

+5.25V
+3.30
+3.60

°C
°C

V
V
V
V

°C

°C

V
V
V

Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.

6.3 DC Characteristics

(Vdd=5.0V, Vss=0V, Ta=0°C to 75°C)

Description SYM Min Tpy Max Units

Low Input Voltage Vil - 0.8 V
High Input Voltage Vih 2 - V
Low Output Voltage Vol - 0.4 V
High Output Voltage Voh Vdd-0.4 - V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA

(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C)

Description SYM Min Tpy Max Units

Low Input Voltage Vil - 0.8 V
High Input Voltage Vih 1.9 - V
Low Output Voltage Vol - 0.4 V
High Output Voltage Voh Vdd-0.4 - V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA

Description SYM Min Tpy Max Units

Power Consumption (Dual power) DPt5v

DPt3v

Power Consumption (Single power 3.3V) SPt3v 48 mA

22
40

mA
mA

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AX88190 PCMCIA Fast Ethernet MAC Controller

6.4 A.C. Timing Characteristics

6.4.1 XTAL / CLOCK

Thigh

LCLK/XTALIN

Tr Tf Tlow

Tcyc

CLK25M Tod

Symbol Description Min Typ. Max Units

Tcyc CYCLE TIME
Thigh CLK HIGH TIME
Tlow CLK LOW TIME
Tr/Tf CLK SLEW RATE
Tod LCLK/XTALIN TO CLK25M OUT DELAY

16 20 24 ns
16 20 24 ns

1 - 4 ns

40 ns

10

6.4.2 Reset Timing

LCLK

RESET

Symbol Description Min Typ. Max Units

Trst Reset pulse width

100 - - LClk

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AX88190 PCMCIA Fast Ethernet MAC Controller

6.4.3 Attribute Memory Read Timing

TcR

Ta(A) Th(A)

A[9:0], REG#

Ta(CE) Tv(A)

CE#

Tsu(A) Ta(OE) Th(CE)

OE#

Tv(WT-OE) Tw(WT) Tdis(CE)

WAIT#

D[15:0] DATA Valid

Tsu(CE)

Ten(OE) Tv(WT) Tdis(OE)

Symbol Description Min Typ. Max Units

TcR READ CYCLE TIME
Ta(A) ADDRESS ACCESS TIME
Ta(CE) CARD ENABLE ACCESS TIME
Ta(OE) OUTPUT ENABLE ACCESS TIME
Tdis(OE) OUTPUT DISABLE TIME FROM OE#
Ten(OE) OUTPUT ENABLE TIME FROM OE#
Tv(A) DATA VALID FROM ADDRESS CHANGE
Tsu(A) ADDRESS SETUP TIME
Th(A) ADDRESS HOLD TIME
Tsu(CE) CARD ENABLE SETUP TIME
Th(CE) CARD ENABLE HOLD TIME
Tv(WT-OE) WAIT# VALID FROM OE#
Tw(WT) WAIT# PULSE WIDTH
Tv(WT) DATA SETUP FOR WAIT# RELEASED

300 - - ns

- - 120 ns

- - 100 ns

- - 100 ns

0.5 - - ns

- - 100 ns

0 - - ns
30 - - ns
20 - - ns

0 - - ns
20 - - ns

- - 10 ns

- - 200 ns

100 - - ns

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AX88190 PCMCIA Fast Ethernet MAC Controller

6.4.4 Attribute Memory Write Timing

TcW

A[9:0], REG#

Tsu(CE-WEH)

CE# Tsu(CE)

Tsu(A-WEH) Th(CE)

OE#

Tsu(A) Tw(WE) Trec(WE)

WE#

Tv(WT-WE) Tv(WT)

Tw(WT) Th(OE-WE)

WAIT#

Tsu(OE-WE) Tsu(D-WEH) Th(D)

D[15:0](Din) DATA Input Establish

Tdis(WE) Ten(OE)

D[15:0](Dout)

Tdis(OE) Ten(WE)

Symbol Description Min Typ. Max Units

TcW WRITE CYCLE TIME
Tw(WE) WRITE PULSE WIDTH
Tsu(A) ADDRESS SETUP TIME
Tsu(A-WEH) ADDRESS SETUP TIME FOR WE#
Tsu(CE-WEH) CARD ENABLE SETUP TIME FOR WE#
Tsu(D-WEH) DATA SETUP TIME FOR WE#
Th(D) DATA HOLD TIME
Trec(WE) WRITE RECOVER TIME
Tdis(WE) OUTPUT DISABLE TIME FROM WE#
Tdis(OE) OUTPUT DISABLE TIME FROM OE#
Ten(WE) OUTPUT ENABLE TIME FROM WE#
Ten(OE) OUTPUT ENABLE TIME FROM OE#
Tsu(OE-WE) OUTPUT ENABLE SETUP TIME FROM OE#
Th(OE-WE) OUTPUT ENABLE HOLD TIME FROM OE#
Tsu(CE) CARD ENABLE SETUP TIME
Th(CE) CARD ENABLE HOLD TIME
Tv(WT-WE) WAIT# VALID FROM WE#
Tw(WT) WAIT# PULSE WIDTH
Tv(WT) WE# HIGH FROM WAIT# RELEASED

250 - - ns
150 - - ns

30 - - ns

180 - - ns
180 - - ns

80 - - ns
30 - - ns
30 - - ns

- - 5 ns

- - 5 ns
5 - - ns
5 - - ns

10 - - ns
10 - - ns

0 - - ns

20 - - ns

- - 15 ns

- - 200 ns
0 - - ns

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AX88190 PCMCIA Fast Ethernet MAC Controller

6.4.5 I/O Read Timing

A[9:0]

REG#

TsuREG ThREG

TsuCE ThCE

CE#

Tw

IORD#

TsuA TdrINPACK

INPACK#

TdfINPACK TdrIOIS16

IOIS16#

TdfIOIS16 Td

Tdr(WT)

WAIT#

TdfWT Tw(WT) Th

D[15:0] DATA Valid

ThA

Symbol Description Min Typ. Max Units

Td DATA DELAY AFTER IORD#
Th DATA HOLD FOLLOWING IORD#
Tw IORD# WIDTH TIME
TsuA ADDRESS SETUP BEFORE IORD#
ThA ADDRESS HOLD BEFORE IORD#
TsuCE CE# SETUP BEFORE IORD#
ThCE CE# HOLD BEFORE IORD#
TsuREG REG# SETUP BEFORE IORD#
ThREG REG# HOLD BEFORE IORD#
TdfINPACK INPACK# DELAY FALLING FROM IORD#
TdrINPACK INPACK# DELAY RISING FROM IORD#
TdfIOIS16 IOIS16# DELAY FALLING FROM ADDRESS*
TdrIOIS16 IOIS16# DELAY RISING FROM ADDRESS*
TdfWT WAIT# DELAY FALLING FROM IORD#
Tdr(WT) DATA DELAY FROM WAIT# RISING
Tw(WT) WAIT# WIDTH TIME

- - 50 ns

0.5 - - ns

165 - - ns

70 - - ns
20 - - ns

5 - - ns

20 - - ns

5 - - ns
0 - - ns
0 - 10 ns

- - 10 ns

- - 10 ns

- - 0 ns

- - 5 ns

- - 0 us

- - 100 ns

* Note : The address includes REG# and CE1# signal

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AX88190 PCMCIA Fast Ethernet MAC Controller

6.4.6 I/O Write Timing

A[9:0]

REG#

TsuREG ThREG

TsuCE ThCE

CE#

Tw

IOWR#

TsuA TdrIOIS16

IOIS16#

TdfIOIS16

TdrIOWR

WAIT#

TdfWT Tw(WT) Th

D[15:0] DATA

ThA

Tsu

Symbol Description Min Typ. Max Units

Tsu DATA SETUP BEFORE IOWR#
Th DATA HOLD FOLLOWING IOWR#
Tw IOWR# WIDTH TIME
TsuA ADDRESS SETUP BEFORE IOWR#
ThA ADDRESS HOLD BEFORE IOWR#
TsuCE CE# SETUP BEFORE IOWR#
ThCE CE# HOLD BEFORE IOWR#
TsuREG REG# SETUP BEFORE IOWR#
ThREG REG# HOLD BEFORE IOWR#
TdfIOIS16 IOIS16# DELAY FALLING FROM ADDRESS*
TdrIOIS16 IOIS16# DELAY RISING FROM ADDRESS*
TdfWT WAIT# DELAY FALLING FROM IOWR#
Tw(WT) WAIT# WIDTH TIME
TdrIOWR IOWR# HIGH FROM WAIT# HIGH

60 - - ns
30 - - ns

165 - - ns

70 - - ns
20 - - ns

5 - - ns

20 - - ns

5 - - ns
0 - - ns

- - 10 ns

- - 0 ns

- - ** ns

- - ** ns
0 - - us

*Note : The address includes REG# and CE1# signal
** Note : There is no wait state while I/O Write operation

30

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

6.4.7 MII Timing

Ttclk Ttch Ttcl

TXCLK
Ttv Tth

TXD<3:0>

TXEN
Trclk Trch Trcl

RXCLK
Trs Trh

RXD<3:0>

RXDV
Trs1

RXER

Symbol Description Min Typ. Max Units

Ttclk Cycle time(100Mbps)
Ttclk Cycle time(10Mbps)

Ttch high time(100Mbps)

Ttch high time(10Mbps)
Trch low time(100Mbps)
Trch low time(10Mbps)

Ttv Clock to data valid

Tth Data output hold time
Trclk Cycle time(100Mbps)
Trclk Cycle time(10Mbps)

Trch high time(100Mbps)
Trch high time(10Mbps)

Trcl low time(100Mbps)
Trcl low time(10Mbps)

Trs data setup time

Trh data hold time

Trs1 RXER data setup time

- 40 - ns

- 400 - ns

14 - 26 ns

140 - 260 ns

14 - 26 ns

140 - 260 ns

- - 20 ns

5 - - ns

- 40 - ns

- 400 - ns

14 - 26 ns

140 - 260 ns

14 - 26 ns

140 - 260 ns

6 - - ns
10 - - ns
10 - - ns

31

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

6.4.8 Asynchronous Memory I/F Access Timing

MEMORY WRITE

Tsu(A) Th(A)

MEMA[15:1]

Tw(WR)

/MEMWR

Tw(RDdis)

/MEMRD

Tsu(D) Th(D)
Write Data
SD[15:0](Dout) DATA Valid

Td(WtoR)

Symbol Description Min Typ. Max Units

Tsu(A) ADDRESS SETUP TIME
Th(A) ADDRESS HOLD TIME
Tw(WR) WRITE PULSE WIDTH
Tw(RDdis) READ DISABLE PULSE WIDTH
Td(WtoR) WRITE TO READ DEALY
Tsu(D) DATA SETUP TIME
Th(D) DATA HOLD TIME

36 - - ns

0.3 - 1 ns
* - ns
* - ns

1 - 4.5 ns

16 - - ns

0.3 - 2 ns

MEMORY READ

Tsu(A) Th(A)

MEMA[15:1]

Referance Tw(RD)
Internal
“/MEMRD”

/MEMWR

/MEMRD

Read Data
MEMD[15:1] Valid DATA

( High Level )

( Low Level )

Tsu(RD) Th(RD)

Symbol Description Min Typ. Max Units

Tsu(A) ADDRESS SETUP TIME
Th(A) ADDRESS HOLD TIME
Tw(RD) READ PULSE WIDTH
Tsu(D) DATA SETUP TIME
Th(D) DATA HOLD TIME

30 - - ns

1.3 - 1 ns
* - ns

3 - - ns

0 - 2 ns
* NOTE : The pulse width can be seen as LCLK/XTALIN high time. See also 6.4.1 “Thigh” parameter.
NOTE : All most any brand asynchronous SRAM access time under 20 ns can fit into the specification.

32

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

7.0 Package Information

Hd

He

E

D

pin 1

b

e

A

A2 A1

L1

L

θ

MILIMETERSYMBOL

MIN. NOM MAX

A1 0.1
A2 1.3 1.4 1.5

A 1.7

b 0.155 0.16 0.26
D 13.90 14.00 14.10
E 13.90 14.00 14.10

e 0.40

Hd 15.60 16.00 16.40
He 15.60 16.00 16.40

L 0.30 0.50 0.70

L1 1.00

θ

0 10

33

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

Appendix A: Application Note 1

A.1 Using Crystal

AX88190 To PHY

CLKO25M

XTALIN XTALOUT

25MHz

Crystal

8pf 2Mohm 8pf

Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing,

please refer to the suggest circuit provided by crystal supplier.

A.2 Using Oscillator

XTALIN XTALOUT

3.3V Power OSC 25MHz

AX88190 To PHY

CLKO25M

NC

34

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

DAA

MAGNETIC

EEPROM

SRAM

DAA

MAGNETIC

EEPROM

SRAM

A.3 Dual power (5V and 3.3V) application

RJ45RJ11

+5V +5V

+5V HVdd +5V

+3.3V LVdd +5V

AX88190

A.4 Single power (3.3V) application

PHY/TxRxMODEM

+5V PCMCIA I/F

RJ45RJ11

+3.3V
(option for core logic)

+3.3V +3.3V

+3.3V HVdd +3.3V

+3.3V LVdd +3.3V

AX88190

PHY/TxRxMODEM

+3.3V PCMCIA I/F

35

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

AX88190

PHY

A.5 Dual power (5V and 3.3V) application with 3.3V PHY

The 510 and 1K Ohm resisters are just for voltage adjustment

RXD[3:0]

CRS

RX_DV

RX_ER

RX_CLK

COL

TX_EN

TXD[3:0]

TX_CLK

MDC

MDIO

RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO

510 ohm 1k ohm

36

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

Appendix B: Application Note 2

B.1 Advance Application for Using Crystal

Date: May 21, 1999

Condition: In short cable, AX88190 +AH 101 Phyceiver can’t link to BCM 5308

Switch.

Conclusion: 1. After measuring and verifying, we found it’s relevant to clock

source.

2. We ascertain the problem is caused by matching issues between

crystal and capacitor.

Solution: Change the value of capacitors beside crystal as below:

C22
18p

Y1

25MHZ
R4

2M

C23
18p

XIN XOUT

Note: The capacitors may be various depend on the specification of crystal.

While designing, please refer to the circuit provided by crystal supplier.

37

ASIX ELECTRONICS CORPORATION

AX88190 PCMCIA Fast Ethernet MAC Controller

Errata of AX88190 V1

1. OE# synchronous problem result in PC hang
Solution : Using hardware CKT to pre-sync OE# signal as below.

From AX88190
Pin 101

CLK25M

OE_# OE_M#

From PCMCIA
Connector
Pin 9

U2A

1
2

74F86

3

Jumper for future use

12
11

2
3

D
CLK

D
CLK

10

PR

13

4

PR

CL

1

U1B
74F74

9

Q

8

Q

CL

U1A
74F74

5

Q

Q

6

To AX88190
Pin 16

2. Interrupt Status can’t always clean up
Solution : Using software to do clean and check iteration until clean up.

Ex : IOBASE=300 ; Clear Tx/Rx interrupt.

Mov dx,307h

ClrISR :

Mov al,3 ; clear Tx/Rx interrupt
Out dx,al ; output to clear ISR
In al,dx ; read ISR
Test al,3 ; Check ISR cleared or not
Jz ClrISRDone ; Clear ok
Mov al,0 ; if not, clear again
Out dx,al
Jmp ClrISR

ClrISRDone: … ; clear successful

3. CE1# Bus decoder problem
Solution : Dis-connect AX88190 CE1# (pin 18) from PCMCIA connector CE1#

(pin 7). And connect AX88190 CE1# (pin 18) to logic “0” always
enable this signal.

38

ASIX ELECTRONICS CORPORATION

AX88190

ASIX

(AX88190 APPLICATION USED LUC6612)

U1

4.7u/16V

1

GND

2

D3

3

D4

4

D5

5

D6

6

D7

7

CE1#

8

A10

9

OE#

10

A11

11

A9

12

A8

13

A13

14

A14

15

WE#

16

IREQ#

17

VCC

18

VPP1

19

A16

20

A15

21

A12

22

A7

23

A6

24

A5

25

A4

26

A3

27

A2

28

A1

29

A0

30

D0

31

D1

32

D2

33

IOIS16#

34

GND

PCMCIA

U8

1

EECS VDD MA15
EESK LVDD
EEDI MA14
EEDO GND MA13

C29

+

0.01u

C28

CS

2

SK

3

DI
DO4GND

93C56R

XIN XOUT MA6 MD5

C22
8p

+

C1

4.7u/16V

GND GND SA0 LVDD MEMWR# MD12
SD3 GND SA1 RESET VDD MD11
SD4 SD11 SA2 LVDD MA15 GND
SD5 SD12 SA3 WAIT# MA13 MD10
SD6 SD13 SA4 INPACK# MA8 MD9
SD7 SD14 SA5 REG# MA7 MD8

OE# SA8 IOIS16# MA4 MA3
SA9 IOWR# GND

SA8 IREQ#

WE# IORD# MA12 GND
IREQ# OE_M# MA10 MD7
VDD VDD CE2# MA9 MD6

VDD

SA7 SD13 EESK MA13 MD2
SA6 SD12 EECS MA8 MD1
SA5 RESET GND GND MA7 MD0
SA4 WAIT# SD11 XOUT MA6 MA1
SA3 INPACK# SD10 XIN MA5 MA2
SA2 REG# SD9 GND MA4 MA3
SA1 SPKR# SD8
SA0 STSCHG# VDD LVDD
SD0 SD8 SD7
SD1 SD9 SD6
SD2 SD10 SD5
IOIS16# GND
GND GND SD4

GND

VDD LVDD

GND LVDD

Y1

25MHZ
R6

2M

STSCHG#

VCC

C4

0.01u

IOWR#

RESET

WAIT#

INPACK#

SPKR#

NC
NC

IORD#

REG#

35

GND

36

CD1#

37

D11

38

D12

39

D13

40

D14

41

SD15 SA6 SPKR# MA6 MA1

D15

42

CE2# SA7 STSCHG# MA5 MA2

CE2#

43

VS1#

44

IORD# SA9 GND

45
46

A17

47

A18

48

A19

49

A20

50

A21

51

VCC

52

VPP2

53

A22

54

A23

55

A24

56

A25

57

VS2#

58
59
60
61
62
63
64

D8

65

D9

66

D10

67

CD2#

68

GND

8
7
6
5

C23
8p

U9

4

TAB

2

VIN

1

VSS

XC62FP

PCMCIA Fast Ethernet MAC Controller

U2

VOUT

1

SA[0]

2

SA[1]

3

SA[2]

4

SA[3]

5

SA[4]

6

SA[5]

7

SA[6]

8

SA[7]

9

SA[8]

10

SA[9]

11

VSS

12

IREQ#

WE#
IOWR# MEMRD# MA11

VDD LVDD MEMWR# MD4

R4

SD15 EEDO VDD MD3
SD14 EEDI MA15 GND

0

GND
SD3
SD2 GND
SD1
SD0
GND
GND
MEMWR#
MEMRD# PCLK

MA12
MA11 GND
GND MD0
MA10 MD1
MA9 MD2
MA8 MD3
MA7 MD4
LVDD VDD

MA5 MD6
MA4 MD7 OE# OE_M#
MA3 MD8
GND MD9
MA2 GND
MA1 MD10
MD15 MD11
MD14 MD12
VDD MD13

3

+

C2

4.7u/16V

13

WE#

14

IOWR#

15

IORD#

16

OE#

17

CE2#

18

CE1#

19

HVDD

20

SD[15]

21

SD[14]

22

SD[13]

23

SD[12]

24

VSS

25

SD[11]

26

SD[10]

27

SD[9]

28

SD[8]

29

HVDD

30

SD[7]

31

SD[6]

32

SD[5]

33

SD[4]

34

VSS

35

SD[3]

36

SD[2]

37

SD[1]

38

SD[0]

39

VSS

40

VSS

41

MEMWR#

42

MEMRD#

43

MEMA[15]

44

LVDD

45

MEMA[14]

46

MEMA[13]

47

MEMA[12]

48

MEMA[11]

49

VSS

50

MEMA[10]

51

MEMA[9]

52

MEMA[8]

53

MEMA[7]

54

LVDD

55

MEMA[6]

56

MEMA[5]

57

MEMA[4]

58

MEMA[3]

59

VSS

60

MEMA[2]

61

MEMA[1]

62

MEMD[15]

63

MEMD[14]

64

HVDD

AX88190

VDD

+

C5

0.01uC60.1uC70.1uC80.1uC90.1u

C12

GND

C3

0.01u

4.7u/16V

+

C13

0.01u

C20

GND

4.7u/16V

RESET

WAIT#

INPACK#

SPKR#

STSCHG#

IOIS16#

MRDY

MRESET#

MPWDN

MRIN#

PPWDN

MAUDIO

MINT

MDCS#

EEDO

XTALOUT

LCLK/XTALIN

CLKO25M

TXD[3]
TXD[2]
TXD[1]

TXD[0]
TX_EN

TX_CLK

RXD[3]
RXD[2]
RXD[1]
RXD[0]

RX_CLK

RX_DV
RX_ER

MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]

MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]

MEMD[11]
MEMD[11]
MEMD[12]
MEMD[13]

128

LVDD

127
126

LVDD

125
124
123

REG#

122
121
120
119

VSS

118
117
116
115
114
113
112
111
110

LVDD

109
108

EEDI

107

EECK

106

EECS

105

VSS

104
103
102

VSS

101
100

LVDD

99
98
97

96
95
94
93

VSS

92

MDC

91

MDIO

90
89
88
87
86
85

CRS

84

COL

83
82
81

VSS

80
79
78
77
76
75

HVDD

74
73
72
71
70
69

VSS

68
67
66
65

C14

C15

0.1u

0.1u

RESET#

(OPTION FOR TEST)

R1

10K

R2
20

TXD3
TXD2
TXD1

TXD0
TXEN
TXCLK

MDC
MDIO
RXD3
RXD2
RXD1
RXD0
RXCLK
CRS
COL
RXDV
RXER

C10

0.1u

C16

C17

0.1u

C18

0.1u

0.1u

U4

MEMRD# MA11
MA12 GND
MA10 MD15
MA9 MD14
MA14 MD13

MA14 MD5

PCLK

C21
8p

U6A

1
2

C11

C24

C25

0.1u

0.1u

0.1u

C19

0.1u

3

74F86

C26

0.1u

ASIX ELECTRONICS CORPORATION

Title

Size Document Number Rev

Date: Sheet of

22

#OE

23

A11

24

A9

25

A8

26

A13

27

#WE

28

VCC

1

A14

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3

IS61C256AH

U5

22

#OE

23

A11

24

A9

25

A8

26

A13

27

#WE

28

VCC

1

A14

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3

IS61C256AH

2

D

3

CLK

12

D

11

CLK

C27

0.1u

B

|LINK
|190LU1A1.SCH

PCMCIA BUS & AX88190 & MEMORY

190LU1A.SCH 1.0

21

A10

20

#CE

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

I/O3

14

GND

13

I/O2

12

I/O1

11

I/O0

10

A0

9

A1

8

A2

21

A10

20

#CE

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

I/O3

14

GND

13

I/O2

12

I/O1

11

I/O0

10

A0

9

A1

8

A2

U7A

4

5

Q

PR

6

Q

CL

74F74

1

U7B

10

9

Q

PR

8

Q

CL

74F74

13

1 3Tuesday, December 15, 1998

ASIX ELECTRONICS CORPORATION

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: [phone] FAX: [phone] http://www.asix.com.tw

MDIO

AX88190 PCMCIA Fast Ethernet MAC Controller

U10

GND RDP

R10

4.7K

GND GND ALED ACLED

R7

24.9K

C30

1000p

R8 22.1K

VDDA GND
GND RDN

LLED VDDA
ALED
VDD GND PAD4 VDD
GND
TDP FLED
TDN SLED
GND FLED SLED
VDDA VDD

GND
VDDA LLED GND
GND
GND VDD

PAD4 GND
GND

VDDPLL FLED FDLED

PCLK

GND

MDC

RESET#

VDD
GND GND

TXEN

TXD3
TXD2

R18
220

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

VCCBG
ISET_100
GNDBG
LED_LINK/PHAD0
LED_ACT/PHAD1
VCCIOA
GNDIOA
TD+
TD­GNDT
VCCT
CLKREF
GNDBT
VCCBT
TEST0
TEST1

PHAD4
PCSEN#
TEST2
VCCPLL
LSCLK1
LSCLK2
GNDPLL
ISET_10
MDIO
MDC
RESET#
RX_EN
TX_ER/TXD4
TX_EN
TXD3
TXD2

LUC6612

LED_SPD/PHAD2

LED_FDX/PHAD3

GNDEQAP

VCCEQAP

VCCREC
GNDREC

BGREF0
BGREF1

VCCIOB
GNDIOB

MODE2
MODE1
MODE0

VCCDIGB

GNDDIGB

TX_CLK

RX_ER/RXD4

RX_DV

RX_CLK

GNDIOC

RXD0
RXD1
RXD2
RXD3

GNDDIGA

VCCDIGA

TXD0
TXD1

64
63

RD+

62

RD-

61
60
59
58
57
56
55
54
53
52
51
50
49

48
47
46
45
44
43

COL

42

CRS

41
40
39
38
37
36
35
34
33

R11 24.9k

R12

24.9K

GND ALED

C32

R23

RXER
RXDV

COL
CRS

RXD0
RXD1
RXD2
RXD3

VDD

TXD0
TXD1

33

R24

33

8p

TXCLK

RXCLK

C33
8p

BY PASS CAP WITH DIGITAL POWER SUPPLY

VDD

VDD

GND

GND

Set PHY ADDRESS TO 10000

R28 10K

PHYAD4

R29 10K

PHYAD3

R27 10K

PHYAD2

R26 10K

PHYAD1

R25 10K

PHYAD0

To PCMJ15 Connect

R30 510
R31 510

SLED SPLED

R32 510
R33 510

LLED LILED

C38

4.7u/16V

C39

+

0.01u

C40

C41

C42

C43

0.1u

0.1u

0.1u

C44

0.1u

0.1u

R17

R13

49.9

TDP
TDN GND

RDP
RDN

R15

49.9

220

R14

49.9

R16

49.9

C31

0.01u

C52

0.1u

U11

1

CT

2

TD+

3

TD-

5

RD+

6

RD-

7

CT

14ST9012P

C35

0.01u

C36

0.01u
C37

0.01u

14

CT

13

TX+

12

TX-

10

RX+

9

RX-

8

CT

R1975R2075R2175R22

C53

0.01u/2KV

CHASSIS

SPLED VDD VDDPLL
LILED

75

GND
ACLED
FDLED

J1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

PCMJ15

40

BY PASS CAP WITH ANALOG POWER SUPPLY

VDD VDDA

L1

FB

L2

FB

C45

4.7u/16V

+

C34

0.1u

C46

C47

C48

C49

C51

0.1u

0.1u

0.01u

0.1u

ASIX ELECTRONICS CO.

Title

LUCENT LUC6612 PHY

Size Document Number Rev

190LU1A1.SCH 1.0

B

Date: Sheet of

C50

0.1u

0.1u

ASIX ELECTRONICS CORPORATION

2 3Tuesday, December 15, 1998

AX88190 PCMCIA Fast Ethernet MAC Controller

CHASSIS

J3

1
2
3
4
5
6
7
8

9
10
11
12

CON12

C54

0.01

J2

1
2

3
6

4
5

7
8

RJ45N

D1 LED

D2 LED

D3 LED

D4 LED

SPLED

LILED

ACLED

FDLED

ASIX ELECTRONICS CORPORATION

Title

Size Document Number Rev

Date: Sheet of

41

RJ45 & LED

190LED.SCH 1.0

A

3 3Tuesday, December 15, 1998

ASIX ELECTRONICS CORPORATION