Datasheet AX88170L Datasheet (ASIX)

AX88170 L

10/100 Mbps Ethernet

MAGNETIC

RJ45

EEPROM

MAGNETIC

RJ11

Features

• Single chip USB to 10/100Mbps Fast Ethernet and

• Compliant with USB specification 1.0 and 1.1

• Full Speed USB Device with bus power capability

• USB Communication Class Spec 1.0 Compliant

• Support 4 endpoints on USB

• IEEE 802.3u 100BASE -T, TX, and T4 Compatible

• Embedded 5K*16 bit SRAM

• Support both full-duplex or half-duplex operation on

• Provides a MII port for both Ethernet and

• Supports suspended mode and remote wakeup

• Optional PHY power down mode for power saving

Product description

The AX88170 USB to Fast Ethernet/HomePNA Controller is a high performance and highly integrated Controller with
embedded 5K*16 bit SRAM. The AX88170 contains a USB interface to host CPU and compliant with USB Standard V 1.0 and
V 1.1. The interface between AX88170 and PC Host is compliant with USB Communication Class Specification 1.0. The
AX88170 could be used for both 10M/100Mbps Fast Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and
1M/10M HomePNA standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII) interface to
simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional MII/RMII
interface with PHY mode, combine with Ethernet repeater or switch IC can build a multiple ports USB-to-USB bridge
application.

System Block Diagram

This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

ASIX ELECTRONICS CORPORATION Frist Released Date : Sep/11/2000

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: [phone] FAX: [phone] http://www.asix.com.tw

USB to Fast Ethernet /HomePNA Controller

USB to Fast Ethernet /HomePNA Controller

1/10Mbps HomePNA Network Controller

Fast Ethernet

HomePNA PHY interface

(link_up or magic packet)

PHY/TxRx

AX88170

Always contact ASIX for possible updates before starting a design.

Document No.: AX170-12 / V1.2 / Apr. 11 ’01

• Provides optional MII/RMII interface with PHY

mode for multiple ports USB-to-USB bridge
application.

• Support 256/512 bytes serial EEPROM (used for

saving USB Descriptors)

• Support automatic loading of Ethernet ID, USB

Descriptors and Adapter Configuration from
EEPROM on power -on initialization

• External PHY loop-back diagnostic capability

• Small form factor 64-pin LQFP package

• 48MHz and 25MHz Operation, pure 3.3V operation

with I/O 5V tolerance

*IEEE is a registered trademark of the Institute of Electrical and

Electronic Engineers, Inc.

*All other trademarks and registered trademark are the property of

their respect ive holders.

1/10 Mbps
Home LAN PHY

USB I/F

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CONTENTS

1.0 INTRODUCTION...........................................................................................................................................................................4

1.1 G ENERAL DESCRIPTION:............................................................................................................................................................4

1.2 AX88170 BLOCK DIAGRAM: ...................................................................................................................................................... 4

1.3 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE ...........................................................................................5

1.4 AX88170 PIN CONNECTION DIAGRAM WITH RMII INTERFACE.........................................................................................6

2.0 SIGNAL DESCRIPTION...............................................................................................................................................................7

2.1 USB BUS INTERFACE SIGNALS G ROUP .................................................................................................................................... 7

2.2 EEPROM SIGNALS G ROUP ......................................................................................................................................................... 7

2.3A MII INTERFACE SIGNALS GR OUP (MAC MODE).................................................................................................................. 7

2.3B MII INTERFACE SIGNALS GR OUP (PHY MODE)..................................................................................................................... 8

2.4 RMII INTERFACE SIGNAL PINS (PHY MODE)..........................................................................................................................9

2.5 MISCELLANEOUS PINS GR OUP................................................................................................................................................... 9

3.0 EEPROM MEMORY M APPING...............................................................................................................................................11

4.0 USB COMMANDS.......................................................................................................................................................................12

4.1 USB STANDARD COMMANDS...................................................................................................................................................12

4.2 USB COMMUNICATION CLASS COMMANDS.........................................................................................................................13

4.3 USB V ENDOR COMMANDS.......................................................................................................................................................14

5.0 USB CONFIGURATION STRUCTURE ...................................................................................................................................16

5.1 USB CONFIGURATION..............................................................................................................................................................16

5.2 USB INTERFACE CLASS............................................................................................................................................................16

5.3 USB E NDPOINTS........................................................................................................................................................................16

6.0 ELECTRICAL SPECIFICATION AND TIMING S.................................................................................................................17

6.1 ABSOLUTE MAXIMUM RATINGS............................................................................................................................................17

6.2 G ENERAL OPERATION CONDITIONS......................................................................................................................................17

6.3 DC CHARACTERISTICS..............................................................................................................................................................17

6.4 A.C. TIMING CHARACTERISTICS.............................................................................................................................................18

6.4.1 25M_XIN............................................................................................................................................................................18

6.4.2 48M_XIN............................................................................................................................................................................18

6.4.3 Reset Timing......................................................................................................................................................................18

6.4.4 MII Timing of MAC mode................................................................................................................................................20

6.4.5 MII Timing of PHY mode.................................................................................................................................................21

6.4.6 RMII Interface Timing of PHY Mode.............................................................................................................................22

6.4.7 STATION MANAGEMENT TIMING..............................................................................................................................23

6.4.8 SERIAL EEPROM TIMING.............................................................................................................................................24

7.0 PACKAGE INFORMATION.......................................................................................................................................................25

APPENDIX A: SYSTEM APPLICATIONS....................................................................................................................................26

A.1 USB TO FAST ETHERNET CONVERTER................................................................................................................................26

A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION................................................................................27

A.3 USB-TO-USB OR USB-TO-ETHERNET BRIDGE THROUGH ETHERNET REPEATER CONTROLLER ............................ 28

A.4 USB-TO-USB OR USB-TO-ETHERNET BRIDGE THROUGH ETHERNET SWITCH CONTROLLER.................................28

DEMONSTRATION CIRCUIT A: AX88170 + ETHE RNET PHY.............................................................................................29

DEMONSTRATION CIRCUIT B: AX88170 + HOMEPNA 1M8 PHY....................................................................................31

DEMONSTRATION CIRCUIT C: 4 USB PORTS + 1 ETHERNET PORT BRIDGE AP.....................................................33

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FIGURES

FIG - 1 AX88170 BLOCK DIAGRAM.....................................................................................................................................................4

FIG - 2 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE .........................................................................................5

FIG - 3 AX88170 PIN CONNECTION DIAGRAM RMII INTERFACE..................................................................................................6

TABLES

TAB - 1 USB BUS INTERFACE SIGNALS GROUP ..................................................................................................................................7

TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP .........................................................................................................................7

TAB - 3 MII INTERFACE SIGNALS GR OUP (MAC MODE)................................................................................................................. 8

TAB - 4 MII INTERFACE SIGNALS GR OUP (PHY MODE) ................................................................................................................... 8

TAB - 5 RMII INTERFACE SIGNAL PINS (PHY MODE).......................................................................................................................9

TAB - 6 MISCELLANEOUS PINS GROUP .............................................................................................................................................10

TAB - 7 EEPROM MEMORY MAPPING.............................................................................................................................................11

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Loader I/F

D-/D+

RMII I/F

SMDIO

EEDO

1.0 Introduction

1.1 General Description:

The AX88170 USB to Fast Ethernet Controller is a high performance and highly integrated USB bus Ethernet Controller with
embedded 5K* 16 bit SRAM. The AX88170 contains a full speed USB interface to host CPU and compliant with USB
Communication Class Spec. 1.0. The AX88170 implements both 10Mbps and 100Mbps Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard. The AX88170 supports media -independent interface (MII) or RMII (Reduce MII)
interface to simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional
MII/RMII interface with PHY mode, combines with Ethernet repeater or switch IC can build a multiple ports USB-to-USB
bridge application.

AX88170 use s 64-pin LQFP low profile package, 48MHz operation for USB and 25MHz operation for Ethernet, CMOS
process with pure 3.3V operation and 5 Volt I/O tolerance.

1.2 AX88170 Block Diagram:

Fig – 1 AX88170 Block Diagram

EECS
EECK
EEDI

5K* 16
SRAM

SEEPROM

Memory Arbiter

USB to

Ethernet

Bridge

USB Core and Interface

SMDC

STA

MAC

Core

MII I/F
Or

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1.3 AX88170 Pin Connection Diagram with MII Interface

The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig – 2 AX88170 Pin Connection

Diagram.

VSS
VDD
48M_XOUT
48M_XIN
VSS
VDD

TEST0

TEST1
TEST2
TEST3

VDD
TEST_OUT

TEST4

LD_RDY

ACT/LINK

VSS

EEDO

48

49
50
51
52

53
54
55

56

57

58
59

60
61
62
63
64

1

D+

EECS

EEDI

EECK

46

47

VDD

45

/S_RMII

43

44

VSS

GPIO1

/HomeLink

40

41

42

VDD

/PHY_RST

GPIO0

37

38

39

ASIX

AX88170

(MII Interface)

2

D-

3

VDD

5

/RST

VSS

647

8

/S_FDPX

SPD_UP

S_EXT

9

10111213141516

VSS

VDD

MDC

/S_MAC

25M_XOUT

36

25M_CLKO

VSS

25M_XIN

33

34

35

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

COL

TX_CLK

CRS

MDIO

RX_DV
RX_ER

VDD
RXD3
RXD2
RXD1
RXD0
VSS
RX_CLK

VDD

TX_EN
TXD3
TXD2
TXD1
TXD0

VSS

Fig – 2 AX88170 Pin Connection Diagram with MII Interface

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1.4 AX88170 Pin Connection Diagram with RMII Interface

The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig – 3 AX88170 Pin Connection

Diagram RMII Interface.

VSS
VDD
48M_XOUT
48M_XIN
VSS

VDD

TEST0

TEST1
TEST2
TEST3

VDD

TEST_OUT
TEST4
LD_RDY

ACT/LINK

VSS

49
50
51
52

53
54
55
56

57

58
59

60
61
62

63
64

EEDO

48

(RMII Interface)

1

D+

D-

EEDI

EECK

46

47

2

3

VDD

EECS

VDD

VSS

45

44

/S_RMII

/HomeLink

42

43

/PHY_RST

GPIO1

39

40

41

GPIO0

38

ASIX

AX88170

647

8

5

/RST

VSS

SPD_UP

9

/S_MAC

/S_FDPX

S_EXT

10111213141516

VDD

VSS

25M_XOUT

VDD

37

MDC

VSS

25M_XIN

34

35

36

COL

CRS_DV

MDIO

25M_CLKO

33

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

REF_CLK

NC
NC

VDD
NC
NC
RXD1
RXD0
VSS
NC

VDD

TX_EN
NC
NC
TXD1
TXD0

VSS

Fig – 3 AX88170 Pin Connection Diagram RMII Interface

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Receive Data: RXD[3:0] is driven by the PHY synchronously with respect

Carrier Sense: Asynchronous signal CRS is asserted by the PHY when

ive Data Valid: RX_DV is driven by the PHY synchronously with

respect to RX_CLK. Asserted high when valid data is present on RXD

Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK, is

iods to indicate to the port that an

Receive Clock: RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from

Transmit Enable: TX_EN is transition synchronously with respect to the
rising edge of TX_CLK. TX_EN indicates that the port is presenting

2.0 Signal Description

The following terms describe the AX88170 pin-out:

All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.

I Input PU Pull Up

O Output PD Pull Down

I/O Input/Output P Power Pin

OD Open Drain

2.1 USB Bus I nterface Signals Group

SIGNAL TYPE PIN NO. DESCRIPTION

D+ I/O 1 USB Data Plus Pin
D- I/O 2 USB Data Minus Pin

Tab – 1 USB bus interface signals gr oup

2.2 EEPROM Signals Group

SIGNAL TYPE PIN NO. DESCRIPTION

EECS O 45 EEPROM Chip Select : EEPROM chip select signal.
EECK O 46 EEPROM Clock : Signal connected to EEPROM clock pin.
EEDI O 47 EEPROM Data In : Signal connected to EEPROM data input pin.
EEDO I/PU 48 EEPROM Data Out : Signal connected to EEPROM data output pin.

Tab – 2 EEPROM bus interface signals group

2.3a MII interface signals group (MAC mode)

When /S_RMII=1 and /S_MAC=0

SIGNAL TYPE PIN NO. DESCRIPTION

RXD[3:0]

CRS I/PD 15

RX_DV I/PD 32 Rece

RX_ER I/PD 31

RX_CLK I/PU 24

I/PU 29, 28

27, 26

to RX_CLK.

either the transmit or receive medium is non-idle.

[3:0].

asserted for one or more RX_CLK per
error has detected.

COL I/PD 13 Collision: this signal is driven by PHY when collision is detected.
TX_EN O 22

the PHY to the MII port of the MAC.

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Transmit Data: TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is

ock: TX_CLK is a continuous clock from PHY. It provides the

timing reference for the transfer of the TX_EN and TXD[3:0] signals from

Station Management Data Clock: The timing reference for MDIO. All data

are synchronized to the rising edge of this clock. MDC

Station Management Data Input/Output: Serial data input/output transfers
from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII

sformed from TXD[3:0] of MAC

Carrier Sense: Basically CRS is transformed from TX_EN of MAC mode of

Receive Data Valid: Basically RX_DV is transformed from TX_EN of MAC

Receive Clock: Basically RX_CLK is sourced from internal 25MHz local

when collision is

ly TX_EN is simulation from RX_DV of MAC

Transmit Data: Basically TXD[3:0] is simulation from RXD[3:0] of MAC

nal 25MHz local

SIGNAL TYPE PIN NO. DESCRIPTION

nibbles on TXD [3:0] for transmission.

TXD[3:0] O 21, 20

TX_CLK I 16 Transmit Cl

19, 18

asserted ,TXD[3:0] are accepted for transmission by the PHY.

MDC O 12

MDIO I/O/PU 14

Tab – 3 MII interface signals group (MAC mode)

the MII port to the PHY.

transfers on MDIO
is a 2.5MHz frequency clock output.

specification.

2.3b MII interface signals group (PHY mode)

When /S_RMII=1 and /S_MAC=1

SIGNAL TYPE PIN NO. DESCRIPTION

RXD[3:0]

CRS O 15

RX_DV O 32

RX_ER O 31 Receive Error: No used
RX_CLK O 24

COL O 13 Collision: this signal is generated by internal logic

TX_EN I/PD 22 Transmit Enable: Basical

TXD[3:0] I/PU 21, 20

TX_CLK O 16 Transmit Clock: Basically TX_CLK is sourced from inter

Tab – 4 MII interface signals group (PHY mode)

O 29, 28

27, 26

19, 18

Receive Data: Basically RXD[3:0] is tran
mode of MII interface.

MII interface.

mode of MII interface.

clock.

detected.

mode of MII interface.

mode of MII interface.

clock.

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transformed from TXD[1:0] of MAC

transformed of TX_EN

D[1:0] of MAC

Basically TX_EN is transformed from RX_DV from MAC

timing

60% duty

25 ppm can be

25 ppm can be

ternal

clock is connected to 25M_XIN, the crystal output pin should be left

60% duty

100 ppm can be

100 ppm can

ended external

the crystal output pin should be left

then place AX88170 into reset mode immediately.

selected or When S_EXT is set and

2.4 RMII interface signal pins (PHY mode)

When /S_RMII=0 and /S_MAC=1

SIGNAL TYPE PIN NO. DESCRIPTION

RXD[1:0]

CRS_DV O 15 Carrier Sense _ Data Valid : Basically CRS_DV is

TXD[1:0]

TX_EN

REF_CLK I 16 Reference clock : The input is a continue clock at 50Mhz for

Tab – 5 RMII interface signal pins (PHY mode)

O 27, 26 Receive Data : Basically RXD[1:0] is

I/PU

I/PD

19, 18 Transmit Data : Basically TXD[1:0] is transformed from RX

22 Transmit Enable :

mode of RMII interface.

from MAC mode of RMII interface.

mode of RMII interface.

mode of RMII interface.

reference with RMII interface.

2.5 Miscellaneous pins group

SIGNAL TYPE PIN NO. DESCRIPTION

25M_XIN I 35 CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40%-

cycle. ( See application note also )
Crystal Oscillator Input : Typical a 25Mhz crystal, +/­connected across 25M_XIN and 25M_XOUT.

25M_XOUT O 36 Crystal Oscillator Output : Typical a 25Mhz crystal, +/ -

48M_XIN I 52 48Mhz CMOS Clock In : Typical a 48Mhz clock, +/- 500 ppm, 40%-

48M_XOUT O 51 48Mhz Crystal Oscillator Output: Typical a 48Mhz crystal, +/-

25M_CLKO O 33 Clock Output : This clock is source from 25M_XIN.
/RST I/PD 4 Reset:

/S_RMII I/PU 43 Set to RMII mode:

/S_MAC I/PD 9 Set MII/RMII interface to MAC mode:

/S_FDPX I/PD 8 Set duplex mode when PHY mode is

S_EXT I/PD 7 Select where duplex mode is sourced from when MAC mode:

SPD_UP ID 6 The setting is enable speed up test mode:

connected across 25M_XIN and 25M_XOUT. If a single -ended ex

floating.

cycle. ( See application note also )
48Mhz Crystal Oscillator Input: Typical a 48Mhz crystal, +/­connected across 48M_XIN and 48M_XOUT.

be connected across 48M_XIN and 48M_XOUT. If a single­clock is connected to 48M_XIN,
floating.

Reset is active low
During Rising edge the AX88170 loads the EEPROM data.

0: RMII mode is selected.
1: MII mode is selected. (default)

0: MAC mode is selected. (default)
1: PHY mode is selected.

MAC mode is selected:
0: full-duplex mode is selected. (default)
1: half-duplex mode is selected.

0: duplex mode depands on internal register. (default)
1: duplex mode depands on external signal /S_FDPX

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LED indicator: When link fail, drives logic high always. When link OK, the

0: Normal operation mode.
1: Speed up test mode enable.

TEST0 I/PD 55 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.

TEST1 I/PD 56 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.

TEST2 I 57 Test Pin: This pin for test purpose only.

Pull down the pin for normal operation.

TEST3 I/PD 58 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.

TEST4 I/PD 61 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.
TEST_OUT O 60 Test Output Pin: This pin for test purpose only.
LDRDY O 62 Load EEPROM data completed indicator. Active high.
ACT/LINK O 63

/PHY_RST O 39 PHY Reset: This pin is used to reset PHY and is an active low signal.
GPIO0 B/PD 38 General Purpose I/O 0: Refer to section 4.3 USB Vendor Commands
GPIO1 B/PD 40 General Purpose I/O 1: Refer to section 4.3 USB Vendor Commands
/HOMELINK I/PU 41 Link Status: For external HomePHY link state input active low
VDD P 3, 10, 23, 30

37, 44, 50

54,59

VSS P 5, 11

17, 25, 34
42, 49, 53

64

pin drives logic low and will drives high a period when line has activity

(data transfer).

Power Supply: +3.3V DC.

Power Supply: +0V DC or Ground Power.

Tab - 6 Miscel laneous pins group

MII/RMII interface Cross Reference Table

MII RMII

RXD[0] RXD[0]
RXD[1] RXD[1]
RXD[2]
RXD[3]
CRS CRS_DV
RX_DV
RX_CLK
RX_ER
TX_EN TX_EN
TX_CLK REF_CLK (50MHz)
TXD[0] TXD[0]
TXD[1] TXD[1]
TXD[2]
TXD[3]
COL

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3.0 EEPROM Memory Mapping

EEPROM

OFFSET

00H RESERVED WORD COUNT FOR PRELOAD
01H *FLAG
02H LENGTH OF DEVICE DESCRIPTOR (BYTE) EEPROM OFFSET OF DEVICE

03H LENGTH OF CONFIGURAT ION DESCRIPTOR

04H NODE ID 1 NODE ID 0
05H NODE ID 3 NODE ID 2
06H NODE ID 5 NODE ID 4
07H LANGUAGE ID HIGH BYTE LANGUAGE ID LOW BYTE
08H LENGTH OF STRING INDEX 1 EEPROM OFFSET OF STRING INDEX 1
09H LENGTH OF STRING INDEX 2 EEPROM OFFSET OF STRING INDEX 2

0AH LENGTH OF STRING INDEX 3 EEPROM OFFSET OF STRING INDEX 3

0BH LENGTH OF STRING INDEX 4 EEPROM OFFSET OF STRING INDEX 4
0CH LENGTH OF STRING INDEX 5 EEPROM OFFSET OF STRING INDEX 5
0DH LENGTH OF STRING INDEX 6 EEPROM OFFSET OF STRING INDEX 6

0EH LENGTH OF STRING INDEX 7 EEPROM OFFSET OF STRING INDEX 7
0FH LENGTH OF STRING INDEX 8 EEPROM OFFSET OF STRING INDEX 8 (19H)
10H MAX PACKETSIZE HIGH BYTE MAX PACKET LOW BYTE
11H HOMEPNA PHY ID ETHERNET PHY ID
12H PAUSE PACKET HIGH WATER LEVEL PAUSE PACKET LOW WAT ER LEVEL

13H-18H RESERVED

19H 03H 0CH

1AH BYTE 2 OF UNICODE MAC ADDRESS **BYTE 1 OF UNICODE MAC ADDRESS

1BH BYTE 4 OF UNICODE MAC ADDRESS BYTE 3 OF UNICODE MAC ADDRESS
1CH BYTE 6 OF UNICODE MAC ADDRESS BYTE 5 OF UNICODE MAC ADDRESS
1DH BYTE 8 OF UNICODE MAC ADDRESS BYTE 7 OF UNICODE MAC ADDRESS

1EH BYTE 10 OF UNICODE MAC ADDRESS BYTE 9 OF UNICODE MAC ADDRESS

1FH BYTE 12 OF UNICODE MAC ADDRESS BYTE 11 OF UNICODE MAC ADDRESS
20H-4FH DEVICE /CONFIGURATION /INTERFACE /ENDPOINT DESCRIPTOR
50H-FFH STRINGS

HIGH BYTE LOW BYTE

DESCRIPTOR

EEPROM OFFSET OF CONFIGURATION

(BYTE)

DESCRIPTOR

Tab - 7 EEPROM Memory Mapping
Note:

*Flag: Bit 0 è Self Powered (for USB GetStatus) Bit 1 è Bus Powered (Reserved)
Bit 2 è Remote Wakeup (for USB GetStatus) Bit 3 è Interrupt Endpoint Enaable (Reserved)
Bit 4 è ClkNoStop (for Self Power only) Bit 5 è Reserved
Bit 6 è Reserved Bit 7 è Reserved
Bit 8 è Capture Effective Mode Bit 9 è Flow Control selector (1: software, o: read from PHY)
Bit A – F è Reserved

Bit 4 also effect LED display, if high then LED display USB active only otherwise display USB link and activity.
(In Self power mode Bit_4 set to high)

**Unicode MAC Address:
If the MAC’s NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, … NODE ID5 Then

the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC ADDRESS- BYTE
2 OF UNICODE MAC ADDRESS, … -BYTE 12 OF UNICODE MAC ADDRESS.

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4.0 USB Commands

There are three command groups for Endpoint 0 in AX88170:

l The USB standard commands
l USB Communication Class commands
l USB vendor commands.

4.1 USB standard commands

** The Language ID is 0x0904 for English
** PPLL means buffer length
** CC means configuration number
** I I means Interface number

SETUP COMMAND DATA IN/OUT DESCRIPTION

80 06 00 01 00 00 LL PP Data PPLL bytes Get Device Descriptor
80 06 00 02 00 00 LL PP Data PPLL bytes Get Configuration Descriptor
80 06 00 03 00 00 LL PP Data 2 bytes Get Supported Language ID
80 06 01 03 09 04 LL PP Data PPLL bytes Get Manufacture String
80 06 02 03 09 04 LL PP Data PPLL bytes Get Product String
80 06 03 03 09 04 LL PP Data PPLL bytes Get Serial Number String
80 06 04 03 09 04 LL PP Data PPLL bytes Get Configuration String
80 06 05 03 09 04 LL PP Data PPLL bytes Get Interface 0 String
80 06 06 03 09 04 LL PP Data PPLL bytes Get Interface 1/0 String
80 06 07 03 09 04 LL PP Data PPLL bytes Get Interface 1/1 Stirng
80 06 08 03 09 04 LL PP Data 12 bytes Get Ethernet Address String
80 08 00 00 00 00 01 00 Data 1 bytes Get Configuration
00 09 CC 00 00 00 00 00 No Data Set Configuration
81 0A 00 00 I I 00 01 00 Data 1 byte Get Interface
01 0B AS 00 01 00 00 00 No Data Set Interface

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1: All broadcast packet packets received by the networking device are forwarded

4.2 USB Communication Class Commands

** NN: number of multicast addresses
** BBAA: Ethernet Packet Filter
** TTSS: Number of Ethernet Statics

SETUP COMMAND DATA IN/OUT DESCRIPTION

21 40 NN 00 00 00 6*N 00 Data 6*N bytes Set Ethernet Multicast Filters
21 41 00 00 00 00 10 00 Data 16 bytes Set Ethernet Power Management Pattern
A1 42 00 00 00 00 02 00 Data 2 bytes Get Ethernet Power Management Pattern
21 43 AA BB 00 00 00 00 No Data Set Ethernet Packet Filter (AA BB)

Description of Ethernet Packet Filter (AA BB) Bitmap

BB = [D15:D8]
AA = [D7:D0]

Bit position DESCRIPTION

D15..D5 RESERVED (Reset to Zero)
D4 PACKET_TYPE_MULTICAST

1: All multicast packets enumerated in the device’s multicast address list are
forwarded up to the host.
0: Disabled.

D3 PACKET_TYPE_BROADCAST

D2 PACKET_TYPE_DIRECTED

D1 PACKET_TYPE_ALL_MULTICAST

D0 PACKET_TYPE_PROMISCUOUS

Tab - 9 Ethernet Packet Filter Bitmap

up to the host.
0: Disable.

1: Directed packets received containing a destination address equal to the MAC
address of the networking device are forwarded up to the host.
0: Always not set to Zero.

1 : ALL multicast frames received by the networking device are forwarded up to
the host, not just the ones enumerated in the device’s multicast address list.
0: Disabled.

1: ALL frames received by the networking device are forwarded up to the host.
0: Disabled.

ASIX ELECTRONICS CORPORATION 13

CONFIDENTIAL

AX88170 PRELIMINARY

4.3 USB Vendor Commands

SETUP COMMAND DATA IN/OUT DESCRIPTION

C0 02 XX YY 00 0M 02 00 Data 2 bytes Read Rx/Tx SRAM

M = 0 : Rx, M=1 : Tx
40 03 XX YY PP QQ 00 00 No Data Write Rx SRAM
40 04 XX YY PP QQ 00 00 No Data Write Tx SRAM
40 06 00 00 00 00 00 00 No Data Disable H/W MII Operation
C0 07 PI 00 RG 00 02 00 Data 2 Bytes Read MII Register
40 08 PI 00 RG 00 02 00 Data 2 Bytes Write MII Register
C0 09 00 00 00 00 01 00 Data 1 Bytes Read MII Operation Mode
40 0A 00 00 00 00 00 00 No Data Enable H/W MII Operation
C0 0B DR 00 00 00 02 00 Data 2 Bytes Read SROM
40 0C DR 00 MM SS 00 00 No Data Write SROM
40 0D 00 00 00 00 00 00 No Data Write SROM Enable
40 0E 00 00 00 00 00 00 No Data Write SROM Disable
C0 0F 00 00 00 00 02 00 Data 2 Bytes Read Rx Control Register
40 10 RR 00 00 00 00 00 No Data Write Rx Control Register
C0 11 00 00 00 00 03 00 Data 3 Bytes Read IPG/IPG1/IPG2 Register
40 12 II 00 00 00 00 00 No Data Write IPG Register
40 13 II 00 00 00 00 00 No Data Write IPG1 Register
40 14 II 00 00 00 00 00 No Data Write IPG2 Register
C0 15 00 00 00 00 08 00 Data 8 Bytes Read Multi-Filter Array
40 16 00 00 00 00 08 00 Data 8 Bytes Write Multi -Filter Array
C0 17 00 00 00 00 06 00 Data 6 Bytes Read Node ID
C0 19 00 00 00 00 02 00 Data 2 Bytes Read Ethernet/HomePNA PhyID
C0 1A 00 00 00 00 01 00 Data 1 Byte Read Medium Status(*)
40 1B MM 00 00 00 00 00 No Data Write Medium Mode(*)
C0 1C 00 00 00 00 01 00 Data 1 Byte Get Monitor Mode Status(**)
40 1D MM 00 00 00 00 00 No Data Set Monitor Mode On/Off(**)

Notes:

* Read / Write Medium status
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Read GPI1 X GPI0 X Home_Link 100MHz Full_Duplex Link
Write GPO1 GPO1EN GPO0 GPO0EN FRBI 100MHz Full_Duplex Link

** Read / Write Monitor Mode
Bit7-5 Bit4 Bit3 Bit2 Bit1 Bit0
Read Reserved

(Hardware_Version
for ASIX only)

Write X Flow_Contron_En X Magic_Packet_En Link_UP_Wake Monitor_Mode

Flow_Contron_En X Magic_Packet_En Link_UP_Wake Monitor_Mode

ASIX ELECTRONICS CORPORATION 14

CONFIDENTIAL

AX88170 PRELIMINARY

Interrupt Endpoint report link status format

Byte Number
Byte 0 A1 Fixed value
Byte 1 00 Fixed value
Byte 2 NN Bit_0 : Ethernet Link state, Bit_1 : Home PHY Link state (active high)
Byte 3 00 Fixed value
Byte 4 NN Bit_0 : 100MHz speed detect
Byte 5 NN Reserved (Hardware version for ASIX only)
Byte 6 NN Bit_0 : Full Duplex
Byte 7 00 Fixed value

ASIX ELECTRONICS CORPORATION 15

CONFIDENTIAL

AX88170 PRELIMINARY

5.0 USB Configuration Structure

5.1 USB Configuration.

The AX88170 supports 1 Configuration only.

5.2 USB Interface Class.

The AX88170 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface.

5.3 USB Endpoints.

The AX88170 supports 4 endpoints.

Endpoint 0 è Control endpoint, it is for configuring device.
Endpoint 1 è (optional) Interrupt endpoint, it is for reporting status change
Endpoint 2è Bulk Out endpoint, it is for Transmitting Ethernet Packet.
Endpoint 3 è Bulk In endpoint, it is for Receiving Ethernet Packet.

ASIX ELECTRONICS CORPORATION 16

CONFIDENTIAL

AX88170 PRELIMINARY

6.0 Electrical Specification and Timings

6.1 Absolute Maximum Ratings

Description SYM Min Max Units

Operating Temperature Ta 0 +85 °C
Storage Temperature Ts -55 +150 °C
Supply Voltage Vdd -0.3 +3.6 V
Input Voltage Vin -0.3 Vdd+0.3 V
Output Voltage Vout -0.3 Vdd+0.3 V
Lead Temperature (soldering 10 seconds maximum) Tl -55 +240 °C
Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to
Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.

6.2 General Operation Conditions

Description SYM Min Tpy Max Units

Operating Temper ature Ta 0 25 +70 °C
Supply Voltage Vdd +3.0 +3.30 +3.6 V

6.3 DC Characteristics

(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C)

Description SYM Min Tpy Max Units

Low Input Voltage Vil - 0.3*Vdd V
High Input Voltage Vih 0.7*Vdd - V
Low Output Voltage V ol - 0.4 V
High Output Voltage Voh 2.4 - V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -10 +10 uA
Input Pull-up / down resistance Ri 75 K ohm

Description SYM Min Tpy Max Units

Power Consumption (3.3V) SPt3v 40 mA

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CONFIDENTIAL

AX88170 PRELIMINARY

6.4 A.C. Timing Characteristics

6.4.1 25M_XIN

25M_XIN

Tr Tf Tlow

25M_CLKO Tod

Symbol Description Min Typ. Max Units

Tcyc CYCLE TIME 40 ns
Thigh CLK HIGH TIME 16 20 24 ns
Tlow CLK LOW TIME 16 20 24 ns
Tr/Tf CLK SLEW RATE 1 - 4 ns
Tod LCLK/XTALIN TO 25M_CLKO OUT DELAY 8 29 ns

6.4.2 48M_XIN

48M_XIN

Tr Tf Tlow

Symbol Description Min Typ. Max Units

Tcyc CYCLE TIME 20.83 ns
Thigh CLK HIGH TIME 8.3 10.42 12.5 ns
Tlow CLK LOW TIME 8.3 10.42 12.5 ns
Tr/Tf CLK SLEW RATE 1 - 4 ns

6.4.3 Reset Timing

25M_XIN

/RST

Symbol Description Min Typ. Max Units

Trst Reset pulse width 100 - - 25M

Thigh

Tcyc

Thigh

Tcyc

_XIN

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CONFIDENTIAL

AX88170 PRELIMINARY

ASIX ELECTRONICS CORPORATION 19

CONFIDENTIAL

AX88170 PRELIMINARY

6.4.4 MII Timing of MAC mode

Ttclk Ttch Ttcl

TXCLK(in)
Ttv Tth

TXD<3:0>(out)

TXEN(out)
Trclk Trch Trcl

RXCLK(in)
Trs Trh

RXD<3:0>(in)

RXDV(in)
Trs1

RXER(in)

CRS(in)

Symbol Description Min Typ. Max Units

Ttclk Cycle time(100Mbps) - 40 - ns
Ttclk Cycle time(10Mbps) - 400 - ns

Ttch high time(100Mbps) 14 - 26 ns
Ttch high time(10Mbps) 140 - 260 ns
Trch low time(100Mbps) 14 - 26 ns
Trch low time(10Mbps) 140 - 260 ns

Ttv Clock to data valid - - 20 ns

Tth Data output hold time 5 - - ns
Trclk Cycle time(100Mbps) - 40 - ns
Trclk Cycle time(10Mbps) - 400 - ns

Trch high time(100Mbps) 14 - 26 ns
Trch high time(10Mbps) 140 - 260 ns

Trcl low time(100Mbps) 14 - 26 ns
Trcl low time(10Mbps) 140 - 260 ns

Trs data setup time 6 - - ns

Trh data hold time 10 - - ns

Trs1 RXER data setup time 10 - - ns

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CONFIDENTIAL

AX88170 PRELIMINARY

6.4.5 MII Timing of PHY mode

Ttclk Ttch Ttcl

TXCLK(out)
Tts Tth

TXD<3:0>(in)

TXEN(in)
Trclk Trch Trcl

RXCLK(out)
Trs Trh

RXD<3:0>(out)

RXDV(out)
Tcrsh

CRS(out)

Symbol Description Min Typ. Max Units

Ttclk Cycle time(100Mbps) - 40 - ns
Ttclk Cycle time(10Mbps) - 400 - ns

Ttch high time(100Mbps) 14 - 26 ns
Ttch high time(10Mbps) 140 - 260 ns
Trch low time(100Mbps) 14 - 26 ns
Trch low time(10Mbps) 140 - 260 ns

Tts TXD, TXEN setup to TXCLK high 15 - - ns

Tth TXD, TXEN hold to TXCLK high 0 - - ns
Trclk Cycle time(100Mbps) - 40 - ns
Trclk Cycle time(10Mbps) - 400 - ns

Trch high time(100Mbps) 14 - 26 ns
Trch high time(10Mbps) 140 - 260 ns

Trcl low time(100Mbps) 14 - 26 ns
Trcl low time(10Mbps) 140 - 260 ns

Trv RXD, RXDV valid to RXCLK high 10 - - ns

Trh RXCLK high to RXD, RXDV invalid 10 - - ns

Tcrsh RXCLK high to CRS invalid 10 - - ns

ASIX ELECTRONICS CORPORATION 21

CONFIDENTIAL

AX88170 PRELIMINARY

6.4.6 RMII Interface Timing of PHY Mode

Tclk Tch Tcl

REF_CLK

Ts Th
TX_EN
(in)

TXD

(in)

CRS_DV
(out)
Tod Tod
RXD
(out)

Symbol Description Min Typ. Max Units

Tclk REF_CLK Clock Cycle Time 19.998 20 20.002 ns

Tch REF_CLK Clock High Time 7 10 13 ns

Tcl REF_CLK Clock Low Time 7 10 13 ns

Ts TXEN and TXD data setup to REF_CLK high 4 ns

Th TXEN and TXD data hold from REF_CLK high 2 ns

Tod REF_CLK rising edge to CRS_DV, RXD delay 4 ns

ASIX ELECTRONICS CORPORATION 22

CONFIDENTIAL

AX88170 PRELIMINARY

Tod

Tclk

Ts

6.4.7 STATION MANAGEMENT TIMING

MDC

Tch

Tcl

MDIO
(output)

Th

MDIO
(input)

Symbol Description Min Typ. Max Units

Tclk MDC Clock Cycle Time 2560 ns

Tch MDC Clock High Time 1280 ns

Tcl MDC Clock Low Time 1280 ns

Tod Clock Falling Edge to Output Valid Delay 2 9 ns

Ts Data In Setup Time 10 ns

Th Data In Hold Time 100 ns

ASIX ELECTRONICS CORPORATION 23

CONFIDENTIAL

AX88170 PRELIMINARY

Tch

Tclk

Tcl

6.4.8 SERIAL EEPROM TIMING

EECK

EEDI

Tdv

VALID

Tod

VALID

(output)

Tsc

Thcs

Tlcs

EECS

EEDO

Ts

DATA VALID

Th

(input)

Symbol Description Min Typ. Max Units

Tclk EECK Clock Cycle Time 5120 ns

Tch EECK Clock High Time 2500 9 ns

Tcl EECK Clock Low Time 2500 9 ns
Tdv EEDI Data Valid Output to EECK High Time 500 ns
Tod EECK High to EEDI Data Output Delay Time 500 ns

Tscs EECS Valid to EECK High Time 300 ns

Thcs EECK Low to EECS Invalid Time 0 ns

Tlcs Minimum EECS Low Time 2500 ns

Ts Data Input Setup Time 10 ns

Th Data Input Hold Time 100 ns

ASIX ELECTRONICS CORPORATION 24

CONFIDENTIAL

AX88170 PRELIMINARY

7.0 Package Information

Hd

He

E

D

pin 1

b

e

A

A2 A1

L1

L

θ

ASIX ELECTRONICS CORPORATION 25

CONFIDENTIAL

AX88170 PRELIMINARY

MAGNETIC

EEPROM

MILIMETER SYMBOL

MIN. NOM MAX

A1 0.05 0.1 0.15

A2 1.35 1.40 1.45

A 1.60

b 0.17 0.22 0.27

D 10.00

E 10.00

e 0.5

Hd 12.00

He 12.00

L 0.45 0.60 0.75

L1 1.00

θ

0° 3.5° 7°

Appendix A: System Applications

Some typical applications for AX88170 are illustrated bellow.

A.1 USB to Fast Ethernet Converter

RJ45

10/100 PHY/TxRx

AX88170

USB I/F

ASIX ELECTRONICS CORPORATION 26

CONFIDENTIAL

AX88170 PRELIMINARY

MAGNETIC

EEPROM

MAGNETIC

RJ11

A.2 USB to Fast Ethernet and/or HomeLAN Combo solution

RJ45

10/100 Mbps

Ethernet PHY/TxRx

AX88170

USB I/F

1/10 Mbps
Home LAN PHY

ASIX ELECTRONICS CORPORATION 27

CONFIDENTIAL

AX88170 PRELIMINARY

AX88170

AX88170

AX88170

AX88170

PC A

PC B

PC C

PC D

MII I/F

To Ethernet Backend

USB I/F

USB I/F

USB I/F

USB I/F

AX88170

AX88170

AX88170

AX88170

PC A

PC B

PC C

PC D

MII I/F

To Ethernet Backend

USB I/F

USB I/F

USB I/F

USB I/F

A.3 USB -to-USB or USB-to-Ethernet Bridge through Ethernet Repeater Controller

MII I/F MII I/F MII I/F MII I/F

Client

AX88875

Repeater Controller

Client

Client

Ethernet PHY for
Up-link

Client

Note : Using AX88871 for 8-port or less then 8-port solutions.

A.4 USB -to-USB or USB-to-Ethernet Bridge through Ethernet Switch Controller

MII I/F MII I/F MII I/F MII I/F

Client

AX88615

Switch Controller

Client

Client

Ethernet PHY for
Up-link

Client

ASIX ELECTRONICS CORPORATION 28

AX88170 USB to Fast Ethernet /HomePNA Controller

Demonstration Circuit A: AX88170 + Ethernet PHY

AX88710 L Application for
10BASE-T/100BASE-TX

J1 USB-CON

4

D-

4 3

3

D+

2

VDD5

1

GND

12

S S

C8

0.01u

L3

48M_XIN

VDD3

R5

1.5K
R6 18

R7 18

L2

FUSE

L4

F.B.

F.B.

+

C16
10u/16V

L1

2.2uH

C5
22p

C6
20P

U2

V6300C

5V

C19
1000P

D2

RESET#

1N4148

1

VCC

2
3

GND

VDD3

U4

3

VIN

AMS1117 - 3.3

R1 20K

Y1

48M

C1

8p

C7
20P

VDD3
RST#
GND

R9
10K

RST#

*2 RC reset (option)

C14

0.47u

2

VOUT

1

ADJ/GND

R3

48M_XOUT

0
C2
8p

*1 USB Port Link/Act LED

VDD3

R4 330

C9

C10

0.1u

0.1u

+

C15
10u/16V

C17

0.1u

D1 LED

R8 4.7K

C11

0.1u

VDD3

C18

0.01u

GND

C12

0.1u

VDD3

R2 1M

25M_XIN

48M_XOUT
48M_XIN

ACT/LINK#

RST#

D+
D-

VDD3
VDD3
VDD3
VDD3

VDD3

C13

0.1u

VDD3

GND

52
63

4

62

1
2

55
56
57
58
61
60

3
10
23
30
37
44
50
54
59

5
11
17
25
34
42
49
53
64

48M_XOUT
48M_XIN

ACT/LINK

/RST

LEERDY
D+
D-

TEST0
TEST1
TEST2
/EP78DIS TEST3
TEST4
TEST_OUT

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AX88170 L

/HOMELINK

U1

51

/PHY_RST

RX_CLK

TX_CLK

25M_CLKO

25M_XIN

25M_XOUT

/S_RMII
/S_MAC

/S_FDPX
SPD_UP

GPIO1

GPIO0

RX_DV
RX_ER

TX_EN

EEDO

EECK
EECS

S_EXT

RXD3
RXD2
RXD1
RXD0

MDIO

41
40

39

PRST#

38

RXDV

32
31

RXER

29

RXD3

28

RXD2

27

RXD1
RXD0

26
24

RXCLK
TXEN

22
21

TXD3

TXD3

20

TXD2

TXD2

TXD1

19

TXD1

18

TXD0

TXD0

16

TXCLK

15

CRS

CRS

13

COL

COL

14

MDIO

12

MDC

MDC

25MHZ

33

25M_XIN

35

25M_XOUT

36

EEDO

48

EEDI

47

EEDI

EECK

46

EECS

45
43

9
8
7
6

Y2

25M
C3
20P

EECS
EECK
EEDI
EEDO

25M_XOUT

C4
20P

PRST#

RXDV
RXER
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS
COL

MDIO
MDC

25MHZ

U3

1

CS

2

SK

3

DI

4 5

DO GND

93C56R

8

VDD3

VCC

7

NC

6

NC

ASIX ELECTRONIC CORPORATION

Title

AX88170

Size Document Number Rev

170AP1A.SCH 2.0

B

Date: Sheet of

1 2Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 29

AX88170 USB to Fast Ethernet /HomePNA Controller

Set PHY Address to 00010

RXDV
RXER
RXD3
RXD2
RXD1
RXD0

RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0

TXCLK

CRS

COL

MDIO
MDC

PRST#
25MHZ

C33

C32

0.1u

0.1u

：

U5

18

RXDV

19

RXER

20

RXD3

21

RXD2

22

RXD1

23

RXD0

24

RXCLK

27

TXEN

29

TXD3

30

TXD2

31

TXD1

32

TXD0

33

GND

R22 4.7K

VDD3

R25 2K

GND

VDD3

R30 4.7K
R31 4.7K

GND

VDD3
VDD3

VDD3
VDD3

VDD3

C35

C34

C36

0.1u

0.1u

0.1u D6 LED

TXCLK

28

TXER

34

CRS/PHY[3]

39

COL/PHY[4]

35

MDIO

45

MDC

47

XIN

48

XOUT

16

MDIOINTZ/PHY[2]

12

PHY[1]

10

PHY[0]

7

EQVDD1

13

VDD5

15

VDD1

25

VDD8

37

VDD4

38

VDD6

46

XTLVDD

3

GND9

6

EQGND1

14

GND1

26

GND8

36

GND4

LU3X31T-T64

LEDTX/ACTLED/BPSCR

TPTX+

TPRX+

TPRX-

AUTONEN

100FDEN

100HDEN

LEDSP/10FDEN

LEDFD/10HDEN

LNKLED/BPALIGN

LEDRX

LEDCOL/BP4B5B

REF100

REF10

TPTXTR

CSVDD
CSVDD

CSGND

TXVDD1
TXVDD2

TXGND1

RXVDD1
RXVDD2

RXGND1
RXGND2

TPTX-

RESVRSTZ
RESV

TDP

53

TDN

54

RDP

61

RDN

62

SPDLED
FULLED

LNKLED

ACTLED

GND
GND
GND

R12 4.7K
R13 4.7K
R14 4.7K
R15 4.7K
R23 4.7K

R24 4.7K

R26 4.7K
R27 301

R28 4.65K

C27

+

0.1u

C30

C31

0.1u

0.1u

C40

C39

0.1u

0.1u

C25

4.7u/16V

+

+

C28

4.7u/16V

C37

4.7u/16V

4
2
11
17
43

44
40
42
41

50
49
89
1
5

58
57

56

51
55

52

59
64

60
63

VDD3

R29 1

L5

F.B.

L6

F.B.

R10

49.9

R16

49.9

C23

0.01u

C26
1000P

C29
1000P

C38
1000P

R11

49.9

49.9

VDD3

VDD3

VDD3

R17

1
2
3

6
7
8 9

C20

0.01u

TX 1:1
RX 1:1

U6

1
2
3

6
7
8 9

TS6121A

FULLED

SPDLED

ACTLED

LNKLED

16

16

15

15

14

14

11

11

10

10

C21

0.01u

C24

0.01u

R32 510

R33 510

R34 510

R35 510

R18
75

C22

0.01u/2KV

TX+

TX­RX+
RX-

R19
75

D3LED

D4LED

D5 LED

R20
75

VDD3

R21
75

J2

SS

1
2
3
6

4
5
7
8

RJ45

FULL DUPLEX LED

SPEED LED

ACTIVITY LED

LINK LED

VDD3

GND

C41

+

4.7u/16V

VDD3

C42

0.1u

VDD3

GND

ASIX ELECTRONIC CORPORATION

Title

LU3X31

Size Document Number Rev

170AP1A1.SCH 2.0

B

Date: Sheet of

2 2Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 30

AX88170 USB to Fast Ethernet /HomePNA Controller

Demonstration Circuit B: AX88170 + HomePNA 1M8 PHY

AX88710 Application for 1M8 HomePNA

VDD3

J2 USB-CON

4 3

VDD5

GND

12

S S

C22

0.01u

4

D-

3

D+

2
1

R22

1.5K

F1

FUSE

L4

L5

F.B.

F.B.

+ C30

47u/16V

R24 18
R25 18

U4

V6300C

5V

C33

1000P

RESET#

D6

1N4148

VCC

GND

3

48M_XIN

C20
20P

1
2
3

VDD3

U6

VIN

AMS1117

R29
10K

RST#

C28

0.47u

C21
20P

VDD3
RST#
GND

ADJ/GND

L3

2.2uH

C19
22pF

VOUT

R18 20k

Y1

48M

C15

8p

*1 USB Port Link/Act LED

VDD3

C23

0.1u

C16
8p

R21 330

C24

0.1u

*2 RC reset (option)

2
1

+ C29

47u/16V

C31

0.1u

R20

0

R26 4.7K

C25

0.1u

VDD3

C32

0.01u

48M_XOUT

D5 LED

C26

0.1u

VDD3

GND

C27

0.1u

48M_XOUT
48M_XIN

ACT/LINK#

RST#

D+
D-

VDD3
VDD3
VDD3
VDD3

VDD3

VDD3

GND

U3

51

48M_XOUT

52

48M_XIN

63

ACT/LINK

4

/RST

62

LEERDY

1

D+

2

D-

55

TEST0

56

TEST1

57

TEST2

58

/EP78DIS TEST3

61

TEST4

60

TEST_OUT

3

VDD

10

VDD

23

VDD

30

VDD

37

VDD

44

VDD

50

VDD

54

VDD

59

VDD

5

VSS

11

VSS

17

VSS

25

VSS

34

VSS

42

VSS

49

VSS

53

VSS

64

VSS

AX88170 L

/PHY_PWN

PHY_PWN

/PHY_RST

PHY_RST

RX_DV
RX_ER

RXD3
RXD2
RXD1
RXD0

RX_CLK

TX_EN

TXD3
TXD2
TXD1
TXD0

TX_CLK

CRS

COL

MDIO

MDC

25M_CLKO

25M_XIN

25M_XOUT

EEDO

EEDI
EECK
EECS

/S_RMII
/S_MAC

/S_FDPX

S_EXT

SPD_UP

R19 1M

25M_XIN

41
40

39
38

32
31
29
28
27
26
24
22
21
20
19
18
16
15
13

14
12

33
35

36
48

47
46
45

43
9
8
7
6

PRST#

RXDV
RXD3

RXD2
RXD1
RXD0
RXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS
COL

MDIO
MDC

25MHZ
25M_XIN

25M_XOUT
EEDO

EEDI
EECK
EECS

Y2

25M
C17
20P

EECS
EECK

EEDI

EEDO

ASIX ELECTRONIC CORPORATION

Title

AX88170

Size Document Number Rev

170AP2A.SCH 2.0

B

Date: Sheet of

C18
20P

PRST#

RXDV
RXD3

RXD2
RXD1
RXD0
RXCLK

TXEN
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS
COL

MDIO
MDC

25MHZ

U5

1

CS

2

SK

3

DI

4 5

DO GND

93C56R

25M_XOUT

VDD3

VCC

NC
NC

R23

4.7K

R27

4.7K

8
7
6

ASIX ELECTRONICS CORPORATION 31

VDD3

VDD3

2 2Monday, February 26, 2001

R28

4.7K

VDD3

VDD3

VDD3

TXD0
TXD1
TXD2
TXD3
TXCLK
TXEN

RXD0
RXD1
RXD2
RXD3
RXCLK
RXDV
COL
CRS

25MHZ

PRST#

MDC

MDIO

VDD3
GND

AX88170 USB to Fast Ethernet /HomePNA Controller

Set PHY Address TO 00001 and LED DISPLAY C.K.T.

ACTLED#

COLLED#

SPEEDLED# R8 330

C5

+

47u/16V

C10

+

47u/16V

TXD0
TXD1
TXD2
TXD3
TXCLK
TXEN

RXD0
RXD1
RXD2
RXD3
RXCLK
RXDV
COL
CRS

25MHZ
PRST#

MDC
MDIO

VDD3
GND

C7

0.01u

C12

0.01u

C1

+

47u/16V

L1

F.B.

L2

F.B.

C2

0.01u

VDD3

VDD3

C6

+

47u/16V

C11

+

47u/16V

R2

4.7K

R9

4.7K

TXD3
TXD2

TXD1
TXD0
TXEN
TXCLK

RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK

COL
CRS

MDIO
MDC

25MHZ

C8

0.01u

C13

0.01u

C3

0.1u

R4

20

R7 20

C4

0.1u

AVDD3_1

C9

0.1u

AVDD3_2

C14

0.1u

VDD3

U1

36

TXD3

35

TXD2

34

TXD1

33

TXD0/TXD

32

TX_EN

31

TX_CLK

23

RXD3/PHYAD0

24

RXD2/CMDDIS#

25

RXD1/HI_POWER_EN#

26

RXD0/RXD/LOW_SPEED_EN#

27

RX_DV/GPSI_SEL#

28

RX_CLK

37

COL/MDIO_INT_EN#

38

CRS/PIN_INTRP_EN#

21

MDIO

22

MDC

45

X1

46

X2

19

IO_VDD1

29

IO_VDD2

39

CORE_VDD

48

ANA_VDD1

5

ANA_VDD2

11

ANA_VDD3

20

IO_GND1

30

IO_GND2

40

CORE_GND

41

CORE_SUB(0V)

47

ANA_GND1

3

ANA_GND2

6

ANA_GND3

10

ANA_GND4

1

SUB_GND1

2

SUB_GND2

9

SUB_GND3

DP83851C

RING

RBIAS

LED_COL/PHYAD2
LED_ACT/PHYAD1

LED_SPEED/PHYAD3

LED_POWER/PHYAD4

RESET#

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

7

TIP

TIP

8

RING

4

R12

9.31K

1%

17

COLLED#
ACTLED#

18
16

SPEEDLED#
POWERLED#

15
44

PRST#

12
13
14

R16

42
43

4.7K

POWERLED#

TIP
RING

R1 330

R3 10K

R5 330

R6 10K

R10 10K

R11 330

R13 10K

VDD3

R14

R15

49.9

49.9

R17
0

：

D1

GREEN LED

D2

YELLOW LED

D3

YELLOW LED

D4

RED LED

U2

1

+

2

-

3

GND

4

NC

5

NC

6

NC

7

NC

8

NC

HR002

RING

16

NC

15

NC

14

NC

13

NC

12

NC

11

NC

10

TIP

9

J1

1

NC

2

A1

3

TIP

4

RING

5

A2

6

NC

RJ11

Title

HOMENET PHY C.K.T.

Size Document Number Rev

170AP2A1.SCH 2.0

B

Date: Sheet of

1 2Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 32

AX88170 USB to Fast Ethernet /HomePNA Controller

Demonstration Circuit C: 4 US B Ports + 1 Ethernet Port Bridge AP

AX88170 L PHY mode application (MII Interface)

JP1

+5V

1
2
3

POWER CONNECTOR

(POWER IN: 5V/3A)

4

+

200u/16V

C1

C4

0.1u

C5
1000p

F.B.

F.B.

C6

0.1u

VDD5

C7
1000p

VDD5

GND5

L1

+

C2

L2

200u/16V

VDD5

GND

C8

+

47u/16V

C11

0.1u

U1

3

VIN

AMS1084-3.3V

VOUT

ADJ/GND

2
1

C3

+

47u/16V

VDD5

C9

0.1u

C10

0.01u

VDD3

GND

VDD3

C12

0.1u

L3

F.B.

C13
1000p

U5

OSC 25MHZ

OUT

GNDVCC

U2A

1 2

74LV04

25MHZ

R4 51

U6A

1 2

74F04

5
48

U2B

3 4

74LV04
U2C

5 6

74LV04
U2D

9 8

74LV04
U2E

11 10

74LV04

R7 20

U6B

3 4

74F04

U6C

5 6

74F04

R10 20

U3

V6300F

VCC

RESET#

GND

20

20

25M_USB0

25M_USB1

25M_USB2

25M_USB3

*1 R7 & R8 : Adjust ax88875AP
LCLK to AX88170 L TXCLK

25M_REP

25M_PHY

*2 R9 & R10 : Adjust DM9191F
LCLK to AX88875AP LCLK

R2 20 U4B

R3 20

R5 20

R6 20

R8

R9

VDD5

1
2
3

GND

U4A

1 2

74HC04

3 4

74HC04

U4C

5 6

74HC04

VDD5
VDD3
GND
25M_USB0
25M_USB1
25M_USB2
25M_USB3
25M_REP
25M_PHY
RST_EN#
RST_USB#

Title

POWER & RESET C.K.T.

Size Document Number Rev

170AP5A.SCH 2.0

B

Date: Sheet of

R1
10K

VDD5
VDD3
GND
25M_USB0
25M_USB1
25M_USB2
25M_USB3
25M_REP
25M_PHY
RST_EN#
RST_USB#

RST_EN#

RST_USB#

1 7Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 33

AX88170 USB to Fast Ethernet /HomePNA Controller

VDD3

GND

VDD3

VDD3

GND

J1 USB-CON

4 3

VDD5

12

GND

S S

C16

0.01u

D-

D+

4
3
2
1

48M_XIN

VDD3

Q1

2SC2412K

L4 F.B.

L5

2.2uH

C24
22pF

R13

1.5K

R14 18
R15 18

R17 20k

Y1

48M

C22

8p

R11

1K

C23
8p

R20

C14
20P

0

C15
20P

48M_XOUT

*3 USB Port Link/Act LED

VDD3

R12 330

C18

C17

0.1u

0.1u

D1 LED

RST_USB#

R16 4.7K

C19

C20

0.1u

0.1u

C21

0.1u

48M_XOUT
48M_XIN

ACT/LINK#

RST#

ALDONE
D+
D-

VDD3
VDD3
VDD3
VDD3

VDD3

U7

51

48M_XOUT

52

48M_XIN

63

ACT/LINK

4

/RST

62

LEERDY

1

D+

2

D-

55

TEST0

56

TEST1

57

TEST2

58

/EP78DIS TEST3

61

TEST4

60

TEST_OUT

3

VDD

10

VDD

23

VDD

30

VDD

37

VDD

44

VDD

50

VDD

54

VDD

59

VDD

5

VSS

11

VSS

17

VSS

25

VSS

34

VSS

42

VSS

49

VSS

53

VSS

64

VSS

AX88170 L

/HOMELINK

GPIO1

/PHY_RST

GPIO0

RX_DV
RX_ER

RXD3
RXD2
RXD1
RXD0

RX_CLK

TX_EN

TXD3
TXD2
TXD1
TXD0

TX_CLK

CRS

COL

MDIO

MDC

25M_CLKO

25M_XIN

25M_XOUT

EEDO

EEDI
EECK
EECS

/S_RMII
/S_MAC

/S_FDPX

S_EXT

SPD_UP

41
40

39
38

32

RXDV

31
29

RXD3

RXD2

28

RXD1

27
26

RXD0

24

RXCLK

TXEN

22
21

TXD3

20

TXD2

TXD1

19

TXD0

18
16
15

CRS

13
14

12
33
35

36

EEDO

48

EEDI

47

EECK

46

EECS

45
43

9
8
7
6

R18 10K
R19 10K

EECS

1
2

EECK

3

EEDI

4 5

EEDO

RXDV0
RXD03

RXD02
RXD01
RXD00
RXCLK0
TXEN0
TXD03
TXD02
TXD01
TXD00

CRS0

25M_USB0

VDD3

U8

CS

VCC
SK
DI
DO GND

93C56R

VDD3

8
7

NC

6

NC

ASIX ELECTRONIC CORPORATION

Title

AX88170 CIRCUIT 1

Size Document Number Rev

170AP5A1.SCH 2.0

B

Date: Sheet of

2 7Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 34

AX88170 USB to Fast Ethernet /HomePNA Controller

VDD3

GND

VDD3

VDD3

GND

J2 USB-CON

4 3

VDD5

12

GND

S S

C27

0.01u

D-

D+

48M_XIN

4
3
2
1

VDD3

Q2

2SC2412K

L6 F.B.

L7

2.2uH

C35
22pF

R23

1.5K

R24 18
R25 18

R27 20k

Y2

48M
C33
8p

R21

1K

C34
8p

R30

*4 USB Port Link/Act LED

VDD3

R22 330

C25

20P

20P

C29

C28

0.1u

0.1u

48M_XOUT

0

D2 LED

RST_USB#

R26 4.7KC26

C30

0.1u

C31

0.1u

C32

0.1u

48M_XOUT
48M_XIN

ACT/LINK#

RST#

ALDONE
D+
D-

VDD3
VDD3
VDD3
VDD3

VDD3

U9

51

48M_XOUT

52

48M_XIN

63

ACT/LINK

4

/RST

62

LEERDY

1

D+

2

D-

55

TEST0

56

TEST1

57

TEST2

58

/EP78DIS TEST3

61

TEST4

60

TEST_OUT

3

VDD

10

VDD

23

VDD

30

VDD

37

VDD

44

VDD

50

VDD

54

VDD

59

VDD

5

VSS

11

VSS

17

VSS

25

VSS

34

VSS

42

VSS

49

VSS

53

VSS

64

VSS

AX88170 L

/HOMELINK

GPIO1

/PHY_RST

GPIO0

RX_DV
RX_ER

RXD3
RXD2
RXD1
RXD0

RX_CLK

TX_EN

TXD3
TXD2
TXD1
TXD0

TX_CLK

CRS

COL

MDIO

MDC

25M_CLKO

25M_XIN

25M_XOUT

EEDO

EEDI
EECK
EECS

/S_RMII
/S_MAC

/S_FDPX

S_EXT

SPD_UP

41
40

39
38

RXDV

32
31

RXD3

29

RXD2

28

RXD1

27

RXD0

26

RXCLK

24

TXEN

22

TXD3

21

TXD2

20

TXD1

19

TXD0

18
16

CRS

15
13

14
12

33
35

36

EEDO

48

EEDI

47

EECK

46

EECS

45
43

9
8
7
6

R28 10K
R29 10K

EECS

1

EECK

2

EEDI

3

EEDO

4 5

RXDV1
RXD13

RXD12
RXD11
RXD10
RXCLK1
TXEN1
TXD13
TXD12
TXD11
TXD10

CRS1

25M_USB1

VDD3

U10

CS

VCC
SK
DI
DO GND

93C56R

VDD3

8
7

NC

6

NC

ASIX ELECTRONIC CORPORATION

Title

AX88170 CIRCUIT 2

Size Document Number Rev

170AP5A2.SCH 2.0

B

Date: Sheet of

3 7Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 35

AX88170 USB to Fast Ethernet /HomePNA Controller

VDD3

GND

VDD3

VDD3

GND

J3 USB-CON

4 3

VDD5

12

GND

S S

C38

0.01u

48M_XIN

VDD3

R33

1.5K

Y3

48M

R31

1K

R34 18
R35 18

C45
8p

R40

C37

C36

20P

20P

48M_XOUT

0

Q3

2SC2412K

4

D-

3

D+

2
1

L8 F.B.

R37 20k

L9

2.2uH

C46
22pF

C44

8p

*5 USB Port Link/Act LED

VDD3

R32 330

C40

C39

0.1u

0.1u

D3 LED

RST_USB#

R36 4.7K

C42

C41

0.1u

0.1u

C43

0.1u

48M_XOUT
48M_XIN

ACT/LINK#

RST#

ALDONE
D+
D-

VDD3
VDD3
VDD3
VDD3

VDD3

U11

51

48M_XOUT

52

48M_XIN

63

ACT/LINK

4

/RST

62

LEERDY

1

D+

2

D-

55

TEST0

56

TEST1

57

TEST2

58

/EP78DIS TEST3

61

TEST4

60

TEST_OUT

3

VDD

10

VDD

23

VDD

30

VDD

37

VDD

44

VDD

50

VDD

54

VDD

59

VDD

5

VSS

11

VSS

17

VSS

25

VSS

34

VSS

42

VSS

49

VSS

53

VSS

64

VSS

AX88170 L

/HOMELINK

GPIO1

/PHY_RST

GPIO0

RX_DV
RX_ER

RXD3
RXD2
RXD1
RXD0

RX_CLK

TX_EN

TXD3
TXD2
TXD1
TXD0

TX_CLK

CRS
COL

MDIO

MDC

25M_CLKO

25M_XIN

25M_XOUT

EEDO

EEDI
EECK
EECS

/S_RMII
/S_MAC

/S_FDPX

S_EXT

SPD_UP

41
40

39
38

32

RXDV

31
29

RXD3

28

RXD2

27

RXD1

26

RXD0

RXCLK

24
22

TXEN

21

TXD3

20

TXD2

19

TXD1

18

TXD0

16
15

CRS

13
14

12
33
35

36

EEDO

48

EEDI

47

EECK

46

EECS

45
43

9
8
7
6

R38 10K
R39 10K

EECS

1
2

EECK

3

EEDI
EEDO

4 5

RXDV2
RXD23

RXD22
RXD21
RXD20
RXCLK2
TXEN2
TXD23
TXD22
TXD21
TXD20

CRS2

25M_USB2

VDD3

U12

CS

VCC
SK
DI
DO GND

93C56R

8

VDD3

7

NC

6

NC

ASIX ELECTRONIC CORPORATION

Title

AX88170 CIRCUIT 3

Size Document Number Rev

170AP5A3.SCH 2.0

B

Date: Sheet of

4 7Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 36

AX88170 USB to Fast Ethernet /HomePNA Controller

VDD3

GND

VDD3

VDD3

GND

J4 USB-CON

4 3

VDD5

GND

12

S S

C49

0.01u

48M_XIN

VDD3

Y4

48M

R43

1.5K

R41

1K

R44 18
R45 18

C56
8p

R50

C48

C47

20P

20P

48M_XOUT

0

Q4

2SC2412K

4

D-

3

D+

2

L10 F.B.

1

R47 20k

L11

2.2uH

C57
22pF

C55
8p

*6 USB Port Link/Act LED

VDD3

R42 330

C50

C51

0.1u

0.1u

D4 LED

RST_USB#

R46 4.7K

C52

C53

0.1u

0.1u

C54

0.1u

48M_XOUT
48M_XIN

ACT/LINK#

RST#

ALDONE
D+
D-

VDD3
VDD3
VDD3
VDD3

VDD3

U13

51

48M_XOUT

52

48M_XIN

63

ACT/LINK

4

/RST

62

LEERDY

1

D+

2

D-

55

TEST0

56

TEST1

57

TEST2

58

/EP78DIS TEST3

61

TEST4

60

TEST_OUT

3

VDD

10

VDD

23

VDD

30

VDD

37

VDD

44

VDD

50

VDD

54

VDD

59

VDD

5

VSS

11

VSS

17

VSS

25

VSS

34

VSS

42

VSS

49

VSS

53

VSS

64

VSS

AX88170 L

/HOMELINK

GPIO1

/PHY_RST

GPIO0

RX_DV
RX_ER

RXD3
RXD2
RXD1
RXD0

RX_CLK

TX_EN

TXD3
TXD2
TXD1
TXD0

TX_CLK

CRS

COL

MDIO

MDC

25M_CLKO

25M_XIN

25M_XOUT

EEDO

EEDI
EECK
EECS

/S_RMII
/S_MAC

/S_FDPX

S_EXT

SPD_UP

41
40

39
38

RXDV

32
31
29

RXD3

28

RXD2
RXD1

27

RXD0

26
24

RXCLK
TXEN

22
21

TXD3
TXD2

20

TXD1

19

TXD0

18
16
15

CRS

13
14

12
33
35

36

EEDO

48

EEDI

47

EECK

46

EECS

45
43

9
8
7
6

R48 10K
R49 10K

EECS

1

EECK

2

EEDI

3

EEDO

4 5

RXDV3
RXD33

RXD32
RXD31
RXD30
RXCLK3

TXEN3
TXD33
TXD32
TXD31
TXD30

CRS3

25M_USB3

VDD3

U14

CS

VCC
SK
DI
DO GND

93C56R

VDD3

8
7

NC

6

NC

ASIX ELECTRONIC CORPORATION

Title

AX88170 CIRCUIT 4

Size Document Number Rev

170AP5A4.SCH 2.0

B

Date: Sheet of

5 7Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 37

AX88170 USB to Fast Ethernet /HomePNA Controller

U15

1

VDD

2

RXD<1><2>

3

RXD<1><3>

4

TXEN<1>

5

TXD<1><0>

6

TXD<1><1>

7

TXD<1><2>

8

TXD<1><3>

9

TXER<1> COL<1>

10

VSS

11

PULL_DN

12

PULL_DN

13

VDD

14

VSS

15

RXER<2>

16

RXDV<2>

17

CRS<2>

18

RXCLK<2>

19

RXD<2><0>

20

RXD<2><1>

21

RXD<2><2>

22

RXD<2><3>

23

TXEN<2>

24

TXD<2><0>

25

TXD<2><1>

26

TXD<2><2>

27

TXD<2><3>

28

TXER<2> COL<2>

29

VSS

30

RXER<3>

31

RXDV<3>

32

CRS<3>

33

RXCLK<3>

34

RXD<3><0>

35

RXD<3><1>

36

RXD<3><2>

37

RXD<3><3>

38

VDD

39

TXEN<3>

40

TXD<3><0>

41

TXD<3><1>

42

TXD<3><2>

43

TXD<3><3>

44

TXER3<3> COL<3>

45

VSS

46

PULL_DN

47

EN_FLOW-CTL

48

MODE

49

TXE_DELAY

50

VDD

51

RXER<4>

52

RXDV<4>

53

CRS<4>

54

VSS

55

VDD

56

RXCLK<4>

57

RXD<4><0>

58

RXD<4><1>

59

RXD<4><2>

60

RXD<4><3>

61

TXEN<4>

62

TXD<4><0> MEM_SIZE<0>

63

TXD<4><1> MEM_SIZE<1>

64

TXD<4><2> ENTRIES

65

TXD<4><3> ST_FW

66

TXER<4> COL<4>

67

COL_O<4>

68

VSS

69

/LCOL100

70

MDC

71

MDO

72

MCLK

73

/BMA<15>

74

/LUTI<0>

75

/LUTI<1>

76

/LUTI<2>

77

/LUTI<3>

78

/BMWR /IR_ACT_EN

79

BMA<8>

80

BMA<9>

AX88875AP

RXD<1><1>
RXD<1><0>

RXCLK<1>

CRS<1>
RXDV<1>
RXER<1>

COL<0> TXER<0>

TXD<0><3>
TXD<0><2>
TXD<0><1>
TXD<0><0>

TXEN<0>

VSS
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>

RXCLK<0>

CRS<0>
RXDV<0>
RXER<0>

VSS

VDD
PULL_DN
PULL_DN

VDD

/HALF10

LCLK

VSS

/RST

TEST1

/LACT<1>
/LACT<0>

VDD
/LACT<3>
/LACT<2>

/LACT<4>

VSS

/LPART<4>

LPART<3>
/LPART<2>
/LPART<1>
/LPART<0>

/TEST2
/LUTI<4>
/LUTI<5>

/LCOL10

/LSEL10

VDD

VSS
BMA<7>
BMA<6>
BMA<5>
BMA<4>

VDD
BMA<3>
BMA<2>
BMA<1>
BMA<0>

VSS
BMD<7>
BMD<6>
BMD<5>
BMD<4>
BMD<3>
BMD<2>
BMD<1>
BMD<0>

VSS

BMA<16>
BMA<15>
BMA<14>
BMA<13>
BMA<12>
BMA<11>
BMA<10>

VDD

160
159

R51 20

158
157
156
155
154
153
152
151
150
149

GND

148
147
146
145
144
143

R61 20

142
141
140
139

GND

VDD5

138
137
136
135

VDD5

134

LCLK

133

GND

132

RST#

131
130
129

NC

128
127
126

NC

125
124
123
122

NC

121

GND

120
119
118
117
116
115
114
113
112

COL10#

111
110

VDD5

109

GND

108

MA7

107

MA6

106

MA5

105
104

MA4

VDD5

103

MA3

102
101

MA2

100

MA1

MA0

99
98

GND

97

MD7

MD6

96
95

MD5

94

MD4

MD3

93

MD2

92

MD1

91

MD0

90
89

GND

MA16

88
87

MA15

MA14

86
85

MA13

84

MA12

MA11

83
82

MA10

VDD5

81

10K

VDD5

GND

VDD5
GND

R60 20

GND

R66 20

VDD5

GND

DISFC#
MODE0

VDD5

GND
VDD5

R70 20

MEMS0
MEMS1
ENTRY
ST_FW

GND
COL100#

10K

MWR#
MA8
MA9

RXD12
RXD13
TXEN1
TXD10
TXD11
TXD12
TXD13

R56
R57 10K

R59 10K

RXDV2

CRS2

RXCLK2

RXD20
RXD21
RXD22
RXD23
TXEN2
TXD20
TXD21
TXD22
TXD23

R65 10K

RXDV3

CRS3

RXCLK3

RXD30
RXD31
RXD32
RXD33

TXEN3
TXD30

TXD31 GND
TXD32
TXD33

R67 10K

R68 10K

RXER4
RXDV4

CRS4

RXCLK4

RXD40
RXD41
RXD42
RXD43
TXEN4
TXD40
TXD41
TXD42
TXD43
TXER4

R72

RXD11
RXD10

CRS1
RXDV1

TXD03
TXD02
TXD01
TXD00
TXEN0

RXD03
RXD02
RXD01
RXD00

CRS0
RXDV0

R63 10K

R64

25M_REP
RST_EN#

RXCLK1

R52 10K

RXCLK0

R62 10K

VDD5

GND

MEMS1

R53
R54
R55

R58

10K

LLED4

C58

C59

+

100u/16V

0.1u

0.1u

10K

ENTRY

10K

DISFC#

10K

MODE0

10K

U16

1

MA16
MA14
MA12
MA7
MA6
MA5
MA4
MA3
MA2 MA10
MA1
MA0
MD0
MD1
MD2
GND

COL10#

COL100#

C60

C61

0.1u

N.C.

2

A16

3

A14

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O1

14

I/O2

15

I/O3

16

VSS

HSRAM128*8

D5 LED

D6 LED

C63

C62

C64

0.1u

0.1u

0.1u

Title

Size Document Number Rev

Date: Sheet of

*7 Set memory size to 128KB
*8 ENTRIES Setting : High : 256

Low : 1024
*9 LOW: DIS_FLOW-CONTROL

*10 settingt to mode 0

VCC

WE_#

OE_#

CS1_#

R69

510

R71

510

C66

C65

0.1u

0.1u

AX88875 AP C.K.T.

170AP5A5.SCH 2.0

B

32

VDD5

31

MA15

A15

VDD5

30

CS2

29

MWR#

28

MA13

A13

27

MA8

A8

26

MA9

A9

MA11

25

A11

24

GND

23

A10

GND

22

MD7

21

I/O8

20

MD6

I/O7

19

MD5

I/O6

18

MD4

I/O5

MD3

17

I/O4

VDD5

10 GLOBAL COLLISION

100 GLOBAL COLLISION

C67

C68

0.1u

0.1u

C69

0.1u

C70

0.1u

C71

0.1u

6 7Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 38

25M_PHY

RST_EN#

VDD5

GND

LLED4

CRS4
RXER4
RXDV4

RXCLK4

RXD40
RXD41
RXD42
RXD43

TXEN4
TXER4
TXD40
TXD41
TXD42
TXD43

AX88170 USB to Fast Ethernet /HomePNA Controller

VDD5
GND

LLED4

25M_PHY
RST#

CRS
RXER
RXDV

RXCLK

RXD0
RXD1
RXD2
RXD3
TXEN
TXER
TXD0

TXD1
TXD2
TXD3

R81

6.2K

(1%)

AVDD5

AGND
AVDD5

RDN
RDP

AGND
TDN
TDP
AVDD5

AGND

AVDD5

AGND
TDN
TDP
AVDD5

25M_PHY
AGND

AVDD5
AVDD5
AGND

AGND

GND
VDD5
GND

GND

VDD5

U17

1

AVCC

2

NC

3

NC

4

NC

5

NC

6

AGND

7

AVCC

8

AVCC

9

RXI-

10

RXI+

11

AGND

12

AGND

13

10TXO-

14

10TXO+

15

AVCC

16

AVCC

17

AGND

18

AGND

19

NC

20

NC

21

AVCC

22

AVCC

23

AGND

24

AGND

25

100TXO-

26

100TXO+

27

AVCC

28

DVCC

29

OSC/X1

30

X2

31

DGND

32

OSC/XLT#

33

AVCC

34

AGND

35

BGRES

36

NC

37

DGND

38

DGND

39

AGND

40

AVCC

41

TRIDRV

42

UTP

43

SPEED10

44

RX_LOCK

45

DGND

46

NC

47

LINKSTS

48

CLK25M

49

DVCC

50 51

FDXLED# COLLED#

DM9191F

AGND
AGND

10BTSER

BPSCR

BP4B5B

BPALIGN

RPTR/NODE#

OPMODE3
OPMODE2
OPMODE1
OPMODE0

PHYAD4
PHYAD3

DVCC

DGND
PHYAD2
PHYAD1
PHYAD0

TESTDOME

RESET#

RX_EN

RX_ER/RXD4

RX_DV

COL
CRS

RX_CLK

DVCC

DGND

RXD0
RXD1
RXD2

RXD3
DVCC
DGND

MDIO

MDC

TX_CLK

TX_EN
DVCC
DGND

TXD0
TXD1
TXD2
TXD3

TX_ER/TXD4

TXLED#

RXLED#

LINKLED#

DGND

100

AGND

99
98
97
96

GND

95
94

VDD5

93

VDD5
VDD5

92

VDD5

91
90

VDD5
GND

89
88

GND
VDD5

87

GND

86
85

VDD5

84
83
82

GND

81

RST#

80

VDD5

79

RXER

78

RXDV

77

CRS

76
75

RXCLK

74

VDD5

GND

73

RXD0

72

RXD1

71

RXD2

70
69

RXD3

68

VDD5

67

GND

66
65
64
63

TXEN

62

VDD5

61

GND

60

TXD0

59

TXD1

TXD2

58

TXD3

57

TXER

56
55
54

LLED

53

GND

52

D7

R82 510

GREEN LED

Ethernet Port Link/Act LED

TDP
TDN
RDP
RDN

LLED4

AVDD5

R73

49.9

R75

49.9

C74

0.1u

R74

49.9

R76

49.9

TX 1CT:1CT
RX 1CT:1CT

16
14
15

1
3
2

C75

0.1u

C72

0.1u

T1

16
14
15

1
3
2

16ST8515

C73

0.01u/2KV

C76

0.01u

JP2

(ETHERNET UPLINK POART)

1
2
3
4
5
6
7
8

RJ45

(ETHERNET PORT)

JP3

1
2
3
4
5
6
7
8

RJ45

GND_E

CHASSIS

RJ03
RJ06
RJ01

RJ02

RJ03

10

10

12

12

RJ06

11

11

7

RJ01

7

5

5

RJ02

6

6

75

R77

R78

RJ01
RJ02
RJ03

RJ06

75

75

75

R80

R79

GND

VDD5

GND

VDD5

GND

C78
1000p

L12

F.B.

C79
1000p

C77

+

47u/16V

C86

+

47u/16V

C80

0.1u

C87

0.1u

AVDD5

AGND

0.1u

C81

C88

0.1u

0.1u

C82

C89

0.1u

0.1u

C83

C90

0.1u

0.1u

C84

0.1u

C91

C85

0.1u

0.1u

C92

0.1u

C93

Title

EtherNet PHY C.K.T.

Size Document Number Rev

170AP5A6.SCH 2.0

B

Date: Sheet of

7 7Monday, February 26, 2001

ASIX ELECTRONICS CORPORATION 39