Page 1
Integrated
Circuit
Systems, Inc.
ICS9248-169
Third party brands and names are the property of their respective owners.
Block Diagram
9248-169 Rev A- 6/05/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
440BX/VIA Apollo 133/694X style chipset.
Output Features:
• 2 - CPUs @2.5V, up to 166MHz.
• 1 - IOAPIC @ 2.5V
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management: PCI, CPU stop and Mode
• Spread spectrum for EMI control (± 0.50%).
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU – CPU: <175ps
• SDRAM - SDRAM: <500ps
• PCI – PCI: <500ps
• CPU(early)-PCI: Typ=1.0ns
Frequency Generator & Integrated Buffers for Celeron & PII/III™
CLK_STOP#
PCI_STOP#
PLL2
PLL1
Spread
Spectrum
48MHz
24MHz
IOAPIC
CPUCLK_F
CPUCLK 1
SDRAM (11:0)
PCICLK (4:0)
PCICLKF
SDRAM_F
X1
X2
BUFFER IN
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
STOP
STOP
S DATA
SCLK
FS(3:0)
MODE
Control
Logic
Config.
Reg.
/2
REF(1:0)
LATCH
POR
2
12
5
4
4
VDDREF
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDA
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
S DATA
SCLK
VDDL
IOAPIC
REF1/FS2*
GND
CPUCLK_F
CPUCLK1
VDDL
CLK_STOP#*
SDRAM_F
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24MHz/FS1*
ICS9248-169
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
3SF2SF1SF0SF
UPC
)zHM(
KLCICP
)zHM(
0000 00.0800.04
0001 00.5705.73
0010 13.3856.14
0011 28.6614.33
0100 00.30133.43
0101 10.21143.73
0110 10.8610.43
0111 32.00114.33
1000 00.02100.04
100 1 99.41133.83
10 10 99.90166.63
10 11 00.50100.53
1100 00.04100.53
1101 00.05105.73
1110 00.42100.13
1111 33.33133.33
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Page 2
2
ICS9248-169
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,91,41,6,1
63,03,72
DDVRWPylppusrewoPV3.3
2
0FERTUO.kcolcecnereferzhM813.41
#POTS_ICP
1
NI
nI(woltupninehw,level0cigoltaskcolc)4:0(KLCICPstlaH
)0=EDOM,edomelibom
,22,61,9,3
54,93,33
DNGRWPdnuorG
41XNI
kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
52XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp63(pac
7
F_KLCICPTUO
rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF
.tnemeganam
EDOM
2,1
NI
.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf7niP
.tupnIdehctaL
8
3SFNIDNGotnwod-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF
0KLCICPTUO
wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
01,11,21,31)1:4(KLCICPTUO
wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
,12,02,81,71
,23,13,92,82
83,73,53,43
)0:11(MARDSTUO
nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS
.)tespihcybdellortnoc(
32ATADSO/IIrofnipataD
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tnarelotV5yrtiucricC
42KLCSNIIfonipkcolC
2
tnarelotV5yrtiucricC
52
zHM42TUOkcolctuptuozHM42
1SF
2,1
NI.tupnIdehctaL.niptcelesycneuqerF
62
zHM84TUOkcolctuptuozHM84
0SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
04F_MARDSTUO#POTS_UPCybdetceffatoN.tuptuokcolcMARDSgninnureerF
14#POTS_KLCNI
MARDS&CIPAOI,1KLCUPCstlahtupnisuonorhcnysasihT
.wolnevirdnehwlevel"0"cigolta)11:0(
84,24LDDVRWPlanimonV3.3roV5.2rehtie,skcolcCIPAOI,UPCrofylppuS
341KLCUPCTUOwoL=#POTS_UPCfiwoL.2LDDVybderewop,stuptuokcolcUPC
44F_KLCUPCTUO#POTS_UPCehtybdetceffatoN.kcolcUPCgninnureerF
64
1FERTUO.kcolcecnereferzHM813.41
2SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
74CIPAOITUOCIPAOI.1LDDVybderewoPzHM813.41.tuptuokcolc
Page 3
3
ICS9248-169
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-169 is a single chip clock solution for Desktop
designs. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-169
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
7niP,EDOM
)tupnIdehctaL(
2niP
0
#POTS_ICP
)tupnI(
1
0FER
)tuptuO(
Power Groups
VDDREF = REF (1:0), X1, X2
VDDPCI = PCICLK_F , PCICLK(4:0)
VDDA = Supply for PLL core
VDD48 = 24MHz, 48MHz
VDDL = CPUCLK, CPUCLK_F , IOAPIC
VDDSDR = SDRAM
Page 4
4
ICS9248-169
Third party brands and names are the property of their respective owners.
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
A
CK
Byte 0
A
CK
Byte 1
ACK
Byte 2
A
CK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
A
CK
Stop Bit
How to Write:
Page 5
5
ICS9248-169
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
tiBnoitpircseDDWP
,2tiB
4:7tiB
)4,5,6,7,2(tiB
KLCUPC
)zHM(
KLCICP
)zHM(
10100
1etoN
00000 00.0800.04
00001 00.5705.73
00010 13.3856.14
00011 28.6614.33
00100 00.30133.43
00101 10.21143.73
00110 10.8610.43
00111 32.00114.33
01000 00.02100.04
01001 99.41133.83
01010 99.90166.63
01011 00.50100.53
01100 00.04100.53
01101 00.05105.73
01110 00.42100.13
01111 33.33133.33
10000 00.53157.33
10001 99.92105.23
100 10 00.62105.13
100 11 00.81133.93
10 100 89.51166.83
10 10 1 00.5976.13
10 110 00.0900.03
10111 10.5843.82
11000 00.66105.14
11001 10.06100.04
11010 99.45157.83
11011 59.74199.63
11100 89.54105.63
11101 89.34199.53
11110 99.14105.53
11111 10.83105.43
3tiB
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
4:7,2tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
daerpSretneC%05.0±delbanEmurtcepSdaerpS-1
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Page 6
6
ICS9248-169
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-X #2SFdehctaL
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB041 F_MARDS
2tiB-1 )devreseR(
1tiB341 1KLCUPC
0tiB441 F_KLCUPC
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB71 F_KLCICP
5tiB-1 )devreseR(
4tiB311 4KLCICP
3tiB211 3KLCICP
2tiB111 2KLCICP
1tiB011 1KLCICP
0tiB81 0KLCICP
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB-X #1SFdehctaL
2tiB-1 )devreseR(
1tiB-X #3SFdehctaL
0tiB-1 )devreseR(
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB741 CIPAOI
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB641 1FER
0tiB210FER
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-X #0SFdehctaL
5tiB621 zHM84
4tiB521 zHM42
3tiB-1 )devreseR(
2tiB
,02,12
71,81
1)11:8(MARDS
1tiB
,13,23
82,92
1)7:4(MARDS
0tiB
,73,83
43,53
1)3:0(MARDS
Page 7
7
ICS9248-169
Third party brands and names are the property of their respective owners.
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-169. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-169.
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-169
CLK_STOP# signal. SDRAM's are controlled as shown.
5. All other clocks continue to run undisturbed.
PCICLK
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
IOAPIC
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
Page 8
8
ICS9248-169
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-169. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-169 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-169 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-169.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Page 9
9
ICS9248-169
Third party brands and names are the property of their respective owners.
Fig. 1
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248169 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power -On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
T o program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K W
8.2K W
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Page 10
10
ICS9248-169
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD =V
DDL
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
S
YMBOL
CO
NDITION
S
MIN TYP MAX UNIT
S
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN=V
DD
5uA
Input Low Current I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5 uA
Input Low Current I
IL2
VIN = 0 V; Inputs with pull-up resistors -200 uA
I
DD3.3OP66CL
= 0 pF; Select @ 66.8 MHz 94
I
DD3.3OP100CL
= 0 pF; Select @ 100 MHz 130
Input frequency F
i
VDD = 3.3 V 12 14.318 16 MHz
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 45 pF
Clk Stabili
zation
1
T
STAB
From VDD = 3.3 V to 1% target Freq.
3ms
1
Guaranteed by design, not 100% tested in production.
mA
Operating Supply Current
Input Capacitance
1
180
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/- 5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
S
YMBOL
CO
NDITION
S
MIN TYP MAX UNIT
S
I
DD2.5OP66CL
= 0 pF; Select @ 66.8 MHz 72
I
DD2.5OP100CL
= 0 pF; Select @ 100 MHz 100
Sk
ew
1
t
CPU-PCI
VT = 1.5V; VTL = 1.25V
0.5 1.12 1.5 ns
1
Guaranteed by design, not 100% tested in production.
mA
Operating Supply Current
Page 11
11
ICS9248-169
Third party brands and names are the property of their respective owners.
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%, V
DDL
=2.5V +/- 5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH2B
IOH = -8 mA 2 2.4 V
Output Low Voltage V
OL2B
IOL = 12 mA 0.17 0.4 V
Output High Current
I
OH2B
VOH = 1.7 V -58 -16
mA
Output Low Current
I
OL2B
V
O
L
= 0.7 V 19 46
mA
Rise Time
1
t
r2B
V
O
L
= 0.4 V, VOH = 2.0 V 1.3 1.6 ns
Fall Time
1
t
f2B
VOH = 2.0 V, V
O
L
= 0.4 V 1.0 1.6 ns
Duty Cycle
1
d
t2B
VT = 1.25 V 45 47.5 55
%
Skew
1
t
sk2B
VT = 1.25 V 41 175 ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
VT = 1.25 V
216 250 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; V
DD
= 3.3V +/-5%, V
DDL
= 2.5V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH1
IOH = -11 mA 2.4 3.15 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.13 0.4 V
Output High Cu r rent
I
OH1
VOH = 2.0 V -97 -40
mA
Output Low Current
I
OL1
VOL = 0.8 V 41 69
mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.66 2.0 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.52 2.0 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 49.7 55 %
Skew
1
t
sk1
VT = 1.5 V 254 500 ps
Jitter, Absolute
1
t
jabs1
VT = 1.5 V
-500 180 500 ps
1
Guaranteed by design, not 100% tested in production.
Page 12
12
ICS9248-169
Third party brands and names are the property of their respective owners.
Electrical Characteristics - SDRAM
TA = 0 - 70C; V
DD
= 3.3V +/-5%, V
DDL
= 2.5V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH3
IOH = -28 mA 2.4 3.0 V
Output Low Voltage V
OL3
IOL = 20 mA 0.18 0.4 V
Output High Curre nt
I
OH3
VOH = 2.0 V -110 -40
mA
Output Low Current
I
OL3
VOL = 0.8 V 41 86
mA
Rise Time
1
t
r3
VOL = 0.4 V, VOH = 2.4 V 1.13 2 ns
Fall Time
1
t
f3
VOH = 2.4 V, VOL = 0.4 V 1.11 2 ns
Duty Cycle
1
d
t3
VT = 1.5 V 45 53.1 55 %
Skew
1
t
sk3
VT = 1.5 V 215 500 ps
1
Guaranteed by design, not 100% tested in pro duction.
5
Propagation Dela
y
1
(Buffer In to Output)
Tprop ns
V
T
= 1.5 V
3.26
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD=3.3V +/- 5%, V
DDL
=2.5V +/- 5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH4B
IOH = -8 mA 2 2.4 V
Output Low Voltage V
OL4B
IOL = 12 mA 0.17 0.4 V
Output High Curre nt
I
OH4B
VOH = 1.7 V -58 -16
mA
Output Low Current
I
OL4B
VOL = 0.7 V 19 46
mA
Rise Time
1
t
r4B
VOL = 0.4 V, VOH = 2.0 V 1.14 2 ns
Fall Time
1
t
f4B
VOH = 2.0 V, VOL = 0.4 V 1.07 2 ns
Duty Cycle
1
d
t4B
VT = 1.25 V 45 52.7 55
%
Jitter, Absolute
1
t
jabs4B
VT = 1.25 V
-1 0.27 1 ns
1
Guaranteed by design, not 100% tested in production.
Page 13
13
ICS9248-169
Third party brands and names are the property of their respective owners.
Electrical Characteristics - REF, 48MHz, 24MHz
TA = 0 - 70C; V
DD
= 3.3V +/-5%, V
DDL
= 2.5V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Volta ge V
OH5
IOH = -12 mA 2.4 3.03 V
Output Low Voltage V
OL5
IOL = 10 mA 0.23 0.4 V
Output High Current
I
OH5
VOH = 2.0 V -50 -22
mA
Output Low Current
I
OL5
VOL = 0.8 V 16 40
mA
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 1.26 4.0 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 1.57 4.0 ns
Duty Cycle
1
d
t5
VT = 1.5 V 45 53.3 55 %
Jitter, Absolute
1
t
jabs5
VT = 1.5 V
-1 0.25 1 ns
1
Guaranteed by design, not 100% tested in production.
Page 14
14
ICS9248-169
Third party brands and names are the property of their respective owners.
Ordering Information
ICS9248yF-169-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
h x 45°
h x 45°
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80.095.110
A1
0.20
0.40.008.016
b
0.20
0.34.008.0135
c
0.13
0.2
5.
00
5.
010DE
10.03
10.68.395.420E17.40
7.60.291.299eh
0.38
0.64.015.025L0.50
1.02.020.040
Nα0°8°0°8°MIN
MAX
MIN
MAX481
5.75
16.00.620.630
10-0034
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
N
D mm. D (inch)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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