Datasheet AV9248F-162-T, AV9248G-162-T, ICS9248F-162-T, ICS9248G-162-T Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9248-162

Block Diagram

Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

TM

& K6

9248-162 Rev A 8/31/00

Pin Configuration

 Up to 137MHz frequency support
 Spread Spectrum for EMI control
 Serial I

2

C interface for Power Management,

Frequency Select, Spread Spectrum.

 Provides the following system clocks

- 4-CPUs @ 2.5/3.3V, up to 137MHz.
(including CPUCLK_F)

- 9-SDRAMs @3.3V, up to 137MHz
(including SDRAM_F)

- 8-PCI @3.3V, CPU/2 or CPU/3
(including 1 free running PCICLK_F)

- 1-24/48MHz @3.3V

- 1-48MHz @3.3V fixed

- 2-REF @3.3V, 14.318MHz.

 Efficient Power management scheme through PCI

and CLK STOP CLOCKS

 Spread Spectrum ± .25%, & 0 to -0.5% down spread

48-Pin SSOP and TSSOP

Power Groups

VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F
VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F
VDD48, GND48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
VDDCOR = PLL CORE

* Internal Pull-up Resistor of 120K to VDD

The ICS9248-162 is the single chip clock solution for various
mobile chipset platforms. It provides all necessary clock signals
for such a system.

Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-162
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

VDDREF

REF0

GNDREF

X1
X2

VDDPCI

*CPU2.5_3.3#/PCICLK_F

*FS3/PCICLK0

GNDPCI

*SEL24_48#/PCICLK1

PCICLK2
PCICLK3
PCICLK4

VDDPCI

BUFFER IN

GNDPCI
PCICLK5
PCICLK6

VDDCOR

PCI_STOP#

*PD#

GND48

S DATA

SCLK

REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*

ICS9248-162

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

CLK_STOP#

PCI_STOP#

CPU2.5_3.3#

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK_F

CPUCLK (2:0)

SDRAM (7:0)

PCICLK (6:0)

PCICLK_F

SDRAM_F

X1

X2

BUFFER IN

XTAL
OSC

PCI

CLOCK

DIVDER

STOP

STOP

STOP

S DATA

SCLK

PD#

FS(3:0)

SEL24_48#

Control

Logic

Config.

Reg.

/ 2

REF(1:0)

LATCH

POR

2

3

8

7

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-162

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

NIP

REBMUN

EMANNIPEPYTNOITPIRCSED

1FERDDVRWPV3.3lanimon,ylppusrewopLATX,feR

20FERTUO sdaolSUBASIrofreffubREGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41

02#POTS_ICPNI )0=EDOM,edomelibomnI(woltupninehw,level0cigoltaskcolcKLCICPstlaH

,61,9,3

44,04,33

DNGRWPdnuorG

41XNI

kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

52XTUO.zHM813.41yllanimon,tuptuolatsyrC

41,6ICPDDVRWPV3.3lanimon,KLCICPdnaF_KLCICProfylppuS

7

#3.3_5.2UPC

2,1

NI .tupnIdehctaL.UPCV3.3=WOL,UPCV5.2=hgiH.V3.3ro5.2siUPCLDDVrehtehwsetacidnI

F_KLCICPTUO .tnemeganamrewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF

8

3SF

2,1

NI.tupnIdehctaL.niptcelesycneuqerF

0KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.tuptuokcolcICP

01

#84_42LES

2,1

NIzHM84=woLnehwzHM84ro42rehtiestceleS

1KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.tuptuokcolcICP

,31,71,81

,11,21

)2:6(KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.stuptuokcolcICP

51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
91ROCDDVRWPV3.3.erocLLPehtrofniprewoP

12#DP

1

NI

ehT.etatsrewopwolaotniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA

rewopehtfoycnetalehT.deppotseralatsyrcehtdnaOCVehtdnadelbasideraskcolclanretni

.sm4nahtretaergebtonlliwnwod

2284DNGRWP.erocLLPdexif&sreffubtuptuozHM84&42ehtrofnipdnuorG

,23,13,92,82

83,73,53,43

)0:7(MARDSTUO .)tespihcybdellortnoc(nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS

63,03RDSDDVRWP.V3.3lanimon,eroCLLPUPCdnaMARDSrofylppuS

32ATADSO/IIrofnipataD

2

tnarelotV5yrtiucricC

42KLCSNIIfotupnikcolC

2

tupnitnarelotV5,tupniC

52

zHM84_42TUO01nipybelbatceleskcolctuptuozHM84rozHM42

1SF

2,1

NI.tupnIdehctaL.niptcelesycneuqerF

62

zHM84TUOkcolctuptuozHM84

0SF

2,1

NItupnIdehctaL.niptcelesycneuqerF
7284DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
93F_MARDSTUO#POTS_UPCybdetceffatoN.tuptuokcolcMARDSgninnureerF
14#POTS_KLCNI .wolnevirdnehwlevel"0"cigoltaskcolcMARDS&,KLCUPCstlahtupnisuonorhcnysasihT

54,34,24]0:2[KLCUPCTUOUPCLDDVybderewop,stuptuokcolcUPC

64F_KLCUPCTUO#POTS_UPCehtybdetceffatoN.kcolcUPCgninnureerF

74UPCLDDVRWPV5.2skcolcUPCrofylppuS

84

1FERTUO.kcolcecnereferzHM813.41

2SF

2,1

NItupnIdehctaL.niptcelesycneuqerF

3

ICS9248-162

Functionality

VDD = 3.3V±5%, V

DDL

= 2.5V±5% or 3.3±5%, TA=0 to 70°C

Crystal (X1, X2) = 14.31818MHz

3SF2SF1SF0SF

UPC

)zHM(

ICP

)zHM(
0000 00.42133.14
0001 00.02100.04
0010 99.41133.83
0011 99.90166.63
0100 00.50100.53
0101 13.3856.14
0110 00.73152.43
0111 00.5705.73

1000 00.00133.33
100 1 00.5976.13
10 10 00.7933.23
10 11 33.33133.33
1100 00.0900.03
1101 22.6970.23
1110 28.6614.33
1111 5.195.03

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

tiBnoitpircseDDWP

7tiB

daerpSretneC,noitaludoMmurtcepSdaerpS%52.0±-0

daerpSnwoD%5.0-ot0-1

1

tiB

]4:6,2[

]4:6,2[tiB

KLCUPC

)zHM(

KLCICP
)zHM(

1etoN

000000.42133.14

100000.02100.04

010099.41133.83

110099.90166.63

001000.50100.53

101013.3856.14

011000.73152.43

111000.5705.73

000100.00133.33

100100.5976.13

010100.7933.23

110133.33133.33

001100.0900.03

101122.6970.23

011128.6614.33

11115.195.03

3tiB

stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0

)4:6,2(tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

delbanEmurtcepSdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

Notes:

1, Default at Power-up will be for latched

logic inputs to define frequency.
Bit (2, 6:4) are default to 0010.
2, PWD = Power-Up Default
3, When disabling spread spectrum bit7

needs to be set to 0 to maintain nominal

frequency.

4

ICS9248-162

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB71 )tcanI/tcA(F_KLCICP
6tiB811 )tcanI/tcA(6KLCICP
5tiB711 )tcanI/tcA(5KLCICP
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB641 )tcanI/tcA(F_KLCUPC
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB931 )tcanI/tcA(F_MARDS
2tiB241 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB541 )tcanI/tcA(0KLCUPC

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB821 )evitcanI/evitcA(7MARDS
2tiB921 )evitcanI/evitcA(6MARDS
1tiB131 )evitcanI/evitcA(5MARDS
0tiB231 )evitcanI/evitcA(4MARDS

5

ICS9248-162

Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)

Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-X #)84_42LES(
4tiB-1 )devreseR(
3tiB-X #1SFdehctaL
2tiB-1 )devreseR(
1tiB-X #3SFdehctaL
0tiB-1 )devreseR(

tiB#niPDWPnoitpircseD

7tiB431 )tcanI/tcA(3MARDS

6tiB531 )tcanI/tcA(2MARDS

5tiB731 )tcanI/tcA(1MARDS

4tiB831 )tcanI/tcA(0MARDS

3tiB621 )tcanI/tcA(zHM84

2tiB521 )tcanI/tcA(zHM42

1tiB841 )tcanI/tcA(1FER

0tiB21 )tcanI/tcA(0FER

6

ICS9248-162

Absolute Maximum Ratings

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Logic Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = V

DDL

= 3.3 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage V

IH

2V

DD

+0.3 V

Input Low Voltage V

IL

VSS-0.3 0.8 V

C

L

= 0 pF; Select @ 66MHz 90 150

C

L

= 0 pF; Select @ 100MHz 120 170

C

L

= 0 pF; Select @ 133MHz 151 180

Powerdown Current

I

DDPD

CL = 0 pF; Input address VDD or GND 250 600

µA

Input Frequency F

i

VDD = 3.3 V 12 14.318 16 MHz

Input Capacitance

1

C

IN

Logic Inputs 5 pF

C

INX

X1 & X2 pins 27 36 45 pF

Clk Stabilization

1

T

STAB

From VDD = 3.3 V to 1% target Freq. 5.5 ms

Skew

1

t

CPU-PCI1

VT = 1.5 V

12.8 4 ns

1

Guaranteed by design, not 100% tested in production.

mA

Operating Supply

Current

I

DD3.3OP

Electrical Characteristics - Input/ Suppl y/Common Output Parameters

TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

C

L

= 0 pF; Select @ 66.8 MHz 8

15

C

L

= 0 pF; Select @ 100 MHz 11

18

C

L

= 0 pF; Select @ 133 MHz 17

20

Powerdown Current

I

DDLPD

CL = 0 pF; Input address VDD or GND <1

10

µA

Skew

1

t

CPU-PCI2

VT = 1.5 V; VTL = 1.25 V

12.4 4 ns

1

Guaranteed by design, not 100% tested in production.

perating SupplyCurre

n

I

DDL2.5

mA

7

ICS9248-162

Electrical Characteristics - CPU

TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage V

OH2A

IOH = -20 mA 2.4 2.85 V

Output Low Voltage V

OL2A

IOL = 12 mA 0.31 0.4 V

Output High Current I

OH2A

VOH = 2.0 V -45 -27 mA

Output Low Current I

OL2A

VOL = 0.8 V 22 29 mA

Rise Time

1

t

r2A

VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns

Fall Time

1

t

f2A

VOH = 2.4 V, VOL = 0.4 V 1.4 2 ns

Duty Cycle

1

d

t2A

VT = 1.5 V 45 55 %

Skew window

1

t

sk2A

VT = 1.5 V 80 175 ps

Jitter, Cycle-to-cycle

1

t

jcyc-cyc2A

VT = 1.5 V

200 250 ps

1

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - CPU

TA = 0 - 70C; V

DDL

= 2.5 V +/-5%; CL = 20 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage V

OH2B

IOH = -12 mA 2 2.3 V

Output Low Voltage V

OL2B

IOL = 12 mA 0.31 0.4 V

Output High Current I

OH2B

VOH = 1.7 V -39 -21 mA

Output Low Current I

OL2B

VOL = 0.7 V 22 26 mA

Rise Time

1

t

r2B

VOL = 0.4 V, VOH = 2.0 V 1.3 1.6 ns

Fall Time

1

t

f2B

VOH = 2.0 V, VOL = 0.4 V 1.4 1.6 ns
V

T

= 1.25 V, < 133 MHz 45 47.5 55

V

T

= 1.25 V, >= 133 MHz 42 47 52

Skew window

1

t

sk2B

VT = 1.25 V 70 175 ps

Jitter, Cycle-to-cycle

1

t

jcyc-cyc2B

VT = 1.25 V

200 300 ps

1

Guaranteed by design, not 100% tested in production.

Duty Cycle

1

d

t2B

%

8

ICS9248-162

Electrical Characteristics - PCI

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage V

OH1

IOH = -18 mA 2.4 3 V

Output Low Voltage V

OL1

IOL = 9.4 mA 0.2 0.4 V

Output High Current I

OH1

VOH = 2.0 V -62 -33 mA

Output Low Current I

OL1

VOL = 0.8 V 38 43 mA

Rise Time

1

t

r1

VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns

Fall Time

1

t

f1

VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns

Duty Cycle

1

d

t1

VT = 1.5 V 45 50 55 %

Skew window

1

t

sk1

VT = 1.5 V 180 500 ps

Jitter, One Sigma

1

t

j

1s1

VT = 1.5 V 15 150 ps

Jitter, Absolute

1

t

jabs1

VT = 1.5 V

-250 75 250 ps

1

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - SDRAM

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage

V

OH3

IOH = -28 mA

2.4 3 V

Output Low Voltage

V

OL3

IOL = 19 mA

0.3 0.4 V

Output High Current

I

OH3

VOH = 2.0 V

-69 -46 mA

Output Low Current

I

OL3

VOL = 0.8 V

32 42 mA

Rise Time

1

T

r3

VOL = 0.4 V, VOH = 2.4 V

11.3ns

Fall Time

1

T

f3

VOH = 2.4 V, VOL = 0.4 V

1.3 2 ns

Duty Cycle

1

D

t3

VT = 1.5 V

45 50 55 %

Skew window

1

T

sk3

VT = 1.5 V

185 250 ps

Propagation Time

1

(Buffer In to output)

T

sk3

VT = 1.5 V

45ns

1

Guaranteed by design, not 100% tested in production.

9

ICS9248-162

Electrical Characteristics - 24,48M Hz, REF

TA = 0 - 70C; VDD = V

DDL

= 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAM ETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage V

OH5

IOH = -14 mA 2.4 2.6 V

Output Low Voltage V

OL5

IOL = 6 mA 0.22 0.4 V

Output High Current I

OH5

VOH = 2.0 V -32 -20 mA

Output Low Current I

OL5

VOL = 0.8 V 16 22 mA

Rise Time

1

t

r5

VOL = 0.4 V, VOH = 2.4 V 2 4 ns

Fall Time

1

t

f5

VOH = 2.4 V, VOL = 0.4 V 2 4 ns

Duty Cycle

1

d

t5

VT = 1.5 V 45 1 55 %

Jitter, One Sigma

1

t

j1s5

VT = 1.5 V 150 250 ps

Jitter, Absolute

1

t

jabs5

VT = 1.5 V

-600 600 ps

1

Guaranteed by design, not 100% tested in production.

10

ICS9248-162

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

AC

K

Byte Count

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte 4

ACK

Byte

5

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D2

(H)

AC

K

Dummy Command Code

AC

K

Dummy Byte Count

AC

K

Byte 0

AC

K

Byte 1

ACK

Byte 2

AC

K

Byte 3

AC

K

Byte 4

AC

K

Byte 5

AC

K

Stop Bit

How to Write:

11

ICS9248-162

CLK_STOP# Timing Diagram

CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-162. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.

Notes:

1. All timing is referenced to the internal CPU clock.

2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized

to the CPU clocks inside the ICS9248-162.

3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-162

CLK_STOP# signal. SDRAMs are controlled as shown.

4. All other clocks continue to run undisturbed.

PCICLK

SDRAM

CPUCLK

CPUCLK _F

SDRAM_F

PCI_STOP# (High)

CLK_STOP#

INTERNAL

CPUCLK

12

ICS9248-162

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.

Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP#
are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).

2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.

3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.

4. The shaded sections on the VCO and the Crystal signals indicate an active clock.

5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.

CPUCLK

PCICLK

VCO

Crystal

PD#

13

ICS9248-162

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9248-162. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-162 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.

3. All other clocks continue to run undisturbed.

4. CLK_STOP# is shown in a high (true) state.

CPUCLK
(Internal)

PCICLK_F

(Internal)

PCICLK_F

(Free-running)

CLK_STOP#

PCICLK

PCI_STOP#

14

ICS9248-162

Fig. 1

Shared Pin Operation ­Input/Output Pins

The I/O pins designated by (input/output) on the ICS9248­162 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.

To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.

Via to
VDD

Clock trace to load

Series Term. Res.

Programming
Header

Via to Gnd

Device
Pad

2K 

8.2K 

Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.

15

ICS9248-162

Ordering Information

ICS9248yF-162-T

Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)
Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y F - PPP - T

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

MIN MAX MIN MAX

A 2.413 2.794 .095 .110

A1 0.203 0.406 .008 .016

b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420

E1 7.391 7.595 .291 .299

e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N

α

0° 8° 0° 8°

VARIATIONS

MIN MAX MIN MAX

48 15.748

16.002

.620 .630

JEDEC MO-118

DOC# 10-0034

6/1/00

REV B

SYMBOL

SEE VARIATIONS

SEE VARIATIONS

In Millimeters

COMMON DIMENSIONS

In Inches

COMMON DIMENSIONS

SEE VARIATIONS

N

D mm.

D (inch)

SEE VARIATIONS

16

ICS9248-162

Ordering Information

ICS9248yG-162-T

Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type

G=TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)
Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y G - PPP - T

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil)

(0.020 mil)

MIN MAX MIN MAX

A - 1.20 - .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041

b 0.17 0.27 .007 .011

c 0.09 0.20 .0035 .008
D
E

E1 6.00 6.20 .236 .244

e 0.50 BASIC 0.020 BASIC

L 0.45 0.75 .018 .30
N

α

0° 8° 0° 8°

aaa - 0.10 - .004

VARIATIONS

MIN MAX MIN MAX

48 12.40

12.60

.488 .496

MO-153 JEDEC

Doc.# 10-0039

7/6/00 Rev B

SYMBOL

SEE VARIATIONS

SEE VARIATIONS

In Millimeters

COMMON DIMENSIONS

In Inches

COMMON DIMENSIONS

SEE VARIATIONS

8.10 BASIC 0.319

N

D mm.

D (inch)

SEE VARIATIONS