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AV9178Y-03
Datasheet (ICST)
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Datasheet AV9178Y-03, ICS9178Y-03 Datasheet (ICST)

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Page 1
Integrated Circuit Systems, Inc.
General Description Features
ICS9178-03
Block Diagram
ICS9178-03 Rev C 02/12/98P
245 MHz Clock Generator and Integrated Buffer for PowerPC
Generates 2 PECL 2x processor, 2 TTL/CMOS 1x
processor and 10 selectable bus clocks
2XPCLK ranges from 75 MHz to 245 MHz (5V or
5V/3.3V mixed supply) or 60 to 170 MHz (3.3V only)  Asymmetric duty cycle bus clock for PowerPC  Bus to processor clock skews less than ±250ps  2XPCLK to PCLK skew controlled at 300 ±300ps  Selectable reference multiplying factors  Selectable PCLK/BCLK and PCLK/XCLK ratios  Separate supplies allow 5V and 3.3V output mix  3.0V - 5.5V supply range  44-pin PQFP package
PowerPC is a trademark of Motorola Corporation.
Applications
Ideal for high-speed systems based on PowerPC
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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ICS9178-03
Pin Configuration
44-Pin PQFP
*VCO range is limited from 75- 245 MHz at 5V ±5% and 60 - 170 MHz at 3.3V ±5%. Divide ratios assume BCLK is externally fed back to FBCLK.
_=A,B,C
Functionality
The 2XPCLK series or Thevinen trace terminations must be optimized for the specific operating frequency and board layout. The rising edge of ABCLK is coincident with the rising edges of 2XPCLK, PCLK and other BCLKs.
X_S1 X_S0 XCLK_(0,1)
00PCLK 0 1 BCLK 10DCLK 1 1 Tristate
FS1 FS0 RST TEN *VCO 2XPCLK PCLK ABCLK (H/L%) BCLK DCLK
00106x REFVCOVCO/2VCO/6 (66/33)VCO/6VCO/4 01108x REFVCOVCO/2VCO/8 (75/25)VCO/8VCO/4 10104x REFVCOVCO/2VCO/12 (50/50)VCO/4VCO/4 1110X11 1 11
XX0XX00000
0011TCLKTCLKTCLK/2TCLK/6 (66/33)TCLK/6TCLK/4 0111TCLKTCLKTCLK/2TCLK/8 (75/25)TCLK/8TCLK/4 1011TCLKTCLKTCLK/2TCLK/12 ( 66/33)TCLK/12TCLK/4 1111TCLKTCLKTCLK/2TCLK/2TCLK/2TCLK/4
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ICS9178-03
Pin Description
*=Pin is pulled-up to VDD internally by the device.
PIN NUMBER PIN NAME TYPE DESCRIPTION
32 XAS0 Input LSB Programm able Group A frequency selector. 31 XAS1 Input MSB Program mable Group A frequency selector.
6 XCLKA0 Output TTL/CMOS group A programmable clock output.
5 XCLKA1 Output TTL/CMOS group A programmable clock output. 30 XBS0 Input LSB Programmable G roup B frequency selecto r. 29 XBS1 Input M SB Programmab le Group B frequen cy selector.
3 XCLK B0 O utput TTL /CMOS G roup B program mable clock output.
2 XCLK B1 O utput TTL /CMOS G roup B program mable clock output.
1 VDDXBA — Power for pro grammable Gro up A and B buffers (Pins 2, 3, 5, 6).
4 GNDXBA — Ground for programmable Group A and B buffers (Pins 2, 3, 5, 6). 44 GNDXC — Ground for the programmable Group C buffers (Pins 42 and 43). 43 XCLKC 0 Ou tput TTL /CMOS Grou p C programm able clock output. 42 XCLKC 1 Ou tput TTL /CMOS Grou p C programm able clock output. 41 VDDXC — Power for the XC signal output buffers (Pins 42 and 43). 28 XCS0 Input LSB Programmable G roup C frequency selecto r. 27 XCS1 Input M SB Programmab le Group C frequen cy selector. 11 PCLK0 Output TTL/CMOS 1X Processor clock ou tput. 10 PCLK1 Output TTL/CMOS 1X Processor clock ou tput.
8 GNDP — Ground for PCLK output buffers (Pins 11 and 10).
7 VDDP — Power for PCLK output buffers (Pins 11 and 10). 22 2XPCLK0 Output PECL 2X Processor clock output. 21 2XPCLK1 Output PECL 2X Processor clock output. 24 EVDD — Power for PECL buffers (Pins 21 and 22 ). 23 EGND — Ground for PECL buffers (Pins 21 and 2 2). 20 EGND — Ground for PECL buffers (Pins 21 and 2 2).
38* FS0 Input LSB frequency select PLL (divider mode control). 37* FS1 Input MSB frequenc y select PLL (divider mode control).
36 FBCLK Input External PLL feedback path from one of the BCLK outputs. 35 REFCLK Input Extern al reference clock input. 25 AVDD — Power for the analog PLL circuitry. 26 AGND — Ground for the analog PLL circuitry. 19 DCLK Output TTL/CMOS D clock output. 16 VDDD — Power for D output buffers (Pin 19). 17 GNDD — Ground for D output buffer (Pin 19). 15 BCLK0 Output TTL/CMOS B (Bus) clock output. 14 BCLK1 Output TTL/CMOS B (Bus) clock output. 13 GNDBAB — Ground for output buffers AB and B clocks (Pins 14, 15 & 18). 12 VDDBAB — Power for output buffers AB and B clocks (Pins 14, 15 & 18). 18 ABCLK Output TTL/CMOS AB Bus clock (has Asymmetric duty cycle). 40 TCLK Input External test clock input. 39 TEN# Input Test enable (tie low).
9 RESET # Input Sy nc register reset (active low). 33 VDD — Digital power s upply for 5.0 or 3.3V. 34 GND — Digital ground s upply.
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ICS9178-03
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics
Device Specifications
DC Characteristics
VDD =+5V ±5%, 0°C ≥ TAMBIENT ≥ +70°C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.
Maximum Ratings
DESCRIPTION SYMBOL MIN MAX UNITS Supply vo ltage rela tive to GN D VDD -0.5 7.0 V Input voltage with respect to GND V
IN -0.5 VDD +0.5 V
Operating temperature T
OPER 0+70°C
Storage temperature T
STOR -65 +150 °C
Max soldering temperatu re (10 sec) T
SOL +260 °C
Junction tempera ture T
j +135 °C
Package power dissipation P
DISS 800 900 mWatts
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
High level input voltage V
IH 2.0 V
Low level input voltage V
IL 0.8 V
High level CMOS output voltage V
OH IOH=-25mA 2.4 V
Low level CMOS output voltage V
OL IOL=25mA 0.4 V
High level PECL output voltage (2XPCLK) (Note 1)
V
OHP 110 ohm load to ground 1.9 2.2 V
Low level PECL output voltage (2XPCLK) (Note 1)
V
OLP 110 ohm load to ground 0.3 0.5 V
Input high cu rrent I
IH VIH=V DD -10 10 µA
Input low current (MSX pins, pull-up) I
IL1 VIL=0V -150 µA
Input low current (other inputs) I
IL2 VIL=0V -10 10 µ A
Output leakage current (XCLKs) I
OZ (tristate) -10 10 µA
Power supply current I
DD
@240 MHz on 2XPCLK
145 185 mA
Power supply current (typical) (Note 1) I
DD-TYP @75 MHz on 2XPCLK 80 100 mA
Input capacitance (Note 1) C
IN 8pF
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ICS9178-03
AC Characteristics
V
DD
=+5V ±5%, 0°C ≥ TAMBIENT ≥ +70°C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production. Note 2: For 70Ω Load, 2XPCLK level may be pulled-up with a 390Ω resistor to meet minimum pulse width requirements at both 1.8V and 0.6V at 240 MHz.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Freque ncy (Note 1) fi 8 40.0 50.0 MHz Input Clock Rise time (Note 1) ICLKr - - 3 ns Input Clock Fall time (Note 1) ICLKf - - 3 ns Output Frequency (2XPCLK) fo2XPCLK 6X mode, 8X mode 75 245 M Hz
4X mode 75 240
Output Rise time, 0. 8 to 2.0V 20% to 80% (Note 1)
tr2XPCLK 15 pF load 0.8 to 2.0V - - 1.0 ns
20% to 80% - - 1.5
Fall time 2.0 to 0.8 80% to 20% (Note 1)
tf2XPCLK 15 pF load 2.0 to 0.8V - - 1.0 ns
80% to 20% 1.5
Output Rise time 80% to 20% (Note 1)
t(TTL)r 15pF load - - 3.0 ns
Output Fall time 80% to 20% (Note 1)
t(TTL)f 15pF load - - 2.0 ns
Duty cycle 2XPCLK (Note 1) dt1
200 to 240 MHz @ 1.4V 110 ohm, 15pF load
42.5 50 57.5 %
Pulse Width, High, 2XPCL K (Note 1, 2)
Tpwr @ 1.8V, 110
ΩLoad 2 1.2 - - ns
Pulse Width, Low, 2XPCLK (Note 1, 2)
Tpwr @ 0.6V, 110
ΩLoad 2 1.0 - - ns
Duty cycle ABCLK (Note 1) dt3 15pF load @ 1.4V (8X mode) 70 75 80 % Duty cycle ABCLK (Note 1) dt4 15pF load @ 1.4V 6X mode 61 66 71 %
15pF load @ 1.4V 4X mode 45 50 55
Duty cycle TTL (other clocks) (Note 1)
dt5 15pF load @ 1.4V 45 50 55 %
Jitter 1 Sigma 2XPCLK (10,000 samples) (Note 1)
Tj1s1
for 200 to 240 M Hz on 2XPCLK
-40-ps
Jitter 1 Sigma 1XPCLK B & D (10,000 samp les) (Note 1)
Tj1s2
for 200 to 240 M Hz on 2XPCLK
-50-ps
Jitter 1 Sigma AB clock (10,000 samples) (Note 1)
Tj1s3
for 200 to 240 M Hz on 2XPCLK
-60-ps
Jitter Absolute 2XPCLK (Note 1) Tjabs1
for 200 to 240 M Hz on 2XPCLK
-150 80 +150 ps
Jitter Absolute 1XPCLK, B, D clocks (Note 1)
Tjabs2
for 200 to 240 M Hz on 2XPCLK
-200 110 +200 ps
Jitter Absolute AB clock (Note 1) Tjabs3
for 200 to 240 M Hz on 2XPCLK
-250 120 +250 ps
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ICS9178-03
AC Characteristics (continued)
V
DD
=+5V ±5%, 0°C ≥ TAMBIENT ≥ +70°C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production. Note 2: For 70Ω Load, 2XPCLK level may be pulled-up with a 390Ω resistor to meet minimum pulse width requirements at both 1.8Vand 0.6Vat 240 Mhz. Note 3: 2XPCLK is normally earlier than DCLK by up to 600ps and can be later by up to
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Jitter Absolute 2XPCLK (Note 1) T
jabs4
for 200 to 240 M Hz on 2XPCLK at VDD 4.9 to
5.2V
-125 80 +125 ps
Jitter Absolute 1XPCLK, B, D clocks (Note 1)
T
jabs5
for 200 to 240 M Hz on 2XPCLK at VDD 4.9 to
5.2V
-160 110 +160 ps
Jitter Absolute 2XPCLK (Note 1) T
jabs6 for < 200 M Hz on 2XPCLK -200 - +200 ps
Jitter Absolute 1XPCLK (Note 1) T
jabs7 for < 200 M Hz on 2XPCLK -250 - +250 ps
Jitter Absolute AB clock (Note 1) T
jabs8 for < 200 M Hz on 2XPCLK -300 - +300 ps
Skew, output to output (P, B, D , AB abd XCLKs) (Note 1)
T
skew1 @ 1.4V -250 - +250 ps
Skew, 2XPCLK to P CLK (2XPC LK is earlier than PCLK) (Note 1)
T
skew2 @ 1.4V -600 -300 0 ps
Skew, 2XPCLK to R EFCLK (2XP CLK is earlier) (Note 1)
T
skew3
for 240 MHz on 2XPCLK @ 1.4V
-600 -300 0 ps
Skew, 2XPCLK to DCLK (Notes 1,3) T
skew4 @ 1.4V -600 -100 1 00 ps
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ICS9178-03
PwrPC 603/604 System Clock Diagram
Applications
PwrPC 601/601+Processor Modules
PwrPC 601\601+ System Clock Diagram
Frequency Combinations
(XCLK pairs selectable)
Frequency Combinations
(selectable SCLK)
Frequency Combinations
(9178 x4 mode)
SYS BUS
9178
MODE
2XPCLK (2XCPU)
PCLK(0,1)
(CPU)
XCLK(0,5)
(BUS)
BCLK(0,1)
ABCLK F x4 4F 2F 2F, 1F 1F F x6 6F 3F 3F, 1.5F, 1F 1.5F F 8F 8F 4F 4F, 2F, 1F 2F
OSC
9178
MODE
2XPCLK (2XCPU)
PCLK
(CPU)
XCLK (BUS)
Q (PCI)
Fx4 4F 2F 2F, 1F 1F F x6 6F 3F 3F, 1.5F, 1F 1.5F
F 8F 8F 4F 4F, 2F, 1F 2F 33 x4 132 66 66, 33 33 33 x6 196 99 99, 48, 33 33 33 x8 264 132 132, 66, 33 33 30 x4 120 60 60, 30 30 30 x6 180 90 90, 45, 30 30 30 x8 240 120 120, 60, 30 30 25 x4 100 50 50, 25 25 25 x6 150 75 75, 37, 25 25 25 x8 200 100 100, 50, 25 25
OSC
PwrPC MODE
PCLK,
DCLK (CPU)
PwrPC
INTERNAL
CLOCK
PCLK(0,1) XCLK(0,3)
(BUS)
ABCLK, BCLK(0,1) XCLK(4,5)
F - 2F, 1F - 2F, 1F F 33 x1, x2 66, 33 66 66, 33 33 PCI) 40 x1, x2 80, 40 80 80, 40 40 (VL) 33 x3 -, 33 100 66, 33 33 (PCI) 30 x2, x4 60, 30 120 60, 30 30 (PCI) 40 x3 -, 40 120 80, 40 40 (VL) 33 x2, x4 66, 33 132 66, 33 33 (PCI)
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ICS9178-03
ICS XXXX- M PPP
Ordering Information ICS9178Y-03
Example:
PQFP Package
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
Y=QFP
Device Type (consists of 3 or 4 digit numbers) Prefix
ICS, AV=Standard
LEAD COUNT 44L
BODY THICKNESS 2.0
FOOTPRINT (BODY+) 3.20
DIMENSIONS TOLERANCE
A MAX. 2.45 A1 MAX. 0.25 A2 ±0.10 2.00
D ±0.25 13.20 D1 ±0.10 10.0
E ±0.25 13.20 E1 ±0.10 10.0
L ±0.15/-0.10 0.70
e BASIC 0.80
b +0.05 0.35 ccc MAX. 0.10
∝
0° - 7°
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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