Page 1
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9148-10
Block Diagram
Pentium/ProTM System Clock Chip
9148-10 Rev D 9/27/99
Pin Configuration
48-Pin SSOP
Pentium is a trademark on Intel Corporation.
Generates system clocks for CPU, IOAPIC, PCI, plus
14.314 MHz REF (0:2), USB, and Super I/O
Supports single or dual processor systems
Supports Spread Spectrum modulation for CPU & PCI
clocks, down spread -1%
Skew from CPU (earlier) to PCI clock (rising edges for
100/33.3MHz) 1.5 to 4ns
Two fixed outputs at 48MHz.
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V output: CPU, IOAPIC
3.3V outputs: PCI, REF, 48MHz
No power supply sequence requirements
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal
48 pin 300 mil SSOP
The ICS9148-10 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
Features include four CPU and eight PCI clocks. Three
reference outputs are available equal to the crystal frequency.
Additionally, the device meets the Pentium power-up
stabilization requirement, assuring that CPU and PCI clocks
are stable within 2ms after power-up.
PD# pin enables low power mode by stopping crystal OSC
and PLL stages. Other power management features include
CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#,
which stops PCICLK (0:6) clocks.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates.
The ICS9148-10 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:6)
VDD3 = 48MHz0, 48MHz1
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)
Ground Groups
GND = Ground for PLL core
GND1 = REF (0:2), X1, X2
GND2 = PCICLK_F, PCICLK (0:6)
GND3 = 48MHz0, 48MHz1
GNDL1 = IOAPIC (0:1)
GNDL2 = CPUCLK (0:3)
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
Page 2
2
ICS9148-10
Pin Descriptions
Select Functions
Notes:
1. TCLK is a test clock driven on the X1 (crystal in
pin) input during test mode.
2. -1% modulation down spread from the selected
frequency.
3. Performance not guaranteed
ytilanoitcnuFUPC
,ICP
F_ICP
FERCIPAOI
zHM84
noitceleS
etatsirTZ-IHZ-IHZ-IHZ-IHZ-IH
edomtseT2/KLCT
1
6/KLCT
1
KLCT
1
KLCT
1
2/KLCT
1
murtcepSdaerpSdetaludoM
2
detaludoM
2
zHM813.41zHM813.41zHM0.84
#66/001LES1SF0SFnoitcnuF
000 etatS-irT
001 7.95
3
010 6.47
3
011 ICP3.33,UPCzHM6.66evitcA
100 edoMtseT
101 3.331
3
110 9.28
3
111 ICP3.33,UPCzHM001evitcA
REBMUNNIPEMANNIPEPYTNOITPIRCSED
74,2,1)2:0(FERTUOtuptuokcolczHM813.41
31DNGRWPstuptuoFERrofdnuorG
41XNI
daolFp33lanretnisah,tupnilatsyrCzHM813.41NI_LATX
2Xmorfrotsiserkcabdeefdnapac
52XTUOFp33pacdaollanretnisah,tuptuolatsyrCTUO_LATX
81,21,62DNGRWPstuptuoICProfdnuorG
7F_KLCICPTUOtuptuoICPgninnuReerF
71,61,41,31,11,01,8)6:0(KLCICPTUOV3.3elbitapmocLTT.stuptuokcolcICP
51,92DDVRWPV3.3yllanimon,stuptuoKLCICProfrewoP
33,91DDVRWPV3.3yllanimon,erocrofrewopdetalosI
23,02DNGRWPerocrofdnuorgdetalosI
123DDVRWPV3.3yllanimon,stuptuozHM84rofrewoP
32,22)1:0(zHM84TUOstuptuozHM84
423DNGRWPstuptuozHM84rofdnuorG
52#6.66/001LESNI
zHM6.66rozHM001gnilbanerofniptceleS
)zHM3.33suonorhcnyssyawlaICP(zHM6.66=L,zHM001=H
72,62)1:0(SFNIsniptceleSycneuqerF
82#DAERPSNIWOLnehwerutaefmurtcepSdaerpSselbanE
92#DPNIwolevitca,pihcnwodsrewoP
03#POTS_UPCNIwolnehwlevel"0"cigoltaskcolcUPCstlaH
13#POTS_ICPNIwolnehwlevel"0"cigoltasuBICPstlaH
14,732LDDVRWPV5.2yllanimon,stuptuoUPCrofrewoP
83,432LDNGRWP.stuptuoUPCrofdnuorG
04,93,63,53)0:3(KLCUPCTUOV5.2@stuptuokcolctsoHdnaUPC
24C/N- detcennocyllanretnitoN
341LDNGRWPstuptuoCIPAOIrofdnuorG
54,44)1:0(CIPAOITUOV5.2@)zHM813.41(stuptuoCIPAOI
641LDDVRWPV5.2yllanimon,stuptuoCIPAOIrofrewoP
841DDVRWPV3.3lanimon,2X,1X,)2:0(FERrofylppuS
Page 3
3
ICS9148-10
T echnical Pin Function Descriptions
VDD(1,2,3)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:2),
PCICLK_F, PCICLK (0:6), 48MHz0, 48MHz1.
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
VDDL1,2
This is the power supply for the CPUCLK (0:3) and IOAPIC
output buffers. The voltage level for these outputs may be
2.5 or 3.3volts. Clocks from the buffers that each supplies will
have a voltage swing from Ground to this level. For the actual
Guaranteed high and low voltage levels of these Clocks,
please consult the DC parameter table in this Data Sheet.
GND (1,2,3)
This is the ground to the internal core logic of the device as
well as the clock output buffers for REF(0:2), PCICLK_F,
PCICLK (0:6), 48MHz 0, 48MHz1.
GNDL (1,2)
This is the ground for the CPUCLK (0:3) and IOAPIC output
buffers.
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. With a nominal value of 33pF no
external load cap is needed for a CL=17 to 18pF crystal.
X2
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor nominally 33pF.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks is controlled by the Voltage level
applied to the VDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
48MHz (0:1)
This is a fixed frequency Clock output that is typically used
to drive Super I/O devices. Outputs 0 and 1 are defined as
48MHz.
IOAPIC (0:1)
This Output is a fixed frequency Output Clock that runs at
the Reference Input (typically 14.31818MHz) . Its voltage
level swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
REF(0:2)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and X2.
PCICLK_F
This Output is equal to PCICLK(0:6) and is FREE RUNNING,
and will not be stopped by PCI_STOP#.
PCICLK (0:6)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the current
PCI specification. They run at 33.3 MHz.
SELECT 100/66.6MHz#
This Input pin controls the frequency of the Clocks at the
CPUCLK, PCICLK and SDRAM output pins. If a logic 1
value is present on this pin, the 100MHz Clock will be selected.
If a logic 0 is used, the 66.6MHz frequency will be selected.
The PCI clock is multiplexed to be 33.3MHz for both select
cases. PCI is synchronous at the rising edge of PCI to the
CPU rising edge (with the skew making CPU early).
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms.
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks.
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not affect
PCICLK_F nor any other outputs.
Page 4
4
ICS9148-10
Power Management
ICS9148-10 Power Management Requirements
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF and IOAPIC will be stopped independent of these.
LANGISETATSLANGIS
ycnetaL
eerffosegdegnisirfo.oN
KLCICPgninnur
#POTS_UPC)delbasiD(0
2
1
)delbanE(1
1
1
#POTS_ICP)delbasiD(0
2
1
)delbanE(1
1
1
#DP)noitarepOlamroN(1
3
sm3
)nwoDrewoP(0
4
xam2
-OTS_UPC
#P
#POTS_ICP
-NWD_RWP
#
KLCUPCKLCICP
rehtO
,skcolC
,FER
,sCIPAOI
0zHM84
1zHM84
latsyrCsOCV
XX 0 woLwoLdeppotSffOffO
00 1 woLwoLgninnuRgninnuRgninnuR
011 woLzHM3.33gninnuRgninnuRgninnuR
10 1
-HM6.66/001
z
woLgninnuRgninnuRgninnuR
111
-HM6.66/001
z
zHM3.33gninnuRgninnuRgninnuR
Page 5
5
ICS9148-10
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-10. It is used to turn off the PCICLK (0:6) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-10 internally. The minimum that the PCICLK (0:6) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:6) clocks. PCICLK (0:6) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:6) clock on latency cycles are only one rising PCICLK. Clock off latency is one PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9148-10. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-10.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148-10.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
Page 6
6
ICS9148-10
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9148-10 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power
on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
Page 7
7
ICS9148-10
Elect rical Characterist i cs - I nput / S uppl y/ Com m on Out put Paramet ers
TA = 0 - 70C; Supply Voltage VDD = V
DDL
= 3. 3 V +/- 5% (unless othe r wise sta te d)
PARA METER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltag e V
IH
2V
DD
+0.3 V
Input L ow Voltage V
IL
VSS-0.3 0.8 V
Inpu t High Current I
IH
VIN = V
DD
0.1 5
µ
A
Input Low Current I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5 2.0
µ
A
Input Low Current I
IL2
VIN = 0 V; Inputs with pull-up resistors -200 -100
µ
A
Operating I
DD3.3OP66CL
= Loaded at Cm a x p F; Select @ 66MHz 74 170 mA
Supply C urrent I
D D3.3OP100CL
= Loaded at Cm a x p F; Select @ 100MHz 79 170 mA
Power Down I
DD3.3PD
CL = Loaded at Cm a x pF; With input address to Vdd o3 500
µ
A
Supply C urrent
Input frequen cy F
i
VDD = 3.3 V; 14.318 MHz
Input C a pa c ita nc e
1
C
IN
Logic Inputs 5 pF
C
INX
X 1 & X2 pins 27 36 45 pF
Tr ans ition Time
1
T
trans
To 1s t c rossing of target Freq. 3 ms
Se ttling T im e
1
T
s
From 1st c rossing to 1% target Freq. 5 ms
Clk S ta biliz a tion
1
T
STA B
From VDD = 3. 3 V to 1% target Freq. 3 m s
Skew
1
T
CPU-PCI1VT
= 1.5 V;
1.5 3 4 ns
1
G uaranteed by design, not 100% te sted in production.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteri stics - Input/Supply/Common Out put Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% ( unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TY P MAX UNITS
Operating I
DD2.5OP66
CL = 20 pF; Select @ 66.8 MHz 28 70 mA
Supply Current I
DD2.5OP100CL
= pF; Select @ 100 MHz 43 100 mA
Skew
1
t
CPU-PCI2
VT = 1.5 V; VTL = 1.25 V
1.5 3 4 ns
1
Guar a nt eed by de sign, not 100% tested in production.
Page 8
8
ICS9148-10
Ele ctri ca l Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stat ed)
PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS
O ut put Impedance R
DSP2B
1
VO = VDD*(0.5) 13.5 45
Ω
O ut put Impedance R
DSN2B
1
VO = VDD*(0.5) 13.5 45
Ω
O utput High Voltage V
OH2BIOH
= -12.0 mA 2 2.3 V
Output Low Voltage V
OL2BIOL
= 12 mA 0.2 0.4 V
Ou t put Hig h Current I
OH2B
VOH = 1.7 V -41 -19 mA
Output Low Current I
OL2B
VOL = 0.7 V 19 37 mA
Rise Time t
r2B
1
VOL = 0.4 V, VOH = 2.0 V 1.25 1.6 ns
Fall Time t
f2B
1
VOH = 2.0 V, VOL = 0.4 V 1 1.6 ns
Duty Cycle d
t2B
1
VT = 1.25 V 45 48 55 %
Skew t
sk2B
1
VT = 1.25 V 30 175 ps
Jitter, Cycle-to-cycl e t
jcyc-cyc2B
1
VT = 1.25 V 150 250 ps
Jitter, One Sigma t
j1s2B
1
VT = 1.25 V 40 150 ps
Jitter, Absolute
t
jabs2B
1
VT = 1.25 V
-250 140 +250 ps
1
Guar a nt eed by design, not 100% tested in production.
Ele ctrical C haracteristics - I O APIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; CL = 20 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance
1
R
DSP4B
VO = VDD*(0.5) 13.5 45 Ohm
Output Impedance
1
R
DSN4B
VO = VDD*(0.5) 13.5 45 Ohm
Output High Voltage V
OH4BIOH
= -18 mA 2 2.2 V
Output Low Voltage V
OL4B
IOL = 18 mA 0.33 0.4 V
Ou tput High Current I
OH4B
VOH = 1.7 V -41 -28 m A
O ut put Low Current I
OL4B
VOL = 0.7 V 29 37 mA
Rise Time
1
T
r4B
VOL = 0.4 V , VOH = 2.0 V 1.3 1.6 ns
Fall Time
1
T
f4B
VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns
Duty Cycle
1
D
t4B
VT = 1.25 V 45 54 55 %
Skew
1
t
sk4B
1
VT = 1.25 V 60 250 ps
Jitter, One Sigma
1
T
j1s4B
VT = 1.25 V 1 3 %
Jitter, Absolute
1
T
jabs4B
VT = 1.25 V
-5 5 %
1
Guar a n t e ed by desi g n, not 100% t ested in production.
Page 9
9
ICS9148-10
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = V
DDL
= 3.3 V +/-5%; CL = 30 pF
PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS
O utput Imp eda nce
1
R
DSP1
VO = VDD*(0.5) 12 55 Ohm
O utput Imp eda nce
1
R
DSN1
VO = VDD*(0.5) 12 55 Ohm
O utput High Voltage V
OH1
IOH = -11 mA 2.4 3.1 V
Output Low Voltage V
OL1
IOL = 9.4 mA 0.1 0.4 V
Ou t put Hig h Current I
OH1
VOH = 2.0 V -62 -22 mA
Output Low Current I
OL1
VOL = 0.8 V 16 57 mA
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 1.5 2 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 50 55 %
Skew
1
t
sk1
VT = 1.5 V 140 500 ps
Jitter, One Sigma
1
t
j1s1
VT = 1.5 V 17 150 ps
Jitter, Absolute
1
t
jabs1
VT = 1.5 V
-500 70 500 ps
1
Guar a nt eed by design, not 100% tested in production.
Ele ctrical C haracteristics - REF
TA = 0 - 70C; VDD = V
DDL
= 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS
O utput Imp eda nce
1
R
DSP5
VO = VDD*(0.5) 13.5 45 Ohm
O utput Imp eda nce
1
R
DSN5
VO = VDD*(0.5) 13.5 45 Ohm
O utput High Voltage V
OH5
IOH = -16 mA 2.4 3.1 V
Output Low Voltage V
OL5
IOL = 9 mA 0.17 0.4 V
Ou t put Hig h Current I
OH5
VOH = 2.0 V -44 -22 mA
Output Low Current I
OL5
VOL = 0.8 V 29 42 mA
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 1.4 2 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns
Duty Cycle
1
d
t5
VT = 1.5 V 45 53 55 %
Jitter, One Sigma
1
t
j1s5
VT = 1.5 V 1 3 %
Jitter, Absolute
1
t
jabs5
VT = 1.5 V
35%
1
Guar a nt eed by design, not 100% tested in production.
Page 10
10
ICS9148-10
Ele ctrical C haracteristics - 48 MHz
TA = 0 - 70C; VDD = V
DDL
= 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SY MBOL CONDITIONS MIN TYP MAX UNITS
Fr equency Accuracy
1
F
ACC48m
167 ppm
O utput Imp eda nce
1
R
DSP5
VO = VDD*(0.5) 20 60 Ohm
O utput Imp eda nce
1
R
DSN5
VO = VDD*(0.5) 20 60 Ohm
O utput High Voltage V
OH5
IOH = -16 mA 2.4 3 V
Output Low Voltage V
OL5
IOL = 9 mA 0.14 0.4 V
Ou t put Hig h Current I
OH5
VOH = 2.0 V -44 -22 mA
Output Low Current I
OL5
VOL = 0.8 V 16 42 mA
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 1.2 4 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 1.2 4 ns
Duty Cycle
1
d
t5
VT = 1.5 V 45 52 55 %
Jitter, One Sigma
1
t
j1s5
VT = 1.5 V 1 3 %
Jitter, Absolute
1
t
jabs5
VT = 1.5 V
35%
1
Guar a nt eed by design, not 100% tested in production.
Page 11
11
ICS9148-10
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
Capacitor Values:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Page 12
12
ICS9148-10
This table in inches
SSOP Package
LOBMYS SNOISNEMIDNOMMOC SNOITAIRAV D N
.NIM.MON.XAM.NIM.MON.XAM
A590.101.011.CA026.526.036.84
1A800.210.610.DA027.527.037.65
2A880.090.290.
B800.010.5310.
C500.600.5800.
DsnoitairaVeeS
E292.692.992.
eCSB520.0
H004.604.014.
h010.310.610.
L420.230.040.
NsnoitairaVeeS
µ
°0°5°8
X580.390.001.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
Ordering Information
ICS9148yF-10
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP
Loading...