Page 1
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9112-16
Block Diagram
Low Skew Output Buffer
9112-16 Rev F 10/20/00
Pin Configuration
• Zero input - output delay
• Frequency range 25 - 133 MHz (3.3V)
• High loop filter bandwidth ideal for Spread
Spectrum applications.
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 pin 150 mil SOIC
or 173 mil TSSOP package.
• 3.3V ±10% operation
The ICS9112-16 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the REF input with the
CLKOUT signal. It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
133 MHz.
ICS9112-16 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to the
input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS9112-16 comes in an eight pin 150 mil SOIC or 173
mil TSSOP package. It has five output clocks. In the absence
of REF input, will be in the power down mode. In this mode,
the PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
8 pin SOIC, TSSOP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Page 2
2
ICS9112-16
Pin Descriptions
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. Weak pull-down
3. Weak pull-down on all outputs
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1FER
2
NI.ycneuqerfecnerefertupnI
22KLC
3
TUOtuptuokcolcdereffuB
31KLC
3
TUOtuptuokcolcdereffuB
4DNGRWPdnuorG
53KLC
3
TUOtuptuokcolcdereffuB
6DDVRWP)V3.3(ylppuSrewoP
74KLC
3
TUOtuptuokcolcdereffuB
8TUOKLC
3
TUOnipsihtnokcabdeeflanretnI.tuptuokcolcdereffuB
Page 3
3
ICS9112-16
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. All Skew specifications are mesured with a 50W transmission line, load teminated with 50W to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.6 V, TA = 0 – 70° C unless otherwise stated
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
scitsiretcarahCCD
RETEMARAPLOBMYSSNOITIDNOCTSETNIMPYTXAMSTINU
egatloVwoLtupnI
V
LI
8.0V
egatloVhgiHtupnI
V
HI
0.2V
tnerruCwoLtupnI
I
LI
VNIV0=910.05Aµ
tnerruChgiHtupnI
I
HI
VNIV=
DD
01.00.001Aµ
egatloVwoLtuptuO
1
V
LO
I
LO
Am52=52.04.0V
egatloVhgiHtuptuO
1
V
HO
I
HO
Am52=4.29.2V
ylppuSnwoDrewoP
tnerruC
I
DD
zHM0=FER3.00.05Aµ
tnerruCylppuS
I
DD
LESzHM66.66tastutuodedaolnU
Vtastupni
DD
DNGro
0.030.04Am
Page 4
4
ICS9112-16
Switching Characteristics
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
RETEMARAPLOBMYSNOITIDNOCNIMPYTXAMSTINU
doireptuptuO1tFp03=LChtiW
00.04
)52(
01
)331(
sn
)zHM(
doireptupnI1tFp03=LChtiW
00.04
)52(
01
)331(
sn
)zHM(
elcyCytuD
1
1tDFp03=LC;V4.1taderusaeM0.040506%
elcyCytuD
1
2tDzHM6.66<tuoF2/DDVtaderusaeM540555%
emiTesiR
1
1rt
:V0.2dnaV8.0neewtebderusaeM
Fp03=LC
2.15.1sn
emiTllaF
1
1ft
;V8.0dnaV0.2neewtebderusaeM
Fp03=LC
2.15.1sn
gnisiRFER,yaleD
TUOKLCotegdE
egdEgnisiR
,12
1rDV4.1taderusaeM0053±sp
tuptuOottuptuO
wekS
1
weksTFp02=LC,dedaolyllauqestuptuollA052sp
eciveDoteciveD
wekS
1
ksdT-ksdT
TUOKLCehtno2/DDVtaderusaeM
secivedfosnip
0007sp
rettiJelcyCotelcyC
1
cycT-cycT
dedaol,zHM66.66taderusaeM
stuptuo
002sp
emiTkcoLLLP
1
KCOLt
kcolcdilav,ylppusrewopelbatS
nipFERnodetneserp
0.1sm
rettiJetulosbA;rettiJ
1
sbajT
selcyc000,01@
Fp03=LC
001-07001sp
amgiS-1;rettiJ
1
s1jT
selcyc000,01@
Fp03=LC
4103sp
Page 5
5
ICS9112-16
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the
inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase
difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than
CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to
have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded
Equally
REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
Page 6
6
ICS9112-16
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS XXXX y M - PPP - T
Ordering Information
ICS9112yM-16-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
150 mil (Narrow Body) SOIC
MIN MAX MIN MAX
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.33 0.51 .013 .020
C 0.19 0.25 .0075 .0098
D
E 3.80 4.0 .1497 .1574
e
H 5.80 6.20 .2284 .2440
h 0.25 0.50 .010 .020
L 0.40 1.27 .016 .050
N
α
0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
84.80
5.00
.1890 .1968
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
1.27 BASIC 0.050 BASIC
N
D mm.
D (inch)
SEE VARIATIONS
Page 7
7
ICS9112-16
Ordering Information
ICS9112yG-16-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - PPP - T
4.40 mm. Body, 0.65 mm. pitch TSSOP
(173 mil)
(0.0256 mil)
MIN MAX MIN MAX
A - 1.20 - .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.19 0.30 .007 .012
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e 0.65 BASIC 0.0256 BASIC
L 0.45 0.75 .018 .030
N
α
0° 8° 0° 8°
aaa - 0.10 - .004
VARIATIONS
MIN MAX MIN MAX
82.90
3.10
.114 .122
MO-153 JEDEC
Doc.# 10-0038
7/6/00 Rev B
N
D mm.
D (inch)
SEE VARIATIONS
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
6.40 BASIC 0.252 BASIC
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