Datasheet ATtiny4, ATtiny5, ATtiny9, ATtiny10 Datasheet
ATtiny4/5/9/10
tinyAVR® Data Sheet
Introduction
The ATtiny4/5/9/10 is a low power, CMOS 8-bit microcontrollers based on the AVR® enhanced RISC architecture. The ATtiny4/5/9/10 is a 6/8-pins device ranging from 512 Bytes to 1024 Bytes Flash, with 32 Bytes
SRAM. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching
one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power
consumption versus processing speed.
Features
• High Performance, Low Power AVR
®
8-Bit Microcontroller
• Advanced RISC Architecture
– 54 Powerful Instructions – Most Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12 MHz
• Non-volatile Program and Data Memories
– 512/1024 Bytes of In-System Programmable Flash Program Memory
– 32 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85C / 100 Years at 25C
• Peripheral Features
–QTouch
– One 16-bit Timer/Counter with Prescaler and Two PWM Channels
– Programmable Watchdog Timer with Separate On-chip Oscillator
– 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only)
– On-chip Analog Comparator
®
Library Support for Capacitive Touch Sensing (1 Channel)
• Special Microcontroller Features
– In-System Programmable (at 5V, only)
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Supply Voltage Level Monitor with Interrupt and Reset
– Internal Calibrated Oscillator
• I/O and Packages
– Four Programmable I/O Lines
– 6-pin SOT and 8-pad UDFN
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• Operating Voltage:
– 1.8 – 5.5V
• Programming Voltage:
–5V
• Speed Grade
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
• Industrial and Extended Temperature Ranges
• Low Power Consumption
– Active Mode:
• 200µA at 1MHz and 1.8V
– Idle Mode:
• 25µA at 1MHz and 1.8V
– Power-down Mode:
• < 0.1µA at 1.8V
ATtiny4/5/9/10
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Table Of Contents
1 Pin Configurations ................................................................................... 8
1.1 Pin Description .................................................................................................. 8
2 Ordering Information ............................................................................... 9
2.1 ATtiny4 .............................................................................................................. 9
2.2 ATtiny5 ............................................................................................................ 10
2.3 ATtiny9 ............................................................................................................ 11
2.4 ATtiny10 .......................................................................................................... 12
3 Overview ................................................................................................. 13
3.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 ................................. 14
4 General Information ............................................................................... 15
4.1 Resources ....................................................................................................... 15
ATtiny4/5/9/10
4.2 Code Examples ............................................................................................... 15
4.3 Capacitive Touch Sensing............................................................................... 15
4.4 Data Retention................................................................................................. 15
5 CPU Core ................................................................................................ 16
5.1 Architectural Overview..................................................................................... 16
5.2 ALU – Arithmetic Logic Unit............................................................................. 17
5.3 Status Register ................................................................................................ 17
5.4 General Purpose Register File ........................................................................ 17
5.5 Stack Pointer ................................................................................................... 19
5.6 Instruction Execution Timing ........................................................................... 19
5.7 Reset and Interrupt Handling........................................................................... 20
5.8 Register Description ........................................................................................ 21
6 Memories ................................................................................................ 24
6.1 In-System Re-programmable Flash Program Memory.................................... 24
6.2 Data Memory ................................................................................................... 24
6.3 I/O Memory...................................................................................................... 26
7 Clock System .......................................................................................... 27
7.1 Clock Subsystems ........................................................................................... 27
7.2 Clock Sources ................................................................................................. 28
7.3 System Clock Prescaler .................................................................................. 29
7.4 Starting ............................................................................................................ 30
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7.5 Register Description ........................................................................................ 30
8 Power Management and Sleep Modes ................................................. 32
8.1 Sleep Modes.................................................................................................... 33
8.2 Power Reduction Register............................................................................... 34
8.3 Minimizing Power Consumption ...................................................................... 34
8.4 Register Description ........................................................................................ 35
9 System Control and Reset .................................................................... 37
9.1 Resetting the AVR ........................................................................................... 37
9.2 Reset Sources ................................................................................................. 37
9.3 Watchdog Timer .............................................................................................. 40
9.4 Register Description ........................................................................................ 42
10 Interrupts ................................................................................................ 45
10.1 Interrupt Vectors .............................................................................................. 45
ATtiny4/5/9/10
10.2 External Interrupts ........................................................................................... 46
10.3 Register Description ........................................................................................ 47
11 I/O Ports .................................................................................................. 50
11.1 Overview.......................................................................................................... 50
11.2 Ports as General Digital I/O............................................................................. 51
11.3 Alternate Port Functions .................................................................................. 55
11.4 Register Description ........................................................................................ 60
12 16-bit Timer/Counter0 ............................................................................ 62
12.1 Features .......................................................................................................... 62
12.2 Overview.......................................................................................................... 62
12.3 Clock Sources ................................................................................................. 63
12.4 Counter Unit .................................................................................................... 65
12.5 Input Capture Unit ........................................................................................... 66
12.6 Output Compare Units..................................................................................... 68
12.7 Compare Match Output Unit............................................................................ 70
12.8 Modes of Operation ......................................................................................... 71
12.9 Timer/Counter Timing Diagrams ..................................................................... 78
12.10 Accessing 16-bit Registers .............................................................................. 79
12.11 Register Description ........................................................................................ 81
13 Analog Comparator ................................................................................ 89
13.1 Register Description ........................................................................................ 89
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14 Analog to Digital Converter ................................................................... 91
14.1 Features .......................................................................................................... 91
14.2 Overview.......................................................................................................... 91
14.3 Operation......................................................................................................... 91
14.4 Starting a Conversion ...................................................................................... 92
14.5 Prescaling and Conversion Timing.................................................................. 93
14.6 Changing Channel........................................................................................... 96
14.7 ADC Noise Canceler ....................................................................................... 96
14.8 Analog Input Circuitry ...................................................................................... 97
14.9 Noise Canceling Techniques........................................................................... 97
14.10 ADC Accuracy Definitions ............................................................................... 98
14.11 ADC Conversion Result................................................................................. 100
14.12 Register Description ...................................................................................... 101
15 Programming interface ........................................................................ 104
ATtiny4/5/9/10
15.1 Features ........................................................................................................ 104
15.2 Overview........................................................................................................ 104
15.3 Physical Layer of Tiny Programming Interface.............................................. 104
15.4 Access Layer of Tiny Programming Interface................................................ 108
15.5 Instruction Set................................................................................................ 109
15.6 Accessing the Non-Volatile Memory Controller ............................................. 112
15.7 Control and Status Space Register Descriptions .......................................... 112
16 Memory Programming ......................................................................... 115
16.1 Features ........................................................................................................ 115
16.2 Overview........................................................................................................ 115
16.3 Non-Volatile Memories .................................................................................. 115
16.4 Accessing the NVM ....................................................................................... 118
16.5 Self programming .......................................................................................... 121
16.6 External Programming................................................................................... 121
16.7 Register Description ...................................................................................... 123
17 Electrical Characteristics .................................................................... 124
17.1 Absolute Maximum Ratings* ......................................................................... 124
17.2 DC Characteristics......................................................................................... 124
17.3 Speed ............................................................................................................ 125
17.4 Clock Characteristics..................................................................................... 126
17.5 System and Reset Characteristics ................................................................ 127
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17.6 Analog Comparator Characteristics............................................................... 128
17.7 ADC Characteristics (ATtiny5/10, only) ......................................................... 128
17.8 Serial Programming Characteristics .............................................................. 129
18 Typical Characteristics ........................................................................ 130
18.1 Supply Current of I/O Modules ...................................................................... 130
18.2 Active Supply Current.................................................................................... 131
18.3 Idle Supply Current........................................................................................ 134
18.4 Power-down Supply Current.......................................................................... 136
18.5 Pin Pull-up ..................................................................................................... 137
18.6 Pin Driver Strength ........................................................................................ 140
18.7 Pin Threshold and Hysteresis........................................................................ 144
18.8 Analog Comparator Offset............................................................................. 148
18.9 Internal Oscillator Speed ............................................................................... 149
18.10 VLM Thresholds ............................................................................................ 151
ATtiny4/5/9/10
18.11 Current Consumption of Peripheral Units...................................................... 153
18.12 Current Consumption in Reset and Reset Pulsewidth .................................. 156
19 Register Summary ............................................................................... 157
20 Instruction Set Summary ..................................................................... 159
21 Packaging Information ........................................................................ 161
21.1 6ST1 .............................................................................................................. 161
21.2 8MA4 ............................................................................................................. 162
22 Errata ..................................................................................................... 163
22.1 ATtiny4 .......................................................................................................... 163
22.2 ATtiny5 .......................................................................................................... 164
22.3 ATtiny9 .......................................................................................................... 165
22.4 ATtiny10 ........................................................................................................ 166
23 Datasheet Revision History ................................................................. 167
23.1 Rev. A – 08/2018........................................................................................... 167
23.2 Rev. 8127H – 11/2016................................................................................... 167
23.3 Rev. 8127G – 09/2015 .................................................................................. 167
23.4 Rev. 8127F – 02/2013 ................................................................................... 168
23.5 Rev. 8127E – 11/11....................................................................................... 168
23.6 Rev. 8127D – 02/10....................................................................................... 168
23.7 Rev. 8127C – 10/09....................................................................................... 168
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23.8 Rev. 8127B – 08/09....................................................................................... 168
23.9 Rev. 8127A – 04/09....................................................................................... 169
ATtiny4/5/9/10
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1. Pin Configurations
Figure 1-1. Pinout of ATtiny4/5/9/10
(PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
GND
NC
NC
GND
SOT-23
1
2
3
UDFN
1
2
3
4
ATtiny4/5/9/10
6
PB3 (RESET/PCINT3/ADC3)
5
VCC
4
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
8
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
7
VCC
6
PB3 (RESET/PCINT3/ADC3)
5
PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0)
1.1 Pin Description
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB3..PB0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers
have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally
pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on page 46.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 17-4 on page 127.
Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
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2. Ordering Information
2.1 ATtiny4
12 MHz
10 MHz
(1)
Temperature Package
Industrial
(-40C to 85C)
Extended
(-40C to 125C)
(4)
(6)
Supply Voltage Speed
1.8 – 5.5V
Notes: 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.
3. Tape and reel.
4. Can also be supplied in wafer form. Contact your local Microchip sales office for ordering information and minimum
quantities.
5. Top/bottomside markings:
– Top: T4x, where x = die revision
–Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C)
6. For typical and Electrical characteristics for this device consult Appendix A, ATtiny4/5/9/10 Specification at 125°C on
www.microchip.com
ATtiny4/5/9/10
(2)
Ordering Code
6ST1 ATtiny4-TSHR
8MA4 ATtiny4-MAHR
6ST1 ATtiny4-TS8R
(3)
(5)
(6)
(5)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
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2.2 ATtiny5
12 MHz
10 MHz
(1)
Temperature Package
Industrial
(-40C to 85C)
Extended
(-40C to 125C)
(4)
(6)
Supply Voltage Speed
1.8 – 5.5V
Notes: 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.
3. Tape and reel.
4. Can also be supplied in wafer form. Contact your local Microchip sales office for ordering information and minimum
quantities.
5. Top/bottomside markings:
– Top: T5x, where x = die revision
–Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C)
6. For typical and Electrical characteristics for this device consult Appendix A, ATtiny4/5/9/10 Specification at 125°C on
www.microchip.com
ATtiny4/5/9/10
(2)
Ordering Code
6ST1 ATtiny5-TSHR
8MA4 ATtiny5-MAHR
6ST1 ATtiny5-TS8R
(3)
(5)
(6)
(5)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
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2.3 ATtiny9
12 MHz
10 MHz
(1)
Temperature Package
Industrial
(-40C to 85C)
Extended
(-40C to 125C)
(4)
(6)
Supply Voltage Speed
1.8 – 5.5V
Notes: 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.
3. Tape and reel.
4. Can also be supplied in wafer form. Contact your local Microchip sales office for ordering information and minimum
quantities.
5. Top/bottomside markings:
– Top: T9x, where x = die revision
–Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C)
6. For typical and Electrical characteristics for this device consult Appendix A, ATtiny4/5/9/10 Specification at 125°C on
www.microchip.com
ATtiny4/5/9/10
(2)
Ordering Code
6ST1 ATtiny9-TSHR
8MA4 ATtiny9-MAHR
6ST1 ATtiny9-TS8R
(5)
(5)
(6)
(3)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
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2.4 ATtiny10
12 MHz
10 MHz
(1)
Temperature Package
Industrial
(-40C to 85C)
Extended
(-40C to 125C)
(4)
(6)
Supply Voltage Speed
1.8 – 5.5V
Notes: 1. For speed vs. supply voltage, see section 17.3 “Speed” on page 125.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.
3. Tape and reel.
4. Can also be supplied in wafer form. Contact your local Microchip sales office for ordering information and minimum
quantities.
5. Top/bottom side markings:
– Top: T10x, where x = die revision
–Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C)
6. For typical and Electrical characteristics for this device consult Appendix A, ATtiny4/5/9/10 Specification at 125°C on
www.microchip.com
ATtiny4/5/9/10
(2)
Ordering Code
6ST1 ATtiny10-TSHR
8MA4 ATtiny10-MAHR
6ST1 ATtiny10-TS8R
(3)
(5)
(6)
(5)
Package Type
6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)
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ATtiny4/5/9/10
3. Overview
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per
MHz, allowing the system designer to optimize power consumption versus processing speed.
Figure 3-1. Block Diagram
V
CC
RESET
PROGRAMMING
LOGIC
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
ISP
INTERFACE
PROGRAM
COUNTER
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
RESET FLAG
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
INTERRUPT
8-BIT DATA BUS
UNIT
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
DATA REGISTER
PORT B
DRIVERS
PORT B
PB3:0
DIRECTION
REG. PORT B
GND
ANALOG
COMPARATOR
ADC
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers
are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single
instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of SRAM,
four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and
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ATtiny4/5/9/10
four software selectable power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog to Digital
Converter (ADC).
Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by
stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip
functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of
the device is sleeping, allowing very fast start-up combined with low power consumption.
The device is manufactured using high density non-volatile memory technology. The on-chip, in-system programmable
Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer.
The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro assemblers
and evaluation kits.
3.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10
A comparison of the devices is shown in Table 3-1.
Table 3-1. Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10
Device Flash ADC Signature
ATtiny4 512 bytes No 0x1E 0x8F 0x0A
ATtiny5 512 bytes Yes 0x1E 0x8F 0x09
ATtiny9 1024 bytes No 0x1E 0x90 0x08
ATtiny10 1024 bytes Yes 0x1E 0x90 0x03
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ATtiny4/5/9/10
4. General Information
4.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for
download at www.microchip.com
4.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors
include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
4.3 Capacitive Touch Sensing
QTouch Library provides a simple to use solution for touch sensitive interfaces on AVR microcontrollers. The QTouch
Library includes support for QTouch
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming
Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor.
®
and QMatrix™ acquisition methods.
The QTouch Library is free and can be downloaded from the website. For more information and details of implementation,
refer to the QTouch Library User Guide – also available from the website.
4.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at
85°C or 100 years at 25°C.
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ATtiny4/5/9/10
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
16 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Tim er
Analog
Comparator
Timer/Counter 0
ADC
5. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
5.1 Architectural Overview
Figure 5-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System reprogrammable Flash memory.
The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the
Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables
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ATtiny4/5/9/10
in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this
section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the
whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The
actual instruction set varies, as some devices only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size and the usage
of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed).
The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the four
different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in
accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F.
5.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 159 for a detailed
description.
5.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is
updated after all ALU operations, as specified in document “AVR Instruction Set” and section “Instruction Set Summary” on
page 159. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an
interrupt. This must be handled by software.
5.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance
and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 5-2 below shows the structure of the 16 general purpose working registers in the CPU.
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ATtiny4/5/9/10
Figure 5-2. AVR CPU General Purpose Working Registers
70
R16
R17
General R18
Purpose …
Working R26 X-register Low Byte
Registers R27 X-register High Byte
R28 Y-register Low Byte
R29 Y-register High Byte
R30 Z-register Low Byte
R31 Z-register High Byte
Note: A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement only 16
registers. For reasons of compatibility the registers are numbered R16...R31, not R0...R15.
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle
instructions.
5.4.1 The X-register, Y-register, and Z-register
Registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in
Figure 5-3.
Figure 5-3. The X-, Y-, and Z-registers
15 XH XL 0
X-register 707 0
R27 R26
15 YH YL 0
Y-register 707 0
R29 R28
15 ZH ZL 0
Z-register 707 0
R31 R30
In different addressing modes these address registers function as automatic increment and automatic decrement (see document “AVR Instruction Set” and section “Instruction Set Summary” on page 159 for details).
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clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
5.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is
implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are
enabled. The Stack Pointer must be set to point above 0x40. The Stack Pointer is decremented by one when data is
pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the
Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with
the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL
is needed. In this case, the SPH Register will not be present.
5.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU
clock clk
, directly generated from the selected clock source for the chip. No internal clock division is used.
CPU
Figure 5-4. The Parallel Instruction Fetches and Instruction Executions
Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two regis-
ter operands is executed, and the result is stored back to the destination register.
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Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
Figure 5-5. Single Cycle ALU Operation
5.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space. All interrupts are assigned individual enable bits which must be written
logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45. The list also determines the priority levels of the different interrupts.
The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can
write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these
interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine,
and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag
bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be
set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before
any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning
from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
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When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
Note: See “Code Examples” on page 15.
5.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the
Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three
clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the
interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter
(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
5.8 Register Description
5.8.1 CCP – Configuration Change Protection Register
Bit 76543210
0x3C CCP[7:0] CCP
Read/Write WWWWWWWR/W
Initial Value00000000
• Bits 7:0 – CCP[7:0] – Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct signature.
After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles. All interrupts
are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU, and any pending
interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is enabled,
while CCP[7:1] will always read as zero.
Table 5-1 shows the signatures that are in recognised.
Table 5-1. Signatures Recognised by the Configuration Change Protection Register
Signature Group Description
0xD8 IOREG: CLKMSR, CLKPSR, WDTCSR Protected I/O register
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5.8.2 SPH and SPL — Stack Pointer Register
Bit 151413121110 9 8
0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value
Initial Value
5.8.3 SREG – Status Register
Bit 76543210
0x3F ITHSVNZCSREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then
performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are
enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the
application with the SEI and CLI instructions, as described in the document “AVR Instruction Set” and “Instruction Set Sum-
mary” on page 159.
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A
bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in
a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 159 for detailed information.
• Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 159 for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See document “AVR Instruction Set” and
section “Instruction Set Summary” on page 159 for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See document “AVR Instruction Set”
and section “Instruction Set Summary” on page 159 for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR Instruction Set” and section
“Instruction Set Summary” on page 159 for detailed information.
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• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and section
“Instruction Set Summary” on page 159 for detailed information.
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6. Memories
This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the program
memory space and the data memory space.
6.1 In-System Re-programmable Flash Program Memory
The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash memory for program storage.
Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny4/5/9/10 Program Counter (PC) is 9
bits wide, thus capable of addressing the 256/512 program memory locations, starting at 0x000. “Memory Programming”
on page 115 contains a detailed description on Flash data serial downloading.
Constant tables can be allocated within the entire address space of program memory. Since program memory can not be
accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte address 0x4000
in data memory (see Figure 6-1 on page 25). Although programs are executed starting from address 0x000 in program
memory it must be addressed starting from 0x4000 when accessed via the data memory.
Internal write operations to Flash program memory have been disabled and program memory therefore appears to firmware as read-only. Flash memory can still be written to externally but internal write operations to the program memory area
will not be succesful.
Timing diagrams of instruction fetch and execution are presented in “Instruction Execution Timing” on page 19.
6.2 Data Memory
Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile memory lock bits, and the
Flash memory. See Figure 6-1 on page 25 for an illustration on how the ATtiny4/5/9/10 memory space is organized.
The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address the internal data
SRAM.
The non-volatile memory lock bits and all the Flash memory sections are mapped to the data memory space. These locations appear as read-only for device firmware.
The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect with
post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing.
The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS instructions reaches the 128 locations between 0x0040 and 0x00BF.
The indirect addressing reaches the entire data memory space. When using indirect addressing modes with automatic predecrement and post-increment, the address registers X, Y, and Z are decremented or incremented.
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Figure 6-1. Data Memory Map (Byte Addressing)
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
ATtiny4/5/9/10
I/O SPACE
SRAM DATA MEMORY
(reserved)
NVM LOCK BITS
(reserved)
CONFIGURATION BITS
(reserved)
CALIBRATION BITS
(reserved)
DEVICE ID BITS
(reserved)
FLASH PROGRAM MEMORY
(reserved)
0x0000 ... 0x003F
0x0040 ... 0x005F
0x0060 ... 0x3EFF
0x3F00 ... 0x3F01
0x3F02 ... 0x3F3F
0x3F40 ... 0x3F41
0x3F42 ... 0x3F7F
0x3F80 ... 0x3F81
0x3F82 ... 0x3FBF
0x3FC0 ... 0x3FC3
0x3FC4 ... 0x3FFF
0x4000 ... 0x41FF/0x43FF
0x4400 ... 0xFFFF
6.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM access is
performed in two clk
cycles as described in Figure 6-2.
CPU
Figure 6-2. On-chip Data SRAM Access Cycles
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6.3 I/O Memory
The I/O space definition of the ATtiny4/5/9/10 is shown in “Register Summary” on page 157.
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST
instructions, enabling data transfer between the 16 general purpose working registers and the I/O space. I/O Registers
within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 159 for more details. When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI instructions will only operate on
the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work on
registers in the address range 0x00 to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
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7. Clock System
Figure 7-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the clocks need not be active
at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 32.
The clock systems is detailed below.
Figure 7-1. Clock Distribution
ANALOG-TO-DIGITAL
CONVERTER
GENERAL
I/O MODULES
CPU
CORE
RAM
NVM
clk
ADC
CLOCK CONTROL UNIT
SOURCE CLOCK
CLOCK
PRESCALER
CLOCK
SWITCH
EXTERNAL
CLOCK
7.1 Clock Subsystems
The clock subsystems are detailed in the sections below.
clk
I/O
RESET
LOGIC
WATCHDOG
CLOCK
WATCHDOG
OSCILLATOR
clk
CPU
WATCHDOG
TIMER
clk
NVM
CALIBRATED
OSCILLATOR
7.1.1 CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR Core. Examples of such modules are
the General Purpose Register File, the System Registers and the SRAM data memory. Halting the CPU clock inhibits the
core from performing general operations and calculations.
7.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External
Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be
detected even if the I/O clock is halted.
7.1.3 NVM clock - clk
NVM
The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usually active simultaneously
with the CPU clock.
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EXTERNAL
CLOCK
SIGNAL
CLKI
GND
7.1.4 ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise
generated by digital circuitry. This gives more accurate ADC conversion results.
The ADC is available in ATtiny5/10, only.
7.2 Clock Sources
All synchronous clock signals are derived from the main clock. The device has three alternative sources for the main clock,
as follows:
• Calibrated Internal 8 MHz Oscillator (see page 28)
• External Clock (see page 28)
• Internal 128 kHz Oscillator (see page 28)
See Table 7-3 on page 31 on how to select and change the active clock source.
7.2.1 Calibrated Internal 8 MHz Oscillator
The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 17-2 on page 126, Figure 18-39 on page 150 and
Figure 18-40 on page 150 for more details.
This clock may be selected as the main clock by setting the Clock Main Select bits CLKMS[1:0] in CLKMSR to 0b00. Once
enabled, the oscillator will operate with no external components. During reset, hardware loads the calibration byte into the
OSCCAL register and thereby automatically calibrates the oscillator. The accuracy of this calibration is shown as Factory
calibration in Table 17-2 on page 126.
When this oscillator is used as the main clock, the watchdog oscillator will still be used for the watchdog timer and reset
time-out. For more information on the pre-programmed calibration value, see section “Calibration Section” on page 118.
7.2.2 External Clock
To use the device with an external clock source, CLKI should be driven as shown in Figure 7-2. The external clock is
selected as the main clock by setting CLKMS[1:0] bits in CLKMSR to 0b10.
Figure 7-2. External Clock Drive Configuration
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable
operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable
behavior. It is required to ensure that the MCU is kept in reset during such changes in the clock frequency.
7.2.3 Internal 128 kHz Oscillator
The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on supply
voltage, temperature and batch variations. This clock may be select as the main clock by setting the CLKMS[1:0] bits in
CLKMSR to 0b01.
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7.2.4 Switching Clock Source
The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page 30. When
switching between any clock sources, the clock system ensures that no glitch occurs in the main clock.
7.2.5 Default Clock Source
The calibrated internal 8 MHz oscillator is always selected as main clock when the device is powered up or has been reset.
The synchronous system clock is the main clock divided by 8, controlled by the System Clock Prescaler. The Clock Prescaler Select Bits can be written later to change the system clock frequency. See “System Clock Prescaler”.
7.3 System Clock Prescaler
The system clock is derived from the main clock via the System Clock Prescaler. The system clock can be divided by setting the “CLKPSR – Clock Prescale Register” on page 31. The system clock prescaler can be used to decrease power
consumption at times when requirements for processing power is low or to bring the system clock within limits of maximum
frequency. The prescaler can be used with all main clock source options, and it will affect the clock frequency of the CPU
and all synchronous peripherals.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring
stable operation.
7.3.1 Switching Prescaler Setting
When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system clock
and that no intermediate frequency is higher than neither the clock frequency corresponding the previous setting, nor the
clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than the
CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the
exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is
active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
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7.4 Starting
7.4.1 Starting from Reset
The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the
reset source is released and the start-up sequence is completed. The start-up sequence includes three steps, as follows.
1. The first step after the reset source has been released consists of the device counting the reset start-up time. The
purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels. The reset start-up
time is counted using the internal 128 kHz oscillator. See Table 7-1 for details of reset start-up time.
Note that the actual supply voltage is not monitored by the start-up logic. The device will count until the reset startup time has elapsed even if the device has reached sufficient supply voltage levels earlier.
2. The second step is to count the oscillator start-up time, which ensures that the calibrated internal oscillator has
reached a stable state before it is used by the other parts of the system. The calibrated internal oscillator needs to
oscillate for a minimum number of cycles before it can be considered stable. See Table 7-1 for details of the oscillator start-up time.
3. The last step before releasing the internal reset is to load the calibration and the configuration values from the
Non-Volatile Memory to configure the device properly. The configuration time is listed in Table 7-1.
Table 7-1. Start-up Times when Using the Internal Calibrated Oscillator
Reset Oscillator Configuration Total start-up time
64 ms 6 cycles 21 cycles 64 ms + 6 oscillator cycles + 21 system clock cycles
(1)
Notes: 1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscillator,
divided by 8
7.4.2 Starting from Power-Down Mode
When waking up from Power-Down sleep mode, the supply voltage is assumed to be at a sufficient level and only the oscillator start-up time is counted to ensure the stable operation of the oscillator. The oscillator start-up time is counted on the
selected main clock, and the start-up time depends on the clock selected. See Table 7-2 for details.
Table 7-2. Start-up Time from Power-Down Sleep Mode.
Oscillator start-up time Total start-up time
6 cycles 6 oscillator cycles
Notes: 1. The start-up time is measured in main clock oscillator cycles.
(1)
7.4.3 Starting from Idle / ADC Noise Reduction / Standby Mode
When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and no oscillator startup time is introduced.
The ADC is available in ATtiny5/10, only.
7.5 Register Description
7.5.1 CLKMSR – Clock Main Settings Register
Bit 765432 1 0
0x37
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
2018 Microchip Technology Inc. Data Sheet Complete DS40002060A-page 30
– – – – – – CLKMS1 CLKMS0 CLKMSR
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