ATtiny212/214/412/414/416
tinyAVR® 1-series
Introduction
The ATtiny212/214/412/414/416 are members of the tinyAVR®1-series of microcontrollers, using the AVR® processor
with hardware multiplier, running at up to 20 MHz, with 2/4 KB Flash, 128/256 bytes of SRAM, and 64/128 bytes of
EEPROM in a 8-, 14-, and 20-pin package. The tinyAVR®1-series uses the latest technologies with a flexible, lowpower architecture, including Event System, accurate analog features, and Core Independent Peripherals (CIPs).
Attention: Automotive products are documented in separate data sheets.
Features
• CPU
– AVR® CPU
– Running at up to 20 MHz
– Single-cycle I/O access
– Two-level interrupt controller
– Two-cycle hardware multiplier
• Memories
– 2/4 KB In-system self-programmable Flash memory
– 64/128 bytes EEPROM
– 128/256 bytes SRAM
– Write/erase endurance:
• Flash 10,000 cycles
• EEPROM 100,000 cycles
– Data retention:
• 40 years at 55°C
• System
– Power-on Reset (POR)
– Brown-out Detector (BOD)
– Clock options:
• 16/20 MHz low-power internal RC oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
• 32.768 kHz external crystal oscillator
• External clock input
– Single-Pin Unified Program and Debug Interface (UPDI)
– Three sleep modes:
• Idle with all peripherals running for immediate wake-up
• Standby
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ATtiny212/214/412/414/416
– Configurable operation of selected peripherals
• Power-Down with full data retention
• Peripherals
– One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three compare channels
– One 16-bit Timer/Counter type B (TCB) with input capture
– One 12-bit Timer/Counter type D (TCD) optimized for control applications
– One 16-bit Real-Time Counter (RTC) running from an external crystal, external clock, or internal RC
oscillator
– Watchdog Timer (WDT) with Window mode, with a separate on-chip oscillator
– One USART with fractional baud rate generator, auto-baud, and start-of-frame detection
– One host/client Serial Peripheral Interface (SPI)
– One Two-Wire Interface (TWI) with dual address match
• Philips I2C compatible
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
– Analog Comparator (AC) with a low propagation delay
– 10-bit 115 ksps Analog-to-Digital Converter (ADC)
– 8-bit Digital-to-Analog Converter (DAC) with one external channel
– Multiple voltage references (V
• 0.55V
• 1.1V
• 1.5V
• 2.5V
• 4.3V
– Event System (EVSYS) for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with two programmable look-up tables
– Automated CRC memory scan
– External interrupt on all general purpose pins
• I/O and Packages:
– Up to 18 programmable I/O lines
– 8-pin SOIC150
– 14-pin SOIC150
– 20-pin SOIC300
– 20-pin VQFN 3x3 mm
• Temperature Ranges:
– -40°C to 105°C
– -40°C to 125°C
• Speed Grades:
– 0-5 MHz @ 1.8V – 5.5V
– 0-10 MHz @ 2.7V – 5.5V
– 0-20 MHz @ 4.5V – 5.5V
REF
):
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ATtiny212/214/412/414/416
Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 1
1. Silicon Errata and Data Sheet Clarification Document..........................................................................10
2. tinyAVR® 1-series Overview..................................................................................................................11
2.1. Configuration Summary..............................................................................................................11
3. Block Diagram.......................................................................................................................................13
4. Pinout.................................................................................................................................................... 14
4.1. 8-Pin SOIC................................................................................................................................. 14
4.2. 14-Pin SOIC............................................................................................................................... 15
4.3. 20-Pin SOIC............................................................................................................................... 16
4.4. 20-Pin VQFN.............................................................................................................................. 17
5. I/O Multiplexing and Considerations..................................................................................................... 18
5.1. Multiplexed Signals.................................................................................................................... 18
6. Memories.............................................................................................................................................. 20
6.1. Overview.................................................................................................................................... 20
6.2. Memory Map.............................................................................................................................. 21
6.3. In-System Reprogrammable Flash Program Memory................................................................21
6.4. SRAM Data Memory.................................................................................................................. 22
6.5. EEPROM Data Memory............................................................................................................. 22
6.6. User Row....................................................................................................................................22
6.7. Signature Bytes..........................................................................................................................22
6.8. I/O Memory.................................................................................................................................23
6.9. Memory Section Access from CPU and UPDI on Locked Device..............................................25
6.10. Configuration and User Fuses (FUSE).......................................................................................26
7. Peripherals and Architecture.................................................................................................................45
7.1. Peripheral Address Map.............................................................................................................45
7.2. Interrupt Vector Mapping............................................................................................................46
7.3. System Configuration (SYSCFG)...............................................................................................47
8. AVR® CPU............................................................................................................................................ 50
8.1. Features..................................................................................................................................... 50
8.2. Overview.................................................................................................................................... 50
8.3. Architecture................................................................................................................................ 50
8.4. Arithmetic Logic Unit (ALU)........................................................................................................ 52
8.5. Functional Description................................................................................................................52
8.6. Register Summary......................................................................................................................58
8.7. Register Description................................................................................................................... 58
9. NVMCTRL - Nonvolatile Memory Controller......................................................................................... 62
9.1. Features..................................................................................................................................... 62
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9.2. Overview.................................................................................................................................... 62
9.3. Functional Description................................................................................................................63
9.4. Register Summary......................................................................................................................69
9.5. Register Description................................................................................................................... 69
10. CLKCTRL - Clock Controller................................................................................................................. 77
10.1. Features.....................................................................................................................................77
10.2. Overview.................................................................................................................................... 77
10.3. Functional Description................................................................................................................79
10.4. Register Summary......................................................................................................................83
10.5. Register Description...................................................................................................................83
11. SLPCTRL - Sleep Controller................................................................................................................. 93
11.1. Features.....................................................................................................................................93
11.2. Overview.................................................................................................................................... 93
11.3. Functional Description................................................................................................................93
11.4. Register Summary......................................................................................................................97
11.5. Register Description...................................................................................................................97
12. RSTCTRL - Reset Controller................................................................................................................ 99
12.1. Features.....................................................................................................................................99
12.2. Overview.................................................................................................................................... 99
12.3. Functional Description..............................................................................................................100
12.4. Register Summary....................................................................................................................104
12.5. Register Description.................................................................................................................104
13. CPUINT - CPU Interrupt Controller..................................................................................................... 107
13.1. Features...................................................................................................................................107
13.2. Overview.................................................................................................................................. 107
13.3. Functional Description..............................................................................................................108
13.4. Register Summary ...................................................................................................................113
13.5. Register Description................................................................................................................. 113
14. EVSYS - Event System....................................................................................................................... 118
14.1. Features................................................................................................................................... 118
14.2. Overview...................................................................................................................................118
14.3. Functional Description..............................................................................................................120
14.4. Register Summary....................................................................................................................122
14.5. Register Description.................................................................................................................122
15. PORTMUX - Port Multiplexer.............................................................................................................. 129
15.1. Overview.................................................................................................................................. 129
15.2. Register Summary....................................................................................................................130
15.3. Register Description.................................................................................................................130
16. PORT - I/O Pin Configuration..............................................................................................................135
16.1. Features...................................................................................................................................135
16.2. Overview.................................................................................................................................. 135
16.3. Functional Description..............................................................................................................137
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16.4. Register Summary - PORTx.....................................................................................................140
16.5. Register Description - PORTx.................................................................................................. 140
16.6. Register Summary - VPORTx.................................................................................................. 152
16.7. Register Description - VPORTx................................................................................................152
17. BOD - Brown-out Detector.................................................................................................................. 157
17.1. Features...................................................................................................................................157
17.2. Overview.................................................................................................................................. 157
17.3. Functional Description..............................................................................................................158
17.4. Register Summary....................................................................................................................160
17.5. Register Description.................................................................................................................160
18. VREF - Voltage Reference..................................................................................................................167
18.1. Features...................................................................................................................................167
18.2. Overview.................................................................................................................................. 167
18.3. Functional Description..............................................................................................................167
18.4. Register Summary ...................................................................................................................168
18.5. Register Description.................................................................................................................168
19. WDT - Watchdog Timer.......................................................................................................................171
19.1. Features...................................................................................................................................171
19.2. Overview.................................................................................................................................. 171
19.3. Functional Description..............................................................................................................172
19.4. Register Summary - WDT........................................................................................................175
19.5. Register Description.................................................................................................................175
20. TCA - 16-bit Timer/Counter Type A.....................................................................................................178
20.1. Features...................................................................................................................................178
20.2. Overview.................................................................................................................................. 178
20.3. Functional Description..............................................................................................................180
20.4. Register Summary - Normal Mode...........................................................................................190
20.5. Register Description - Normal Mode........................................................................................ 190
20.6. Register Summary - Split Mode............................................................................................... 209
20.7. Register Description - Split Mode.............................................................................................209
21. TCB - 16-Bit Timer/Counter Type B.................................................................................................... 225
21.1. Features...................................................................................................................................225
21.2. Overview.................................................................................................................................. 225
21.3. Functional Description..............................................................................................................227
21.4. Register Summary....................................................................................................................235
21.5. Register Description.................................................................................................................235
22. TCD - 12-Bit Timer/Counter Type D.................................................................................................... 246
22.1. Features...................................................................................................................................246
22.2. Overview.................................................................................................................................. 246
22.3. Functional Description..............................................................................................................248
22.4. Register Summary....................................................................................................................271
22.5. Register Description.................................................................................................................271
23. RTC - Real-Time Counter................................................................................................................... 296
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ATtiny212/214/412/414/416
23.1. Features...................................................................................................................................296
23.2. Overview.................................................................................................................................. 296
23.3. Clocks.......................................................................................................................................297
23.4. RTC Functional Description..................................................................................................... 297
23.5. PIT Functional Description.......................................................................................................298
23.6. Events...................................................................................................................................... 299
23.7. Interrupts..................................................................................................................................300
23.8. Sleep Mode Operation............................................................................................................. 301
23.9. Synchronization........................................................................................................................301
23.10. Debug Operation......................................................................................................................301
23.11. Register Summary....................................................................................................................302
23.12. Register Description.................................................................................................................302
24. USART - Universal Synchronous and Asynchronous Receiver and Transmitter................................318
24.1. Features...................................................................................................................................318
24.2. Overview.................................................................................................................................. 318
24.3. Functional Description..............................................................................................................319
24.4. Register Summary....................................................................................................................334
24.5. Register Description.................................................................................................................334
25. SPI - Serial Peripheral Interface..........................................................................................................351
25.1. Features...................................................................................................................................351
25.2. Overview.................................................................................................................................. 351
25.3. Functional Description..............................................................................................................352
25.4. Register Summary....................................................................................................................359
25.5. Register Description.................................................................................................................359
26. TWI - Two-Wire Interface.................................................................................................................... 366
26.1. Features...................................................................................................................................366
26.2. Overview.................................................................................................................................. 366
26.3. Functional Description..............................................................................................................367
26.4. Register Summary....................................................................................................................378
26.5. Register Description.................................................................................................................378
27. CRCSCAN - Cyclic Redundancy Check Memory Scan...................................................................... 395
27.1. Features...................................................................................................................................395
27.2. Overview.................................................................................................................................. 395
27.3. Functional Description..............................................................................................................396
27.4. Register Summary - CRCSCAN...............................................................................................399
27.5. Register Description.................................................................................................................399
28. CCL - Configurable Custom Logic...................................................................................................... 403
28.1. Features...................................................................................................................................403
28.2. Overview.................................................................................................................................. 403
28.3. Functional Description..............................................................................................................405
28.4. Register Summary....................................................................................................................412
28.5. Register Description.................................................................................................................412
29. AC - Analog Comparator.....................................................................................................................419
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ATtiny212/214/412/414/416
29.1. Features...................................................................................................................................419
29.2. Overview.................................................................................................................................. 419
29.3. Functional Description..............................................................................................................421
29.4. Register Summary....................................................................................................................423
29.5. Register Description.................................................................................................................423
30. ADC - Analog-to-Digital Converter...................................................................................................... 428
30.1. Features...................................................................................................................................428
30.2. Overview.................................................................................................................................. 428
30.3. Functional Description..............................................................................................................429
30.4. Register Summary - ADCn.......................................................................................................436
30.5. Register Description.................................................................................................................436
31. DAC - Digital-to-Analog Converter...................................................................................................... 454
31.1. Features...................................................................................................................................454
31.2. Overview.................................................................................................................................. 454
31.3. Functional Description..............................................................................................................455
31.4. Register Summary....................................................................................................................457
31.5. Register Description.................................................................................................................457
32. UPDI - Unified Program and Debug Interface.....................................................................................460
32.1. Features...................................................................................................................................460
32.2. Overview.................................................................................................................................. 460
32.3. Functional Description..............................................................................................................462
32.4. Register Summary....................................................................................................................482
32.5. Register Description.................................................................................................................482
33. Instruction Set Summary.....................................................................................................................493
34. Conventions........................................................................................................................................ 494
34.1. Numerical Notation...................................................................................................................494
34.2. Memory Size and Type.............................................................................................................494
34.3. Frequency and Time.................................................................................................................494
34.4. Registers and Bits....................................................................................................................495
34.5. ADC Parameter Definitions......................................................................................................496
35. Electrical Characteristics.....................................................................................................................499
35.1. Disclaimer.................................................................................................................................499
35.2. Absolute Maximum Ratings .....................................................................................................499
35.3. General Operating Ratings ......................................................................................................500
35.4. Power Consumption.................................................................................................................501
35.5. Wake-Up Time..........................................................................................................................503
35.6. Peripherals Power Consumption..............................................................................................503
35.7. BOD and POR Characteristics.................................................................................................504
35.8. External Reset Characteristics.................................................................................................505
35.9. Oscillators and Clocks..............................................................................................................505
35.10. I/O Pin Characteristics............................................................................................................. 507
35.11. TCD..........................................................................................................................................508
35.12. USART..................................................................................................................................... 508
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ATtiny212/214/412/414/416
35.13. SPI........................................................................................................................................... 509
35.14. TWI...........................................................................................................................................510
35.15. VREF........................................................................................................................................513
35.16. ADC..........................................................................................................................................514
35.17. TEMPSENSE........................................................................................................................... 516
35.18. DAC..........................................................................................................................................517
35.19. AC............................................................................................................................................ 518
35.20. UPDI Timing.............................................................................................................................518
35.21. Programming Time...................................................................................................................519
36. Typical Characteristics........................................................................................................................ 521
36.1. Power Consumption.................................................................................................................521
36.2. GPIO........................................................................................................................................ 528
36.3. VREF Characteristics...............................................................................................................536
36.4. BOD Characteristics.................................................................................................................538
36.5. ADC Characteristics.................................................................................................................541
36.6. TEMPSENSE Characteristics.................................................................................................. 546
36.7. AC Characteristics....................................................................................................................546
36.8. OSC20M Characteristics..........................................................................................................550
36.9. OSCULP32K Characteristics................................................................................................... 552
36.10. TWI SDA Hold Timing ............................................................................................................. 553
37. Ordering Information........................................................................................................................... 554
37.1. Product Information..................................................................................................................554
37.2. Product Identification System...................................................................................................554
38. Package Drawings.............................................................................................................................. 556
38.1. Online Package Drawings........................................................................................................556
38.2. 8-Pin SOIC...............................................................................................................................557
38.3. 14-Pin SOIC.............................................................................................................................560
38.4. 20-Pin SOIC.............................................................................................................................563
38.5. 20-Pin VQFN............................................................................................................................566
38.6. Thermal Considerations...........................................................................................................569
39. Errata.................................................................................................................................................. 570
39.1. Errata - ATtiny212/214/412/414/416........................................................................................ 570
40. Data Sheet Revision History............................................................................................................... 571
40.1. Rev. A - 12/2020.......................................................................................................................571
40.2. Appendix - Obsolete Revision History......................................................................................577
The Microchip Website...............................................................................................................................582
Product Change Notification Service..........................................................................................................582
Customer Support...................................................................................................................................... 582
Product Identification System.....................................................................................................................583
Microchip Devices Code Protection Feature.............................................................................................. 583
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ATtiny212/214/412/414/416
Legal Notice............................................................................................................................................... 583
Trademarks................................................................................................................................................ 584
Quality Management System..................................................................................................................... 584
Worldwide Sales and Service.....................................................................................................................585
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ATtiny212/214/412/414/416
Silicon Errata and Data Sheet Clarification ...
1. Silicon Errata and Data Sheet Clarification Document
Microchip aims to provide its customers with the best documentation possible to ensure the successful use of
Microchip products. Between data sheet updates, a Silicon errata and data sheet clarification document will contain
the most recent information for the data sheet. The ATtiny212/214/412/414/416 Silicon Errata and Data Sheet
Clarification(www.microchip.com/DS80000933) is available at the device product page on www.microchip.com.
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2. tinyAVR® 1-series Overview
8
Pins
20 24
14
8 KB
Flash
16 KB
32 KB
4 KB
2 KB
Devices described in this data sheet
Devices described in other data sheets
ATtiny3216 ATtiny3217
ATtiny1614 ATtiny1616
ATtiny1617
ATtiny412
ATtiny212
ATtiny414 ATtiny416
ATtiny417
ATtiny214
ATtiny814 ATtiny816
ATtiny817
The following figure shows the tinyAVR 1-series devices, laying out pin count variants and memory sizes:
• Vertical migration upwards is possible without code modification, as these devices are pin-compatible and
provide the same or more features. Downward migration may require code modification due to fewer available
instances of some peripherals.
• Horizontal migration to the left reduces the pin count and, therefore, the available features
Figure 2-1. tinyAVR® 1-series Overview
ATtiny212/214/412/414/416
tinyAVR® 1-series Overview
Devices with different Flash memory sizes typically also have different SRAM and EEPROM.
2.1 Configuration Summary
2.1.1 Peripheral Summary
Table 2-1. Peripheral Summary
Pins 8 14 8 14 20
SRAM 128B 128B 256B 256B 256B
Flash 2 KB 2 KB 4 KB 4 KB 4 KB
EEPROM 64B 64B 128B 128B 128B
Max. frequency (MHz) 20 20 20 20 20
16-bit Timer/Counter type A (TCA) 1 1 1 1 1
16-bit Timer/Counter type B (TCB) 1 1 1 1 1
12-bit Timer/Counter type D (TCD) 1 1 1 1 1
ATtiny212
ATtiny214
ATtiny412
ATtiny414
ATtiny416
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...........continued
ATtiny212/214/412/414/416
tinyAVR® 1-series Overview
ATtiny212
Real-Time Counter (RTC) 1 1 1 1 1
USART 1 1 1 1 1
SPI 1 1 1 1 1
TWI (I2C) 1 1 1 1 1
ADC 1 1 1 1 1
ADC channels 6 10 6 10 12
DAC 1 1 1 1 1
AC 1 1 1 1 1
AC inputs 1p/1n 1p/1n 1p/1n 1p/1n 2p/2n
Peripheral Touch Controller (PTC) No No No No No
Configurable Custom Logic 1 1 1 1 1
Window Watchdog 1 1 1 1 1
Event System channels 6 6 6 6 6
General purpose I/O 6 12 6 12 18
External interrupts 6 12 6 12 18
CRCSCAN 1 1 1 1 1
ATtiny214
ATtiny412
ATtiny414
ATtiny416
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3. Block Diagram
Figure 3-1. tinyAVR® 1-series Block Diagram
UPDI / RESET
To
detectors
UPDI
CRC
OCD
ATtiny212/214/412/414/416
Block Diagram
Analog peripherals
analog peripherals
®
CPU
Flash
Digital peripherals
analog peripherals
Core components
analog peripherals
Clocks/generators
AINP[3:0]
AINN[1:0]
OUT
OUT
AIN[11:0]
X[13:0]
Y[13:0]
VREFA
AIN[11:0]
LUTn-IN[2:0]
LUTn-OUT
WO[5:0]
WO
WO[A,B,C,D]
RXD
TXD
XCK
XDIR
MISO
MOSI
SCK
SDA
SCL
SRAM
BUS Matrix
EEPROM
NVMCTRL
I
N
/
AC [2:0]
[2:0]
DAC
ADC0 / PTC
ADC1
CCL
TCA0
TCB[1:0]
TCD0
PORTS
GPIOR
D
E
A
V
T
E
A
N
B
T
U
S
R
O
U
T
I
N
G
N
E
T
W
O
R
K
CPUINT
System
Management
RSTCTRL
CLKCTRL
SLPCTRL
WDT
RTC
O
U
T
D
A
T
A
B
U
S
Detectors/
References
RST
Bandgap
BOD
Clock Generation
OSC20M
OSC32K
XOSC32K
POR
VLM
USART0
EXTCLK
SS
SPI0
EVSYS
PA[7:0]
PB[7:0]
PC[5:0]
CLKOUT
TOSC1
TOSC2
EXTCLK
EVOUT[n:0]
TWI0
Note: The block diagram represents the largest device of the tinyAVR®1-series, both in terms of pin count and Flash
size. See sections 2.1 Configuration Summary and 5. I/O Multiplexing and Considerations for an overview of the
features of the specific devices in this data sheet.
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4. Pinout
Power Supply
Ground
Functionality
Programming/Debug
Clock/Crystal
Analog Function
Digital Function OnlyPin on VDD Power Domain
VDD
PA6
PA7
PA1
PA3 (EXTCLK)
PA0 (RESET/UPDI)
PA2
GND
1
2
3
4
5
6
7
8
4.1 8-Pin SOIC
ATtiny212/214/412/414/416
Pinout
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4.2 14-Pin SOIC
ATtiny212/214/412/414/416
Pinout
(TOSC1) PB3
(TOSC2) PB2
Power
Power Supply
Ground
VDD
PA4
PA5
PA6
PA7
1
2
3
4
5
6
7
14
13
12
11
10
9
8
GND
PA3 (EXTCLK)
PA2
PA1
PA0 (RESET/UPDI)
PB0
PB1
Functionality
Programming/Debug
Clock/Crystal
Digital Function OnlyPin on VDD Power Domain
Analog Function
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4.3 20-Pin SOIC
ATtiny212/214/412/414/416
Pinout
VDD
PA4
PA5
PA6
PA7
PB5
PB4
(TOSC1) PB3
(TOSC2) PB2
PB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
PA3 (EXTCLK)
PA2
PA1
PA0 (RESET/UPDI)
PC3
PC2
PC1
PC0
PB0
Power
Power Supply
Ground
Functionality
Programming/Debug
Clock/Crystal
Digital Function OnlyPin on VDD Power Domain
Analog Function
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4.4 20-Pin VQFN
ATtiny212/214/412/414/416
Pinout
PA2
(EXTCLK) PA3
GND
VDD
PA4
Note: It is recommended to
solder the large center pad to
ground for mechanical stability
Power
Power Supply
PA1
PA0 (RESET/UPDI)
20 19 18 17
1
2
3
4
5
6
7
PA6
PA5
PC3
8
PA7
PC2
PC1
16
15
14
13
12
11
9
10
PB4
PB5
Functionality
Programming/Debug
PC0
PB0
PB1
PB2 (TOSC2)
PB3 (TOSC1)
Ground
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Clock/Crystal
Digital Function OnlyPin on VDD Power Domain
Analog Function
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ATtiny212/214/412/414/416
I/O Multiplexing and Considerations
5. I/O Multiplexing and Considerations
5.1 Multiplexed Signals
Table 5-1. PORT Function Multiplexing, 14 and 20 Pins
DD
(1,2)
Other/Special ADC0 AC0 DAC0 USART0 SPI0 TWI0 TCA0 TCB0 TCD0 CCL
(3)
MOSI SDA
(3)
MISO SCL
(3)
SCK WO3
(3)
SS WO4 WOA LUT0-OUT
(3)(4)
(3)(4)
(3)
(3)(4)
(3)(4)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
WO
(3)
WO3
LUT0-IN1
LUT0-IN2
LUT1-OUT
LUT0-OUT
WOC
WOD LUT1-OUT
LUT1-IN0
Pin Name
SOIC 20-Pin
VQFN 20-Pin
19 16 10 PA0 RESET/ UPDI AIN0 LUT0-IN0
20 17 11 PA1 AIN1 TxD
1 18 12 PA2 EVOUT0 AIN2 RxD
2 19 13 PA3 EXTCLK AIN3 XCK
3 20 14 GND
4 1 1 V
5 2 2 PA4 AIN4 XDIR
6 3 3 PA5 AIN5 OUT WO5 WO WOB
7 4 4 PA6 AIN6 AINN0 OUT MOSI
8 5 5 PA7 AIN7 AINP0 MISO
9 6 PB5 CLKOUT AIN8 AINP1 WO2
10 7 PB4 AIN9 AINN1 WO1
11 8 6 PB3 TOSC1 RxD WO0
12 9 7 PB2 TOSC2, EVOUT1 TxD WO2
13 10 8 PB1 AIN10 XCK SDA WO1
14 11 9 PB0 AIN11 XDIR SCL WO0
15 12 PC0 SCK
16 13 PC1 MISO
17 14 PC2 EVOUT2 MOSI
18 15 PC3 SS
SOIC 14-Pin
(3)
(3)
Notes:
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. The notation for
signals is PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to section 15. PORTMUX - Port Multiplexer.
4. Alternate pins for SPI MISO and MOSI are respectively at PA7 and PA6 for 14-pin devices and PC1 and PC2
for 20-pin devices.
Table 5-2. PORT Function Multiplexing, Eight Pins
SOIC 8-Pin
6 PA0 RESET/UPDI AIN0 XDIR SS LUT0-IN0
4 PA1 AIN1 TxD
5 PA2 EVOUT0 AIN2 RxD
7 PA3 EXTCLK AIN3 OUT XCK SCK WO0/WO3
8 GND
1 VDD
2 PA6 AIN6 AINN0 OUT TxD MOSI
3 PA7 AIN7 AINP0 RxD MISO
Pin Name
(1,2)
Other/
Special
ADC0 AC0 DAC0 USART0 SPI0 TWI0 TCA0 TCB0 TCD0 CCL
(3)
MOSI SDA WO1 LUT0-IN1
(3)
MISO SCL WO2 LUT0-IN2
(3)
(3)
WO0
WO0 WOA LUT0-OUT
(3)
WOB LUT1-OUT
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Complete Datasheet
DS40002287A-page 18
ATtiny212/214/412/414/416
I/O Multiplexing and Considerations
Notes:
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. Notation for signals is
PORTx_PINn. All pins can be used as event inputs.
2. All pins can be used for external interrupts, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to section 15. PORTMUX - Port Multiplexer.
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6. Memories
6.1 Overview
The main memories are SRAM data memory, EEPROM data memory, and Flash program memory. Also, the
peripheral registers are located in the I/O memory space.
Table 6-1. Physical Properties of Flash Memory
Property ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416
Size 2 KB 2 KB 4 KB 4 KB 4 KB
Page size 64B 64B 64B 64B 64B
Number of pages 32 32 64 64 64
Start address 0x8000 0x8000 0x8000 0x8000 0x8000
Table 6-2. Physical Properties of SRAM
Property ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416
ATtiny212/214/412/414/416
Memories
Size 128B 128B 256B 256B 256B
Start address 0x3F80 0x3F80 0x3F00 0x3F00 0x3F00
Table 6-3. Physical Properties of EEPROM
Property ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416
Size 64B 64B 128B 128B 128B
Page size 32B 32B 32B 32B 32B
Number of pages 2 2 4 4 4
Start address 0x1400 0x1400 0x1400 0x1400 0x1400
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6.2 Memory Map
Figure 6-1. Memory Map
CPU Code space UPDI/CPU Data space
0x0000
ATtiny212/214/412/414/416
Memories
64 I/O Registers
960 Ext. I/O Registers
0x0000 – 0x003F
0x0040 – 0x0FFF
Flash Code
2/4 KB
NVM I/O Registers and
Data
EEPROM 64/128B
(Reserved)
Internal SRAM
128/256B
(Reserved)
0x1000 – 0x13FF
0x1400
0x1440 (For EEPROM 64B)/
0x1480 (For EEPROM 128B)
0x3F80/0x3F00
0x3FFF
0x8000
Flash Code
2/4 KB
6.3 In-System Reprogrammable Flash Program Memory
The ATtiny212/214/412/414/416 contains 2/4 KB on-chip in-system reprogrammable Flash memory for program
storage. Since all AVR instructions are 16 or 32-bit wide, the Flash is organized with 16-bit data width. For write
protection, the Flash program memory space can be divided into three sections (see the illustration below):
Bootloader section, Application code section, and Application data section, with restricted access rights among them.
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0x87FF (For Flash 2K)/
0x8FFF (For Flash 4K)
DS40002287A-page 21
FLASHSTART: 0x8000
BOOTEND>0: 0x8000+BOOTEND*256
BO O T
APPEND>0: 0x8000+APPEND*256
AP PL IC A T IO N
CO DE
AP PL IC A T IO N
DA TA
FLASH
FLASHEND
ATtiny212/214/412/414/416
Memories
The Program Counter (PC) is 11-bit wide to address the whole program memory. The procedure for writing Flash
memory is described in detail in the documentation of the Nonvolatile Memory Controller (NVMCTRL) peripheral.
The entire Flash memory is mapped in the memory space and is accessible with normal LD/ST instructions as well as
the LPM instruction. For LD/ST instructions, the Flash is mapped from address 0x8000. For the LPM instruction, the
Flash start address is 0x0000.
The ATtiny212/214/412/414/416 also has a CRC peripheral that is a host on the bus.
Figure 6-2. Flash and the Three Sections
6.4 SRAM Data Memory
The 128/256 bytes SRAM is used for data storage and stack.
6.5 EEPROM Data Memory
The ATtiny212/214/412/414/416 has 64/128 bytes of EEPROM data memory. See also section 6.2 Memory Map.
The EEPROM memory supports single-byte read and write. The EEPROM is controlled by the Nonvolatile Memory
Controller (NVMCTRL).
6.6 User Row
In addition to the EEPROM, the ATtiny212/214/412/414/416 has one extra page of EEPROM memory that can be
used for firmware settings; the User Row (USERROW). This memory supports single-byte read and write as the
normal EEPROM. The CPU can write and read this memory as normal EEPROM, and the UPDI can write and read it
as a normal EEPROM memory if the part is unlocked. The User Row can be written by the UPDI when the part is
locked. USERROW is not affected by a chip erase.
6.7 Signature Bytes
All tinyAVR® microcontrollers have a 3-byte signature code that identifies the device. The three bytes reside in a
separate address space. For the device, the signature bytes are given in the following table.
Note: When the device is locked, only the System Information Block (SIB) can be accessed.
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Table 6-4. Device ID
Device Name Signature Bytes Address
ATtiny212 0x1E 0x91 0x21
ATtiny214 0x1E 0x91 0x20
ATtiny412 0x1E 0x92 0x23
ATtiny414 0x1E 0x92 0x22
ATtiny416 0x1E 0x92 0x21
6.8 I/O Memory
All ATtiny212/214/412/414/416 I/Os and peripherals are located in the I/O memory space. The I/O address range
from 0x00 to 0x3F can be accessed in a single cycle using IN and OUT instructions. The extended I/O memory space
from 0x0040 to 0x0FFF can be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between
the 32 general purpose working registers and the I/O memory space.
I/O registers within the address range 0x00-0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
Instruction Set section for more details.
For compatibility with future devices, reserved bits must be written to ‘0’ if accessed. Reserved I/O memory
addresses must never be written.
Some of the interrupt flags are cleared by writing a ‘1’ to them. On ATtiny212/214/412/414/416 devices, the CBI and
SBI instructions will only operate on the specified bit and can be used on registers containing such interrupt flags.
The CBI and SBI instructions work with registers 0x00-0x1F only.
ATtiny212/214/412/414/416
Memories
0x00 0x01 0x02
General Purpose I/O Registers
The ATtiny212/214/412/414/416 devices provide four general purpose I/O registers. These registers can be used for
storing any information, and they are particularly useful for storing global variables and interrupt flags. General
purpose I/O registers, which reside in the address range 0x1C-0x1F, are directly bit-accessible using the SBI, CBI,
SBIS, and SBIC instructions.
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ATtiny212/214/412/414/416
Memories
6.8.1 Register Summary
Offset Name Bit Pos. 7 6 5 4 3 2 1 0
0x00 GPIOR0 7:0 GPIOR[7:0]
0x01 GPIOR1 7:0 GPIOR[7:0]
0x02 GPIOR2 7:0 GPIOR[7:0]
0x03 GPIOR3 7:0 GPIOR[7:0]
6.8.2 Register Description
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ATtiny212/214/412/414/416
Memories
6.8.2.1 General Purpose I/O Register n
Name: GPIORn
Offset: 0x00 + n*0x01 [n=0..3]
Reset: 0x00
Property: -
These are general purpose registers that can be used to store data, such as global variables and flags, in the bitaccessible I/O memory space.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7:0 – GPIOR[7:0] General Purpose I/O Register Byte
6.9 Memory Section Access from CPU and UPDI on Locked Device
The device can be locked so that the memories cannot be read using the UPDI. The locking protects both the Flash
(all Boot, Application Code, and Application Data sections), SRAM, and the EEPROM, including the FUSE data. This
prevents successful reading of application data or code using the debugger interface. Regular memory access from
within the application is still enabled.
The device is locked by writing a non-valid key to the LOCKBIT bit field in FUSE.LOCKBIT.
Table 6-5. Memory Access Unlocked (FUSE.LOCKBIT Valid Key)
GPIOR[7:0]
(1)
Memory Section CPU Access UPDI Access
Read Write Read Write
SRAM Yes Yes Yes Yes
Registers Yes Yes Yes Yes
Flash Yes Yes Yes Yes
EEPROM Yes Yes Yes Yes
USERROW Yes Yes Yes Yes
SIGROW Yes No Yes No
Other fuses Yes No Yes Yes
Table 6-6. Memory Access Locked (FUSE.LOCKBIT Invalid Key)
(1)
Memory Section CPU Access UPDI Access
Read Write Read Write
SRAM Yes Yes No No
Registers Yes Yes No No
Flash Yes Yes No No
EEPROM Yes Yes No No
USERROW Yes Yes No Yes
(2)
SIGROW Yes No No No
Other fuses Yes No No No
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Notes:
1. Read operations marked No in the tables may appear to be successful, but the data are not valid. Hence, any
attempt of code validation through the UPDI will fail on these memory sections.
2. In the Locked mode, the USERROW can be written using the Fuse Write command, but the current
USERROW values cannot be read out.
Important: The only way to unlock a device is through a CHIPERASE. No application data are retained.
6.10 Configuration and User Fuses (FUSE)
Fuses are part of the nonvolatile memory and hold the device configuration. The fuses are available from the device
power-up. The fuses can be read by the CPU or the UPDI but can only be programmed or cleared by the UPDI. The
configuration values stored in the fuses are written to their respective target registers at the end of the start-up
sequence.
The fuses for peripheral configuration (FUSE) are pre-programmed but can be altered by the user. Altered values in
the configuration fuse will be effective only after a Reset.
Note: When writing the fuses, all reserved bits must be written to ‘1’.
ATtiny212/214/412/414/416
Memories
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Complete Datasheet
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ATtiny212/214/412/414/416
Memories
6.10.1 Signature Row Summary
Offset Name Bit Pos. 7 6 5 4 3 2 1 0
0x00 DEVICEID0 7:0 DEVICEID[7:0]
0x01 DEVICEID1 7:0 DEVICEID[7:0]
0x02 DEVICEID2 7:0 DEVICEID[7:0]
0x03 SERNUM0 7:0 SERNUM[7:0]
0x04 SERNUM1 7:0 SERNUM[7:0]
0x05 SERNUM2 7:0 SERNUM[7:0]
0x06 SERNUM3 7:0 SERNUM[7:0]
0x07 SERNUM4 7:0 SERNUM[7:0]
0x08 SERNUM5 7:0 SERNUM[7:0]
0x09 SERNUM6 7:0 SERNUM[7:0]
0x0A SERNUM7 7:0 SERNUM[7:0]
0x0B SERNUM8 7:0 SERNUM[7:0]
0x0C SERNUM9 7:0 SERNUM[7:0]
0x0D
...
0x1F
0x20 TEMPSENSE0 7:0 TEMPSENSE[7:0]
0x21 TEMPSENSE1 7:0 TEMPSENSE[7:0]
0x22 OSC16ERR3V 7:0 OSC16ERR3V[7:0]
0x23 OSC16ERR5V 7:0 OSC16ERR5V[7:0]
0x24 OSC20ERR3V 7:0 OSC20ERR3V[7:0]
0x25 OSC20ERR5V 7:0 OSC20ERR5V[7:0]
Reserved
6.10.2 Signature Row Description
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Complete Datasheet
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ATtiny212/214/412/414/416
Memories
6.10.2.1 Device ID n
Name: DEVICEIDn
Offset: 0x00 + n*0x01 [n=0..2]
Default: [Device ID]
Property: -
Each device has a device ID identifying this device and its properties such as memory sizes, pin count, and die
revision. This ID can be used to identify a device and hence, the available features by software. The Device ID
consists of three bytes: SIGROW.DEVICEID[2:0].
Bit 7 6 5 4 3 2 1 0
Access
Default x x x x x x x x
R R R R R R R R
Bits 7:0 – DEVICEID[7:0] Byte n of the Device ID
DEVICEID[7:0]
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ATtiny212/214/412/414/416
Memories
6.10.2.2 Serial Number Byte n
Name: SERNUMn
Offset: 0x03 + n*0x01 [n=0..9]
Default: [device serial number]
Property: -
Each device has an individual serial number, representing a unique ID. This ID can be used to identify a specific
device in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].
Bit 7 6 5 4 3 2 1 0
Access
Default x x x x x x x x
R R R R R R R R
Bits 7:0 – SERNUM[7:0] Serial Number Byte n
SERNUM[7:0]
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ATtiny212/214/412/414/416
Memories
6.10.2.3 Temperature Sensor Calibration n
Name: TEMPSENSEn
Offset: 0x20 + n*0x01 [n=0..1]
Default: [Temperature sensor calibration value]
Property: -
The Temperature Sensor Calibration registers contain correction factors for temperature measurements from the onchip sensor. The ADC.SIGROW.TEMPSENSE0 is a correction factor for the gain/slope (unsigned), and
SIGROW.TEMPSENSE1 is a correction factor for the offset (signed).
Bit 7 6 5 4 3 2 1 0
Access
Default x x x x x x x x
R R R R R R R R
Bits 7:0 – TEMPSENSE[7:0] Temperature Sensor Calibration Byte n
Refer to the ADC section for a description of how to use this register.
TEMPSENSE[7:0]
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