ATtiny1624/1626/1627
Pins
Flash
Devices described in this data sheet
Devices described in other data sheets
ATtiny824
ATtiny1624
ATtiny424
ATtiny1626 ATtiny1627
ATtiny826 ATtiny827
ATtiny426 ATtiny427
4 KB
20 24
14
8 KB
16 KB
32 KB
ATtiny3224 ATtiny3226 ATtiny3227
tinyAVR® 2 Family
Introduction
The ATtiny1624/1626/1627 microcontrollers of the tinyAVR® 2 family are using the AVR® CPU with hardware
multiplier, running at up to 20 MHz, with 16 KB Flash, 2 KB of SRAM, and 256B of EEPROM available in a 14-, 20-,
and 24-pin package. The family uses the latest technologies from Microchip with a flexible and low-power
architecture, including Event System, advanced digital peripherals, and accurate analog features such as a 12-bit
differential ADC with Programmable Gain Amplifier (PGA).
tinyAVR® 2 Family Overview
The figure below shows the tinyAVR® 2 family devices, laying out pin count variants and memory sizes.
• Vertical migration is possible without code modification, as these devices are fully pin and feature compatible
• Horizontal migration to the left reduces the pin count and, therefore, the available features
Figure 1. tinyAVR® 2 Family Overview
Devices with different flash memory sizes typically also have different SRAM and EEPROM.
The name of a device in the tinyAVR® 2 family is decoded as follows:
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 1
Carrier Type
AT tiny 1627 - MUR - VAO
Flash size in KB
Family number
Pin count
7=24 pins
6=20 pins
4=14 pins
Package Type
M=VQFN
S=SOIC300
SS=SOIC150
X=TSSOP, SSOP
Temperature Range
R = Tape & Reel
U = -40°C to +85°C
F = -40°C to +125°C
Blank = Tube or Tray
Variant Suffix
VAO = Automotive
Blank = Standard
AVR product family
®
ATtiny1624/1626/1627
Figure 2. tinyAVR® 2 Family Device Designations
Note: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for
ordering purposes. Check with your Microchip Sales Office for package availability with the Tape and Reel option.
Note: The VAO variants have been designed, manufactured, tested, and qualified in accordance with AEC-Q100
requirements for automotive applications. These products may use a different package than non-VAO parts and can
have additional specifications in their Electrical Characteristics.
Memory Overview
The following table shows the memory overview of the entire family, but further documentation describes only the
ATtiny1624/1626/1627 devices.
Table 1. Memory Overview
Device ATtiny424
ATtiny426
ATtiny427
Flash Memory 4 KB 8 KB 16 KB 32 KB
SRAM 512B 1 KB 2 KB 3 KB
EEPROM 128B 128B 256B 256B
User Row 32B 32B 32B 32B
ATtiny824
ATtiny826
ATtiny827
ATtiny1624
ATtiny1626
ATtiny1627
ATtiny3224
ATtiny3226
ATtiny3227
Peripheral Overview
Table 2. Peripheral Overview
Device ATtiny1624 ATtiny1626 ATtiny1627
Pins 14 20 24
Package SOIC, TSSOP SOIC,
SSOP,VQFN
VQFN
Maximum frequency (MHz) 20 20 20
General purpose I/O 12 18 22
PORT PA[7:0], PB[3:0] PA[7:0], PB[5:0],
External interrupts 12 18 22
Event system channels 6 6 6
© 2020 Microchip Technology Inc.
Preliminary Datasheet
PC[3:0]
PA[7:0],
PB[7:0], PC[5:0]
DS40002234A-page 2
ATtiny1624/1626/1627
...........continued
Device ATtiny1624 ATtiny1626 ATtiny1627
CCL LUTs 4 4 4
Real-Time Counter (RTC) 1 1 1
16-bit Timer/Counter type A (TCA) 1 1 1
16-bit Timer/Counter type B (TCB) 2 2 2
12-bit Timer/Counter type D (TCD) - - -
USART/SPI master 2 2 2
SPI 1 1 1
TWI (I2C) 1 1 1
ADC (channels) 1 (9) 1 (15) 1 (15)
DAC - - -
Analog Comparators (inputs) 1 (4p/3n) 1 (4p/3n) 1 (4p/3n)
Peripheral Touch Controller (PTC) (self cap/mutual cap
channels)
Unified Program and Debug Interface (UPDI) activated by
shared pin using high-voltage signal or fuse override
- - -
1 1 1
Features
• High-Performance Low-Power AVR® CPU
– Running at up to 20 MHz
– Single-cycle I/O access
– Two-level interrupt controller with vectored interrupts
– Two-cycle hardware multiplier
– Supply voltage range: 1.8V to 5.5V
• Memories
– 16 KB In-System self-programmable Flash memory
– 2 KB SRAM
– 256B EEPROM
– 32B of user row in nonvolatile memory that can keep data during chip-erase and be programmed while the
device is locked
– Write/erase endurance
• Flash 10,000 cycles
• EEPROM 100,000 cycles
– Data retention: 40 years at 55°C
• System
– Power-on Reset (POR)
– Brown-out Detection (BOD)
– Clock options
• Lockable 20 MHz Low-Power internal oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal oscillator
• 32.768 kHz external crystal oscillator
• External clock input
– Single-pin Unified Program and Debug Interface (UPDI)
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 3
ATtiny1624/1626/1627
– Three sleep modes
• Idle with all peripherals running and immediate wake-up time
• Standby with configurable operation of selected peripherals
• Power-Down with full data retention
• Peripherals
– One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three PWM channels
– Two 16-bit Timer/Counter type B (TCB) with input capture and simple PWM functionality
– One 16-bit Real-Time Counter (RTC) running from external 32.768 kHz crystal or internal 32.768 kHz ULP
oscillator
– Two Universal Synchronous Asynchronous Receiver Transmitter (USART) with fractional baud rate
generator, auto-baud, and start-of-frame detection
– Master/Slave Serial Peripheral Interface (SPI)
– Master/Slave Two-Wire Interface (TWI) with dual address match
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
– Event System for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with four programmable Look-Up Tables (LUT)
– One Analog Comparator (AC) with scalable reference input
– One 12-bit differential 375 ksps Analog-to-Digital Converter (ADC) with Programmable Gain Amplifier
(PGA) and up to 15 input channels
– Multiple internal voltage references
• 1.024V
• 2.048V
• 2.500V
• 4.096V
• VDD
– Automated Cyclic Redundancy Check (CRC) flash memory scan
– Watchdog Timer (WDT) with Window Mode, with a separate on-chip oscillator
– External interrupt on all general purpose pins
• I/O and Packages
– Up to 22 programmable I/O pins
– 14-pin
• SOIC
• TSSOP
– 20-pin
• SOIC
• SSOP
• VQFN 3x3 mm
– 24-pin
• VQFN 4x4 mm
• Temperature Ranges
– -40°C to 85°C (standard)
– -40°C to 125°C (extended)
• Speed Grades (-40°C to 85°C)
– 0-5 MHz @ 1.8V – 5.5V
– 0-10 MHz @ 2.7V – 5.5V
– 0-20 MHz @ 4.5V – 5.5V
• Speed Grades (-40°C to 125°C)
– 0-8 MHz @ 2.7V - 5.5V
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 4
– 0-16 MHz @ 4.5V - 5.5V
ATtiny1624/1626/1627
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 5
ATtiny1624/1626/1627
Table of Contents
Introduction.....................................................................................................................................................1
tinyAVR® 2 Family Overview..........................................................................................................................1
1. Memory Overview........................................................................................................................ 2
2. Peripheral Overview..................................................................................................................... 2
Features......................................................................................................................................................... 3
1. Block Diagram.......................................................................................................................................12
2. Pinout.................................................................................................................................................... 13
2.1. 14-Pin SOIC, TSSOP.................................................................................................................13
2.2. 20-Pin SOIC, SSOP................................................................................................................... 14
2.3. 20-Pin VQFN..............................................................................................................................15
2.4. 24-Pin VQFN..............................................................................................................................16
3. I/O Multiplexing and Considerations..................................................................................................... 17
3.1. I/O Multiplexing...........................................................................................................................17
4. Hardware Guidelines.............................................................................................................................18
4.1. General Guidelines.....................................................................................................................18
4.2. Connection for Power Supply.....................................................................................................18
4.3. Connection for RESET...............................................................................................................19
4.4. Connection for UPDI Programming............................................................................................20
4.5. Connecting External Crystal Oscillators.....................................................................................20
4.6. Connection for External Voltage Reference...............................................................................21
5. Conventions.......................................................................................................................................... 22
5.1. Numerical Notation.....................................................................................................................22
5.2. Memory Size and Type...............................................................................................................22
5.3. Frequency and Time...................................................................................................................22
5.4. Registers and Bits...................................................................................................................... 23
5.5. ADC Parameter Definitions........................................................................................................ 24
6. AVR® CPU............................................................................................................................................ 27
6.1. Features..................................................................................................................................... 27
6.2. Overview.................................................................................................................................... 27
6.3. Architecture................................................................................................................................ 27
6.4. Arithmetic Logic Unit (ALU)........................................................................................................29
6.5. Functional Description................................................................................................................29
6.6. Register Summary......................................................................................................................33
6.7. Register Description...................................................................................................................33
7. Memories.............................................................................................................................................. 37
7.1. Overview.................................................................................................................................... 37
7.2. Memory Map.............................................................................................................................. 37
7.3. In-System Reprogrammable Flash Program Memory................................................................37
7.4. SRAM Data Memory.................................................................................................................. 38
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 6
ATtiny1624/1626/1627
7.5. EEPROM Data Memory............................................................................................................. 38
7.6. USERROW - User Row..............................................................................................................39
7.7. LOCKBIT - Memory Sections Access Protection....................................................................... 39
7.8. FUSE - Configuration and User Fuses.......................................................................................42
7.9. SIGROW - Signature Row..........................................................................................................50
7.10. I/O Memory.................................................................................................................................54
8. Peripherals and Architecture.................................................................................................................57
8.1. Peripheral Address Map.............................................................................................................57
8.2. Interrupt Vector Mapping............................................................................................................58
8.3. SYSCFG - System Configuration...............................................................................................59
9. General Purpose I/O Registers............................................................................................................. 62
9.1. Register Summary......................................................................................................................63
9.2. Register Description...................................................................................................................63
10. NVMCTRL - Nonvolatile Memory Controller......................................................................................... 65
10.1. Features.....................................................................................................................................65
10.2. Overview.................................................................................................................................... 65
10.3. Functional Description................................................................................................................66
10.4. Register Summary......................................................................................................................71
10.5. Register Description...................................................................................................................71
11. CLKCTRL - Clock Controller.................................................................................................................79
11.1. Features.....................................................................................................................................79
11.2. Overview.................................................................................................................................... 79
11.3. Functional Description................................................................................................................81
11.4. Register Summary......................................................................................................................85
11.5. Register Description...................................................................................................................85
12. SLPCTRL - Sleep Controller.................................................................................................................95
12.1. Features.....................................................................................................................................95
12.2. Overview.................................................................................................................................... 95
12.3. Functional Description................................................................................................................95
12.4. Register Summary......................................................................................................................99
12.5. Register Description...................................................................................................................99
13. RSTCTRL - Reset Controller.............................................................................................................. 101
13.1. Features...................................................................................................................................101
13.2. Overview.................................................................................................................................. 101
13.3. Functional Description..............................................................................................................102
13.4. Register Summary....................................................................................................................106
13.5. Register Description.................................................................................................................106
14. CPUINT - CPU Interrupt Controller.....................................................................................................109
14.1. Features...................................................................................................................................109
14.2. Overview.................................................................................................................................. 109
14.3. Functional Description..............................................................................................................110
14.4. Register Summary ...................................................................................................................115
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 7
ATtiny1624/1626/1627
14.5. Register Description................................................................................................................. 115
15. EVSYS - Event System.......................................................................................................................120
15.1. Features...................................................................................................................................120
15.2. Overview.................................................................................................................................. 120
15.3. Functional Description..............................................................................................................121
15.4. Register Summary....................................................................................................................127
15.5. Register Description.................................................................................................................127
16. PORTMUX - Port Multiplexer..............................................................................................................133
16.1. Overview.................................................................................................................................. 133
16.2. Register Summary....................................................................................................................134
16.3. Register Description.................................................................................................................134
17. PORT - I/O Pin Configuration..............................................................................................................141
17.1. Features...................................................................................................................................141
17.2. Overview.................................................................................................................................. 141
17.3. Functional Description..............................................................................................................143
17.4. Register Summary - PORTx.....................................................................................................146
17.5. Register Description - PORTx.................................................................................................. 146
17.6. Register Summary - VPORTx.................................................................................................. 158
17.7. Register Description - VPORTx................................................................................................158
18. BOD - Brown-out Detector.................................................................................................................. 163
18.1. Features...................................................................................................................................163
18.2. Overview.................................................................................................................................. 163
18.3. Functional Description..............................................................................................................164
18.4. Register Summary....................................................................................................................166
18.5. Register Description.................................................................................................................166
19. VREF - Voltage Reference..................................................................................................................173
19.1. Features...................................................................................................................................173
19.2. Overview.................................................................................................................................. 173
19.3. Functional Description..............................................................................................................173
19.4. Register Summary....................................................................................................................175
19.5. Register Description.................................................................................................................175
20. WDT - Watchdog Timer ......................................................................................................................178
20.1. Features...................................................................................................................................178
20.2. Overview.................................................................................................................................. 178
20.3. Functional Description..............................................................................................................179
20.4. Register Summary....................................................................................................................182
20.5. Register Description.................................................................................................................182
21. TCA - 16-bit Timer/Counter Type A.....................................................................................................186
21.1. Features...................................................................................................................................186
21.2. Overview.................................................................................................................................. 186
21.3. Functional Description..............................................................................................................189
21.4. Register Summary - Normal Mode...........................................................................................199
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 8
ATtiny1624/1626/1627
21.5. Register Description - Normal Mode........................................................................................ 199
21.6. Register Summary - Split Mode............................................................................................... 218
21.7. Register Description - Split Mode.............................................................................................218
22. TCB - 16-bit Timer/Counter Type B.....................................................................................................234
22.1. Features...................................................................................................................................234
22.2. Overview.................................................................................................................................. 234
22.3. Functional Description..............................................................................................................236
22.4. Register Summary....................................................................................................................246
22.5. Register Description.................................................................................................................246
23. RTC - Real-Time Counter................................................................................................................... 257
23.1. Features...................................................................................................................................257
23.2. Overview.................................................................................................................................. 257
23.3. Clocks.......................................................................................................................................258
23.4. RTC Functional Description..................................................................................................... 258
23.5. PIT Functional Description.......................................................................................................259
23.6. Crystal Error Correction............................................................................................................260
23.7. Events...................................................................................................................................... 260
23.8. Interrupts..................................................................................................................................261
23.9. Sleep Mode Operation............................................................................................................. 262
23.10. Synchronization........................................................................................................................262
23.11. Debug Operation......................................................................................................................262
23.12. Register Summary................................................................................................................... 263
23.13. Register Description.................................................................................................................263
24. USART - Universal Synchronous and Asynchronous Receiver and Transmitter................................280
24.1. Features...................................................................................................................................280
24.2. Overview.................................................................................................................................. 280
24.3. Functional Description..............................................................................................................281
24.4. Register Summary....................................................................................................................296
24.5. Register Description.................................................................................................................296
25. SPI - Serial Peripheral Interface..........................................................................................................313
25.1. Features...................................................................................................................................313
25.2. Overview.................................................................................................................................. 313
25.3. Functional Description..............................................................................................................314
25.4. Register Summary....................................................................................................................321
25.5. Register Description.................................................................................................................321
26. TWI - Two-Wire Interface.................................................................................................................... 328
26.1. Features...................................................................................................................................328
26.2. Overview.................................................................................................................................. 328
26.3. Functional Description..............................................................................................................329
26.4. Register Summary....................................................................................................................340
26.5. Register Description.................................................................................................................340
27. CRCSCAN - Cyclic Redundancy Check Memory Scan......................................................................357
27.1. Features...................................................................................................................................357
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 9
ATtiny1624/1626/1627
27.2. Overview.................................................................................................................................. 357
27.3. Functional Description..............................................................................................................358
27.4. Register Summary....................................................................................................................361
27.5. Register Description.................................................................................................................361
28. CCL – Configurable Custom Logic......................................................................................................365
28.1. Features...................................................................................................................................365
28.2. Overview.................................................................................................................................. 365
28.3. Functional Description..............................................................................................................367
28.4. Register Summary....................................................................................................................376
28.5. Register Description.................................................................................................................376
29. AC - Analog Comparator.....................................................................................................................386
29.1. Features...................................................................................................................................386
29.2. Overview.................................................................................................................................. 386
29.3. Functional Description..............................................................................................................387
29.4. Register Summary....................................................................................................................389
29.5. Register Description.................................................................................................................389
30. ADC - Analog-to-Digital Converter......................................................................................................395
30.1. Features...................................................................................................................................395
30.2. Overview.................................................................................................................................. 395
30.3. Functional Description..............................................................................................................396
30.4. Register Summary....................................................................................................................409
30.5. Register Description.................................................................................................................409
31. UPDI - Unified Program and Debug Interface.....................................................................................429
31.1. Features...................................................................................................................................429
31.2. Overview.................................................................................................................................. 429
31.3. Functional Description..............................................................................................................431
31.4. Register Summary....................................................................................................................451
31.5. Register Description.................................................................................................................451
32. Instruction Set Summary.....................................................................................................................462
33. Electrical Characteristics.....................................................................................................................463
33.1. Disclaimer.................................................................................................................................463
33.2. Absolute Maximum Ratings .....................................................................................................463
33.3. General Operating Ratings ......................................................................................................464
33.4. Power Considerations..............................................................................................................465
33.5. Power Consumption ................................................................................................................466
33.6. Wake-Up Time..........................................................................................................................467
33.7. Peripherals Power Consumption..............................................................................................468
33.8. BOD and POR Characteristics.................................................................................................469
33.9. External Reset Characteristics.................................................................................................470
33.10. Oscillators and Clocks..............................................................................................................470
33.11. I/O Pin Characteristics..............................................................................................................472
33.12. USART..................................................................................................................................... 473
33.13. SPI........................................................................................................................................... 474
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 10
ATtiny1624/1626/1627
33.14. TWI...........................................................................................................................................475
33.15. VREF........................................................................................................................................478
33.16. ADC..........................................................................................................................................479
33.17. TEMPSENSE........................................................................................................................... 481
33.18. AC............................................................................................................................................ 481
33.19. UPDI.........................................................................................................................................482
33.20. Programming Time...................................................................................................................483
34. Typical Characteristics........................................................................................................................ 484
34.1. Power Consumption.................................................................................................................484
34.2. GPIO........................................................................................................................................ 484
34.3. VREF Characteristics...............................................................................................................491
34.4. BOD Characteristics.................................................................................................................491
34.5. ADC Characteristics.................................................................................................................494
34.6. TEMPSENSE Characteristics.................................................................................................. 494
34.7. AC Characteristics....................................................................................................................494
34.8. OSC20M Characteristics..........................................................................................................495
34.9. OSCULP32K Characteristics................................................................................................... 497
35. Ordering Information........................................................................................................................... 498
36. Package Drawings.............................................................................................................................. 500
36.1. Online Package Drawings........................................................................................................500
36.2. 14-Pin SOIC.............................................................................................................................501
36.3. 14-Pin TSSOP..........................................................................................................................504
36.4. 20-Pin SOIC.............................................................................................................................507
36.5. 20-Pin SSOP............................................................................................................................510
36.6. 20-Pin VQFN............................................................................................................................512
36.7. 24-Pin VQFN............................................................................................................................515
37. Data Sheet Revision History............................................................................................................... 518
37.1. Rev.A - 07/2020........................................................................................................................518
The Microchip Website...............................................................................................................................519
Product Change Notification Service..........................................................................................................519
Customer Support...................................................................................................................................... 519
Product Identification System.....................................................................................................................520
Microchip Devices Code Protection Feature.............................................................................................. 520
Legal Notice............................................................................................................................................... 520
Trademarks................................................................................................................................................ 521
Quality Management System..................................................................................................................... 521
Worldwide Sales and Service.....................................................................................................................522
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 11
1. Block Diagram
I
N
/
O
U
T
D
A
T
A
B
U
S
Clock generation
BUS Matrix
CPU
USARTn
SPIn
TWIn
CCL
ADCn
TCAn
TCBn
ACn
AINPm
AINNm
OUT
AINm
WOm
RXD
TXD
XCK
XDIR
MISO
MOSI
SCK
SS
SDA
SCL
PORTS
System
Management
SLPCTRL
RSTCTRL
CLKCTRL
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
UPDI
CRC
SRAM
OSC20M
OSCULP32K
XOSC32K
BOD
POR
WDT
CPUINT
M M
S
M
S
S
RTC
OCD
UPDI / RESET
EVOUTx
TOSC2
TOSC1
S
EXTCLK
LUTn_INm
LUTn_OUT
WO
CLKOUT
Pxn
GPIOR
EVSYS
VLM
VREG
VDD
NVMCTRL
Flash
EEPROM
VREFA
VREF
PORTMUX
PGA
Detectors/power
control
ATtiny1624/1626/1627
Block Diagram
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 12
2. Pinout
1
2
3
4
5
6
7 8
9
13
10
11
12
14
VDD GND
PA0 (UPDI/RESET)
PA1
PA2
PA3 (EXTCLK)PA4
PA5
PA7
PA6
PB0
PB1
(TOSC1) PB3
(TOSC2) PB2
Power
Power Supply
Ground
Functionality
Programming/Debug
Clock/Crystal
Pin on VDD Power Domain
Analog Function
2.1 14-Pin SOIC, TSSOP
ATtiny1624/1626/1627
Pinout
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 13
2.2 20-Pin SOIC, SSOP
1
2
3
4
5
6
7
13
11
12
14
VDD GND
PA1
PA2
PA3 (EXTCLK)PA4
PA5
PA7
PA6
PB0
8
9
10
15
20
19
18
17
16
PB1
PB4
PB5
PC0
PC2
PC3
PC1
PA0 (UPDI/RESET)
(TOSC1) PB3
(TOSC2) PB2
Power
Power Supply
Ground
Functionality
Programming/Debug
Clock/Crystal
Pin on VDD Power Domain
Analog Function
ATtiny1624/1626/1627
Pinout
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 14
2.3 20-Pin VQFN
1
2
3
4
5
6
7
8
20
19
18
179
13
14
15
1610
11
12
PA0 (UPDI/RESET)
PA1
PA4
PA7
PA6
PB0
PB1
PB3 (TOSC1)
PB4
PB5
PC2
PC3
PA5
GND
VDD
PB2 (TOSC2)
PA2 PC0
PC1
Power
Power Supply
Ground
Functionality
Programming/Debug
Clock/Crystal
Pin on VDD Power Domain
Analog Function
ATtiny1624/1626/1627
Pinout
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 15
2.4 24-Pin VQFN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
PA0 (UPDI
/RESET)
PA1
PC3
PC2
PA2
PA4
PA5
PA7
PA6
PC5
PC4
PC0
PC1
GND
VDD
PB4
PB5
PB6
PB7
PB0
PB1
PB3 (TOSC1)
PB2 (TOSC2)
Power
Power Supply
Ground
Functionality
Programming/Debug
Clock/Crystal
Pin on VDD Power Domain
Analog Function
Digital Function Only
ATtiny1624/1626/1627
Pinout
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 16
ATtiny1624/1626/1627
I/O Multiplexing and Considerations
3. I/O Multiplexing and Considerations
3.1 I/O Multiplexing
Table 3-1. PORT Function Multiplexing
Pin
Other/Special ADC0
Name
(1,2)
VQFN 24-pin
VQFN 20-pin
SSOP/SOIC 20-pin
23 19 16 10 PA0 RESET
24 20 17 11 PA1 AIN1 TXD
1 1 18 12 PA2 EVOUTA AIN2 RxD
2 2 19 13 PA3 EXTCLK AIN3 XCK
3 3 20 14 GND
4 4 1 1 VDD
5 5 2 2 PA4 AIN4 XDIR
6 6 3 3 PA5 VREFA AIN5 OUT WO5 0,WO LUT3-OUT
7 7 4 4 PA6 AIN6 AINN0
8 8 5 5 PA7 EVOUTA
9 PB7 EVOUTB
10 PB6 AINP3 LUT2-OUT
11 9 6 PB5 CLKOUT AIN8 AINP1 WO2
12 10 7 PB4 RESET
13 11 8 6 PB3 TOSC1 RxD WO0
14 12 9 7 PB2 TOSC2
15 13 10 8 PB1 AIN10 AINP2 XCK SDA WO1 LUT2-IN1
16 14 11 9 PB0 AIN11 AINN2 XDIR SCL WO0 LUT2-IN0
17 15 12 PC0 AIN12 XCK
18 16 13 PC1 AIN13 RxD
19 17 14 PC2 EVOUTC AIN14 TxD
20 18 15 PC3 AIN15 XDIR
21 PC4 WO4
22 PC5 WO5
TSSOP/SOIC 14-pin
UPDI
(4)
(4)
(4)
EVOUTB
(3)
AC0 USART0 USART1 SPI0 TWI0 TCA0 TCBn CCL
LUT0-IN0
(4)
(4)
(4)
AIN7 AINP0 LUT1-OUT
AIN9 AINN1 WO1
TxD WO2 LUT2-IN2
TXD MOSI LUT0-IN1
RXD MISO LUT0-IN2
XCK SCK WO3 1,WO
(4)
XDIR SS WO4 LUT0-OUT
(4)
(4)
(4)
(4)
(4)
(4)
(4)
SCK
MISO
MOSI
SS
(4)
(4)
(4)
(4)
WO3
(4)
(4)
(4)
0,WO
1,WO
LUT0-OUT
LUT2-OUT
(4)
LUT3-IN0
LUT1-OUT
LUT3-IN1
LUT3-IN2
LUT1-IN0
(4)
LUT1-IN1
LUT3-OUT
LUT1-IN2
(4)
(4)
(4)
Notes:
1. Pin names are of type Pxn with x being the PORT instance (A, B) and n the pin number. Notation for signals is
PORTx_PINn.
2. All pins can be used for external interrupt where pins Px2 and Px6 of each port have full asynchronous
detection. All pins can be used as event input.
3. AIN[15:8] can not be used as negative ADC input for differential measurements.
4. Alternative pin location. For selecting an alternative pin location, refer to the PORTMUX section.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 17
4. Hardware Guidelines
This section contains guidelines for designing or reviewing electrical schematics using AVR 8-bit microcontrollers.
The information presented here is a brief overview of the most common topics. More detailed information can be
found in application notes, listed in this section where applicable.
This section covers the following topics:
• General guidelines
• Connection for power supply
• Connection for
• Connection for UPDI (Unified Program and Debug Interface)
• Connection for external crystal oscillators
• Connection for VREF (external voltage reference)
4.1 General Guidelines
Unused pins must be soldered to their respective soldering pads. The soldering pads must not be connected to the
circuit.
The PORT pins are in their default state after Reset. Follow the recommendations in the PORT section to reduce
power consumption.
All values are given as typical values and serve only as a starting point for circuit design.
Refer to the following application notes for further information:
• AVR040 - EMC Design Considerations
• AVR042 - AVR Hardware Design Considerations
RESET
ATtiny1624/1626/1627
Hardware Guidelines
4.1.1 Special Consideration for Packages with Center Pad
Flat packages often come with an exposed pad located on the bottom, often referred to as the center pad or the
thermal pad. This pad is not electrically connected to the internal circuit of the chip, but it is mechanically bonded to
the internal substrate and serves as a thermal heat sink as well as providing added mechanical stability. This pad
must be connected to GND since the ground plane is the best heat sink (largest copper area) of the printed circuit
board (PCB).
4.2 Connection for Power Supply
The basics and details regarding the design of the power supply itself lie beyond the scope of these guidelines. For
more detailed information about this subject, see the application notes mentioned at the beginning of this section.
A decoupling capacitor must be placed close to the microcontroller for each supply pin pair (VDD, AVDD, or other
power supply pin and its corresponding GND pin). If the decoupling capacitor is placed too far from the
microcontroller, a high-current loop might form that will result in increased noise and increased radiated emission.
Each supply pin pair (power input pin and ground pin) must have separate decoupling capacitors.
It is recommended to place the decoupling capacitor on the same side of the PCB as the microcontroller. If space
does not allow it, the decoupling capacitor may be placed on the other side through a via, but make sure the distance
to the supply pin is kept as short as possible.
If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in
parallel to the decoupling capacitor described above. Place this second capacitor next to the primary decoupling
capacitor.
On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally
important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB
trace inductance.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 18
As mentioned at the beginning of this section, all values used in examples are typical values. The actual design may
VDD
GND
V
DD
C
1
C
2
Typical values (recommended):
C1: 100 nF (primary decoupling capacitor)
C2: 1 nF-10 nF (HF decoupling capacitor)
GND
C
1
SW
1
Typical values (Recommended):
C1: 100 nF (Filtering capacitor)
R1: 330Ω (Switch series resistance)
RESET
R
1
require other values.
4.2.1 Digital Power Supply
For larger pin count package types, there are several VDD and corresponding GND pins. All the VDD pins in the
microcontroller are internally connected. The same voltage must be applied to each of the VDD pins.
The following figure shows the recommendation for connecting a power supply to the VDD pin(s) of the device.
Figure 4-1. Recommended VDD Connection Circuit Schematic
ATtiny1624/1626/1627
Hardware Guidelines
4.3 Connection for RESET
The RESET pin on the device is active-low, and setting the pin low externally will result in a Reset of the device.
AVR devices feature an internal pull-up resistor on the RESET pin, and an external pull-up resistor is usually not
required.
The following figure shows the recommendation for connecting an external Reset switch to the device.
Figure 4-2. Recommended External Reset Circuit Schematic
A resistor in series with the switch can safely discharge the filtering capacitor. This prevents a current surge when
shorting the filtering capacitor, as this may cause a noise spike that can harm the system.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 19
4.4 Connection for UPDI Programming
VDD
GND
V
DD
C
1
Typical values (recommended):
C1: 100 nF (primary decoupling capacitor)
C2: 1 nF-10 nF (HF decoupling capacitor)
NC = Not Connected
1 2
3 4
5 6
UPDI
GND
NCNC
NC
VDD
UPDI
C
2
The standard connection for UPDI programming is a 100-mil 6-pin 2x3 header. Even though three pins are sufficient
for programming most AVR devices, it is recommended to use a 2x3 header since most programming tools are
delivered with 100-mil 6-pin 2x3 connectors.
The following figure shows the recommendation for connecting a UPDI connector to the device.
Figure 4-3. Recommended UPDI Programming Circuit Schematic
ATtiny1624/1626/1627
Hardware Guidelines
The decoupling capacitor between VDD and GND must be placed as close to the pin pair as possible. The
decoupling capacitor must be included even if the UPDI connector is not included in the circuit.
4.5 Connecting External Crystal Oscillators
The use of external oscillators and the design of oscillator circuits are not trivial. This is because there are many
variables: VDD, operating temperature range, crystal type and manufacture, loading capacitors, circuit layout, and
PCB material. Presented here are some typical guidelines to help with the basic oscillator circuit design.
• Even the best performing oscillator circuits and high-quality crystals will not perform well if the layout and
materials used during the assembly are not carefully considered
• The crystal circuit must be placed on the same side of the board as the device. Place the crystal circuit as close
to the respective oscillator pins as possible and avoid long traces. This will reduce parasitic capacitance and
increase immunity against noise and crosstalk. The load capacitors must be placed next to the crystal itself, on
the same side of the board. Any kind of sockets must be avoided.
• Place a grounded copper area around the crystal circuit to isolate it from surrounding circuits. If the circuit board
has two sides, the copper area on the bottom layer must be a solid area covering the crystal circuit. The copper
area on the top layer must surround the crystal circuit and tie to the bottom layer area using via(s).
• Do not run any signal traces or power traces inside the grounded copper area. Avoid routing digital lines,
especially clock lines, close to the crystal lines.
• If using a two-sided PCB, avoid any traces beneath the crystal. For a multilayer PCB, avoid routing signals
below the crystal lines.
• Dust and humidity will increase parasitic capacitance and reduce signal isolation. A protective coating is
recommended.
• Successful oscillator design requires good specifications of operating conditions, a component selection phase
with initial testing, and testing in actual operating conditions to ensure that the oscillator performs as desired
For more detailed information about oscillators and oscillator circuit design, read the following application notes:
• AN2648 - Selecting and Testing 32 KHz Crystal Oscillators for AVR® Microcontrollers
• AN949 - Making Your Oscillator Work
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 20
C
2
C
1
TOSC1
32.768 kHz
Crystal Oscillator
TOSC2
VREFA
GND
Voltage
Reference
+
-
C
1
ATtiny1624/1626/1627
4.5.1 Connection for XOSC32K (External 32.768 kHz Crystal Oscillator)
Ultra low-power 32.768 kHz oscillators typically dissipate significantly below 1 μW, and the current flowing in the
circuit is, therefore, extremely small. The crystal frequency is highly dependent on the capacitive load.
The following figure shows how to connect an external 32.768 kHz crystal oscillator.
Figure 4-4. Recommended External 32.768 kHz Oscillator Connection Circuit Schematic
Hardware Guidelines
4.6 Connection for External Voltage Reference
If the design includes the use of an external voltage reference, the general recommendation is to use a suitable
capacitor connected in parallel with the reference. The value of the capacitor depends on the nature of the reference
and the type of electrical noise that needs to be filtered out.
Additional filtering components may be needed. This depends on the type of external voltage reference used.
Figure 4-5. Recommended External Voltage Reference Connection
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 21
5. Conventions
5.1 Numerical Notation
Table 5-1. Numerical Notation
Symbol Description
165 Decimal number
0b0101
‘0101’ Binary numbers are given without prefix if unambiguous
0x3B24 Hexadecimal number
X Represents an unknown or do not care value
Z Represents a high-impedance (floating) state for either a
ATtiny1624/1626/1627
Conventions
Binary number
signal or a bus
5.2 Memory Size and Type
Table 5-2. Memory Size and Bit Rate
Symbol Description
KB kilobyte (210B = 1024B)
MB megabyte (220B = 1024 KB)
GB gigabyte (230B = 1024 MB)
b bit (binary ‘0’ or ‘1’)
B byte (8 bits)
1 kbit/s 1,000 bit/s rate
1 Mbit/s 1,000,000 bit/s rate
1 Gbit/s 1,000,000,000 bit/s rate
word 16-bit
5.3 Frequency and Time
Table 5-3. Frequency and Time
Symbol Description
kHz 1 kHz = 103 Hz = 1,000 Hz
MHz 1 MHz = 106 Hz = 1,000,000 Hz
GHz 1 GHz = 109 Hz = 1,000,000,000 Hz
ms 1 ms = 10-3s = 0.001s
µs 1 µs = 10-6s = 0.000001s
ns 1 ns = 10-9s = 0.000000001s
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 22
5.4 Registers and Bits
Table 5-4. Register and Bit Mnemonics
Symbol Description
R/W Read/Write accessible register bit. The user can read from and write to this bit.
R Read-only accessible register bit. The user can only read this bit. Writes will be ignored.
W Write-only accessible register bit. The user can only write this bit. Reading this bit will return an
undefined value.
BITFIELD Bitfield names are shown in uppercase. Example: INTMODE.
BITFIELD[n:m] A set of bits from bit n down to m. Example: PINA[3:0] = {PINA3, PINA2, PINA1, PINA0}.
Reserved Reserved bits, bit fields, and bit field values are unused and reserved for future use. For
compatibility with future devices, always write reserved bits to ‘0’ when the register is written.
Reserved bits will always return zero when read.
PERIPHERALn If several instances of the peripheral exist, the peripheral name is followed by a single number to
identify one instance. Example: USARTn is the collection of all instances of the USART module,
while USART3 is one specific instance of the USART module.
ATtiny1624/1626/1627
Conventions
PERIPHERALx If several instances of the peripheral exist, the peripheral name is followed by a single capital
letter (A-Z) to identify one instance. Example: PORTx is the collection of all instances of the
PORT module, while PORTB is one specific instance of the PORT module.
Reset Value of a register after a Power-on Reset. This is also the value of registers in a peripheral after
performing a software Reset of the peripheral, except for the Debug Control registers.
SET/CLR/TGL Registers with SET/CLR/TGL suffix allow the user to clear and set bits in a register without doing
a read-modify-write operation.
Each SET/CLR/TGL register is paired with the register it is affecting. Both registers in a register
pair return the same value when read.
Example: In the PORT peripheral, the OUT and OUTSET registers form such a register pair. The
contents of OUT will be modified by a write to OUTSET. Reading OUT and OUTSET will return
the same value.
Writing a ‘1’ to a bit in the CLR register will clear the corresponding bit in both registers.
Writing a ‘1’ to a bit in the SET register will set the corresponding bit in both registers.
Writing a ‘1’ to a bit in the TGL register will toggle the corresponding bit in both registers.
5.4.1 Addressing Registers from Header Files
In order to address registers in the supplied C header files, the following rules apply:
1. A register is identified by <peripheral_instance_name>.<register_name>, e.g., CPU.SREG, USART2.CTRLA,
or PORTB.DIR.
2. The peripheral name is given in the “Peripheral Address Map” in the “Peripherals and Architecture” section.
3. <peripheral_instance_name> is obtained by substituting any n or x in the peripheral name with the correct
instance identifier.
4. When assigning a predefined value to a peripheral register, the value is constructed following the rule:
<peripheral_name>_<bit_field_name>_<bit_field_value>_gc
<peripheral_name> is <peripheral_instance_name>, but remove any instance identifier.
<bit_field_value> can be found in the “Name” column in the tables in the Register Description sections
describing the bit fields of the peripheral registers.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 23
Example 5-1. Register Assignments
V
REF
Input Voltage
Ideal ADC
Actual ADC
Offset
Error
// EVSYS channel 0 is driven by TCB3 OVF event
EVSYS.CHANNEL0 = EVSYS_CHANNEL0_TCB3_OVF_gc;
// USART0 RXMODE uses Double Transmission Speed
USART0.CTRLB = USART_RXMODE_CLK2X_gc;
Note: For peripherals with different register sets in different modes, <peripheral_instance_name> and
<peripheral_name> must be followed by a mode name, for example:
// TCA0 in Normal Mode (SINGLE) uses waveform generator in frequency mode
TCA0.SINGLE.CTRL=TCA_SINGLE_WGMODE_FRQ_gc;
5.5 ADC Parameter Definitions
An ideal n-bit single-ended ADC converts a voltage linearly between GND and V
code is read as ‘0’, and the highest code is read as ‘2n-1’. Several parameters describe the deviation from the ideal
behavior:
Offset Error The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5
LSb). Ideal value: 0 LSb.
Figure 5-1. Offset Error
ATtiny1624/1626/1627
Conventions
in 2n steps (LSb). The lowest
REF
Gain Error After adjusting for offset, the gain error is found as the deviation of the last transition (e.g.,
© 2020 Microchip Technology Inc.
0x3FE to 0x3FF for a 10-bit ADC) compared to the ideal transition (at 1.5 LSb below
maximum). Ideal value: 0 LSb.
DS40002234A-page 24
Preliminary Datasheet
Figure 5-2. Gain Error
V
REF
Input Voltage
Ideal ADC
Actual ADC
Gain
Error
V
Input Voltage
Ideal ADC
Actual ADC
INL
0x3FF
0x000
0
V
Input Voltage
DNL
1 LSb
ATtiny1624/1626/1627
Conventions
Integral
Nonlinearity (INL)
Differential
Nonlinearity (DNL)
After adjusting for offset and gain error, the INL is the maximum deviation of an actual
transition compared to an ideal transition for any code. Ideal value: 0 LSb.
Figure 5-3. Integral Nonlinearity
The maximum deviation of the actual code width (the interval between two adjacent
transitions) from the ideal code width (1 LSb). Ideal value: 0 LSb.
Figure 5-4. Differential Nonlinearity
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 25
ATtiny1624/1626/1627
Conventions
Quantization Error Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSb wide) will code to the same value. Always ±0.5 LSb.
Absolute Accuracy The maximum deviation of an actual (unadjusted) transition compared to an ideal transition
for any code. This is the compound effect of all errors mentioned before. Ideal value: ±0.5
LSb.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 26
6. AVR® CPU
6.1 Features
• 8-bit, High-Performance AVR RISC CPU:
– 135 instructions
– Hardware multiplier
• 32 8-bit Registers Directly Connected to the ALU
• Stack in RAM
• Stack Pointer Accessible in I/O Memory Space
• Direct Addressing of up to 64 KB of Unified Memory
• Efficient Support for 8-, 16-, and 32-bit Arithmetic
• Configuration Change Protection for System-Critical Features
• Native On-Chip Debugging (OCD) Support:
– Two hardware breakpoints
– Change of flow, interrupt, and software breakpoints
– Run-time read-out of Stack Pointer (SP) register, Program Counter (PC), and Status Register (SREG)
– Register file read- and writable in Stopped mode
ATtiny1624/1626/1627
AVR® CPU
6.2 Overview
All AVR devices use the AVR 8-bit CPU. The CPU is able to access memories, perform calculations, control
peripherals, and execute instructions in the program memory. Interrupt handling is described in a separate section.
6.3 Architecture
To maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses for
program and data. Instructions in the program memory are executed with a single-level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions
to be executed on every clock cycle.
Refer to the Instruction Set Summary section for a summary of all AVR instructions.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 27
Figure 6-1. AVR® CPU Architecture
Register file
Flash Program
Memory
Data Memory
ALU
R0R1
R2R3
R4R5
R6R7
R8R9
R10R11
R12R13
R14R15
R16R17
R18R19
R20R21
R22R23
R24R25
R26 (XL)R27 (XH)
R28 (YL)R29 (YH)
R30 (ZL)R31 (ZH)
Stack
Pointer
Program
Counter
Instruction
Register
Instruction
Decode
Status
Register
ATtiny1624/1626/1627
AVR® CPU
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 28
6.4 Arithmetic Logic Unit (ALU)
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between working registers, or between a
constant and a working register. Also, single-register operations can be executed.
The ALU operates in a direct connection with all the 32 general purpose working registers in the register file.
Arithmetic operations between working registers or between a working register and an immediate operand are
executed in a single clock cycle, and the result is stored in the register file. After an arithmetic or logic operation, the
Status Register (CPU.SREG) is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic are supported, and the instruction set allows for efficient implementation of the 32-bit arithmetic. The
hardware multiplier supports signed and unsigned multiplication and fractional formats.
6.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports
different variations of signed and unsigned integer and fractional numbers:
• Multiplication of signed/unsigned integers
• Multiplication of signed/unsigned fractional numbers
• Multiplication of a signed integer with an unsigned integer
• Multiplication of a signed fractional number with an unsigned fractional number
A multiplication takes two CPU clock cycles.
ATtiny1624/1626/1627
AVR® CPU
6.5 Functional Description
6.5.1 Program Flow
After being reset, the CPU will execute instructions from the lowest address in the Flash program memory, 0x0000.
The Program Counter (PC) addresses the next instruction to be fetched.
The program flow is supported by conditional and unconditional change of flow instructions, capable of addressing
the whole address space directly. Most AVR instructions use a 16-bit word format, and a limited number use a 32-bit
format.
During interrupts and subroutine calls, the return address PC is stored on the stack as a word pointer. The stack is
allocated in the general data SRAM, and consequently, the stack size is only limited by the total SRAM size and the
usage of the SRAM. After the Stack Pointer (SP) is reset, it points to the highest address in the internal SRAM. The
SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas.
The data SRAM can easily be accessed through the five different Addressing modes supported by the AVR CPU.
6.5.2 Instruction Execution Timing
The AVR CPU is clocked by the CPU clock, CLK_CPU. No internal clock division is applied. The figure below shows
the parallel instruction fetches and executions enabled by the Harvard architecture and the fast-access register file
concept. This is the basic pipelining concept enabling up to 1 MIPS/MHz performance with high efficiency.
Figure 6-2. The Parallel Instruction Fetches and Executions
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU operation
using two register operands is executed, and the result is stored in the destination register.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 29
Figure 6-3. Single Cycle ALU Operation
Total Execution Time
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
6.5.3 Status Register
The Status Register (CPU.SREG) contains information about the result of the most recently executed arithmetic or
logic instructions. This information can be used for altering the program flow to perform conditional operations.
CPU.SREG is updated after all ALU operations, as specified in the Instruction Set Summary section. This will, in
many cases, remove the need for using the dedicated compare instructions, resulting in a faster and more compact
code. CPU.SREG is not automatically stored or restored when entering or returning from an Interrupt Service Routine
(ISR). Therefore, maintaining the Status Register between context switches must be handled by user-defined
software. CPU.SREG is accessible in the I/O memory space.
6.5.4 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. Also, it can be used for storing
temporary data. The Stack Pointer (SP) always points to the top of the stack. The SP is defined by the Stack Pointer
bits in the Stack Pointer register (CPU.SP). The CPU.SP is implemented as two 8-bit registers that are accessible in
the I/O memory space.
Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from higher to
lower memory locations. This means that pushing data onto the stack decreases the SP, and popping data off the
stack increases the SP. The SP is automatically set to the highest address of the internal SRAM after being reset. If
the stack is changed, it must be set to point above the SRAM start address (see the SRAM Data Memory section in
the Memories chapter for the SRAM start address), and it must be defined before any subroutine calls are executed
and before interrupts are enabled. See the table below for SP details.
Table 6-1. Stack Pointer Instructions
ATtiny1624/1626/1627
AVR® CPU
Instruction Stack Pointer Description
PUSH
Decremented by 1 Data are pushed onto the stack
CALL
ICALL
Decremented by 2 A return address is pushed onto the stack with a subroutine call or interrupt
RCALL
POP
RET RETI
Incremented by 1 Data are popped from the stack
Incremented by 2
A return address is popped from the stack with a return from subroutine or return
from interrupt
During interrupts or subroutine calls, the return address is automatically pushed on the stack as a word pointer, and
the SP is decremented by two. The return address consists of two bytes and the Least Significant Byte (LSB) is
pushed on the stack first (at the higher address). As an example, a byte pointer return address of 0x0006 is saved on
the stack as 0x0003 (shifted one bit to the right), pointing to the fourth 16-bit instruction word in the program memory.
The return address is popped off the stack with RETI (when returning from interrupts) and RET (when returning from
subroutine calls), and the SP is incremented by two.
The SP is decremented by ‘1’ when data are pushed on the stack with the PUSH instruction, and incremented by ‘1’
when data are popped off the stack using the POP instruction.
To prevent corruption when updating the SP from software, a write to SPL will automatically disable interrupts for up
to four instructions or until the next I/O memory write, whichever comes first.
© 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002234A-page 30
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