Page 1
ATmega328PB
AVR® Microcontroller with Core Independent Peripherals
and PicoPower® Technology
Introduction
The picoPower® ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves
throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed.
Features
High Performance, Low-Power AVR® 8-bit Microcontroller Family
• Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-Chip 2-Cycle Multiplier
• High Endurance Nonvolatile Memory Segments
– 32 KB of In-System Self-Programmable Flash program memory
– 1 KB EEPROM
– 2 KB Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Peripheral Features
– Peripheral Touch Controller (PTC)
• Capacitive Touch Buttons, Sliders, and Wheels
• 24 Self-Cap Channels and 144 Mutual Cap Channels
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode
– Real-Time Counter with Separate Oscillator
– Ten PWM Channels
– 8-channel 10-bit ADC
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 1
Page 2
ATmega328PB
– Two Programmable Serial USARTs
– Two Master/Slave SPI Serial Interfaces
– Two Byte-Oriented Two-Wire Serial Interfaces (Philips I2C Compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-Chip Analog Comparator
– Interrupt and Wake-Up on Pin Change
• Special Microcontroller Features
– Power-On Reset and Programmable Brown-Out Detection
– Internal 8 MHz Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended
Standby
– Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failure
– Individual Serial Number to Represent a Unique ID
• I/O and Packages
– 27 Programmable I/O Lines
– 32-pin TQFP and 32-pin QFN /MLF
• Operating Voltage:
– 1.8 - 5.5V
• Temperature Range:
– -40°C to 105°C
• Speed Grade:
– 0 - 4 MHz @ 1.8 - 5.5V
– 0 - 10 MHz @ 2.7 - 5.5V
– 0 - 20 MHz @ 4.5 - 5.5V
• Power Consumption at 1 MHz, 1.8V, 25°C
– Active Mode: 0.24 mA
– Power-Down Mode: 0.2 μA
– Power-Save Mode: 1.3 μA (Including 32 kHz RTC)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 2
Page 3
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description...............................................................................................................10
2. Configuration Summary........................................................................................... 11
3. Ordering Information................................................................................................12
4. Block Diagram......................................................................................................... 13
5. Pin Configurations................................................................................................... 14
5.1. Pin Descriptions......................................................................................................................... 15
6. I/O Multiplexing........................................................................................................18
7. Resources............................................................................................................... 20
8. About Code Examples.............................................................................................21
9. AVR CPU Core........................................................................................................ 22
9.1. Overview.................................................................................................................................... 22
9.2. ALU – Arithmetic Logic Unit....................................................................................................... 23
9.3. Status Register...........................................................................................................................23
9.4. General Purpose Register File...................................................................................................26
9.5. Stack Pointer..............................................................................................................................27
9.6. Instruction Execution Timing...................................................................................................... 29
9.7. Reset and Interrupt Handling..................................................................................................... 30
10. AVR Memories.........................................................................................................33
10.1. Overview.................................................................................................................................... 33
10.2. In-System Reprogrammable Flash Program Memory................................................................33
10.3. SRAM Data Memory.................................................................................................................. 34
10.4. EEPROM Data Memory............................................................................................................. 35
10.5. I/O Memory.................................................................................................................................36
10.6. Register Description................................................................................................................... 37
11. System Clock and Clock Options............................................................................ 46
11.1. Clock Systems and Their Distribution........................................................................................ 46
11.2. Clock Sources............................................................................................................................ 47
11.3. Low-Power Crystal Oscillator..................................................................................................... 49
11.4. Low Frequency Crystal Oscillator...............................................................................................50
11.5. Calibrated Internal RC Oscillator................................................................................................52
11.6. 128 kHz Internal Oscillator......................................................................................................... 53
11.7. External Clock............................................................................................................................ 54
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 3
Page 4
ATmega328PB
11.8. Clock Output Buffer....................................................................................................................54
11.9. Timer/Counter Oscillator.............................................................................................................55
11.10. System Clock Prescaler............................................................................................................. 55
11.11. Register Description................................................................................................................... 55
12. CFD - Clock Failure Detection mechanism............................................................. 59
12.1. Overview.................................................................................................................................... 59
12.2. Features..................................................................................................................................... 59
12.3. Operations..................................................................................................................................59
12.4. Timing Diagram.......................................................................................................................... 61
12.5. Register Description................................................................................................................... 61
13. Power Management and Sleep Modes................................................................... 63
13.1. Overview.................................................................................................................................... 63
13.2. Sleep Modes.............................................................................................................................. 63
13.3. BOD Disable...............................................................................................................................64
13.4. Idle Mode....................................................................................................................................64
13.5. ADC Noise Reduction Mode...................................................................................................... 64
13.6. Power-Down Mode.....................................................................................................................65
13.7. Power-Save Mode......................................................................................................................65
13.8. Standby Mode............................................................................................................................ 66
13.9. Extended Standby Mode............................................................................................................66
13.10. Power Reduction Registers........................................................................................................66
13.11. Minimizing Power Consumption.................................................................................................66
13.12. Register Description...................................................................................................................68
14. System Control and Reset.......................................................................................74
14.1. Resetting the AVR......................................................................................................................74
14.2. Reset Sources............................................................................................................................74
14.3. Power-on Reset..........................................................................................................................75
14.4. External Reset............................................................................................................................76
14.5. Brown-out Detection...................................................................................................................76
14.6. Watchdog System Reset............................................................................................................77
14.7. Internal Voltage Reference.........................................................................................................77
14.8. Watchdog Timer......................................................................................................................... 78
14.9. Register Description................................................................................................................... 80
15. INT - Interrupts........................................................................................................ 84
15.1. Interrupt Vectors in ATmega328PB............................................................................................ 84
15.2. Register Description................................................................................................................... 85
16. EXTINT - External Interrupts................................................................................... 88
16.1. Pin Change Interrupt Timing.......................................................................................................88
16.2. Register Description................................................................................................................... 89
17. I/O-Ports.................................................................................................................. 99
17.1. Overview.................................................................................................................................... 99
17.2. Ports as General Digital I/O......................................................................................................100
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 4
Page 5
ATmega328PB
17.3. Alternate Port Functions...........................................................................................................103
17.4. Register Description................................................................................................................. 118
18. TC0 - 8-bit Timer/Counter0 with PWM...................................................................133
18.1. Features................................................................................................................................... 133
18.2. Overview.................................................................................................................................. 133
18.3. Timer/Counter Clock Sources.................................................................................................. 135
18.4. Counter Unit............................................................................................................................. 135
18.5. Output Compare Unit............................................................................................................... 136
18.6. Compare Match Output Unit.....................................................................................................138
18.7. Modes of Operation..................................................................................................................140
18.8. Timer/Counter Timing Diagrams.............................................................................................. 144
18.9. Register Description................................................................................................................. 146
19. TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM.................................................158
19.1. Features................................................................................................................................... 158
19.2. Overview.................................................................................................................................. 158
19.3. Accessing 16-bit Timer/Counter Registers...............................................................................159
19.4. Timer/Counter Clock Sources.................................................................................................. 162
19.5. Counter Unit............................................................................................................................. 162
19.6. Input Capture Unit.................................................................................................................... 163
19.7. Compare Match Output Unit.....................................................................................................165
19.8. Output Compare Units..............................................................................................................166
19.9. Modes of Operation..................................................................................................................168
19.10. Timer/Counter Timing Diagrams.............................................................................................. 175
19.11. Register Description.................................................................................................................177
20. Timer/Counter 0, 1, 3, 4 Prescalers.......................................................................214
20.1. Internal Clock Source............................................................................................................... 214
20.2. Prescaler Reset........................................................................................................................214
20.3. External Clock Source..............................................................................................................214
20.4. Register Description................................................................................................................. 216
21. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation...................218
21.1. Features................................................................................................................................... 218
21.2. Overview.................................................................................................................................. 218
21.3. Timer/Counter Clock Sources.................................................................................................. 220
21.4. Counter Unit............................................................................................................................. 220
21.5. Output Compare Unit............................................................................................................... 221
21.6. Compare Match Output Unit.....................................................................................................223
21.7. Modes of Operation..................................................................................................................224
21.8. Timer/Counter Timing Diagrams.............................................................................................. 228
21.9. Asynchronous Operation of Timer/Counter2............................................................................229
21.10. Timer/Counter Prescaler.......................................................................................................... 231
21.11. Register Description................................................................................................................. 231
22. OCM - Output Compare Modulator....................................................................... 246
22.1. Overview.................................................................................................................................. 246
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 5
Page 6
ATmega328PB
22.2. Description............................................................................................................................... 246
23. SPI – Serial Peripheral Interface........................................................................... 248
23.1. Features................................................................................................................................... 248
23.2. Overview.................................................................................................................................. 248
23.3. SS Pin Functionality................................................................................................................. 252
23.4. Data Modes..............................................................................................................................252
23.5. Register Description................................................................................................................. 253
24. USART - Universal Synchronous Asynchronous Receiver Transceiver................262
24.1. Features................................................................................................................................... 262
24.2. Overview.................................................................................................................................. 262
24.3. Block Diagram.......................................................................................................................... 262
24.4. Clock Generation......................................................................................................................263
24.5. Frame Formats.........................................................................................................................266
24.6. USART Initialization................................................................................................................. 267
24.7. Data Transmission – The USART Transmitter......................................................................... 268
24.8. Data Reception – The USART Receiver.................................................................................. 270
24.9. Asynchronous Data Reception.................................................................................................273
24.10. Multi-Processor Communication Mode.................................................................................... 277
24.11. Examples of Baud Rate Setting............................................................................................... 278
24.12. Register Description.................................................................................................................281
25. USARTSPI - USART in SPI Mode.........................................................................291
25.1. Features................................................................................................................................... 291
25.2. Overview.................................................................................................................................. 291
25.3. Clock Generation......................................................................................................................291
25.4. SPI Data Modes and Timing.....................................................................................................292
25.5. Frame Formats.........................................................................................................................292
25.6. Data Transfer............................................................................................................................294
25.7. AVR USART MSPIM vs. AVR SPI............................................................................................295
25.8. Register Description................................................................................................................. 296
26. TWI - Two-Wire Serial Interface............................................................................ 297
26.1. Features................................................................................................................................... 297
26.2. Two-Wire Serial Interface Bus Definition..................................................................................297
26.3. Data Transfer and Frame Format.............................................................................................298
26.4. Multi-Master Bus Systems, Arbitration, and Synchronization...................................................301
26.5. Overview of the TWI Module.................................................................................................... 303
26.6. Using the TWI...........................................................................................................................305
26.7. Transmission Modes................................................................................................................ 308
26.8. Multi-Master Systems and Arbitration...................................................................................... 326
26.9. Register Description................................................................................................................. 327
27. AC - Analog Comparator....................................................................................... 335
27.1. Overview.................................................................................................................................. 335
27.2. Analog Comparator Multiplexed Input...................................................................................... 335
27.3. Register Description................................................................................................................. 336
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 6
Page 7
ATmega328PB
28. ADC - Analog-to-Digital Converter........................................................................ 340
28.1. Features................................................................................................................................... 340
28.2. Overview.................................................................................................................................. 340
28.3. Starting a Conversion...............................................................................................................342
28.4. Prescaling and Conversion Timing...........................................................................................343
28.5. Changing Channel or Reference Selection.............................................................................. 345
28.6. ADC Noise Canceler................................................................................................................ 347
28.7. ADC Conversion Result........................................................................................................... 350
28.8. Temperature Measurement...................................................................................................... 351
28.9. Register Description................................................................................................................. 351
29. PTC - Peripheral Touch Controller.........................................................................360
29.1. Features................................................................................................................................... 360
29.2. Overview.................................................................................................................................. 360
29.3. Block Diagram.......................................................................................................................... 361
29.4. Signal Description.................................................................................................................... 362
29.5. System Dependencies............................................................................................................. 362
29.6. Functional Description..............................................................................................................363
30. debugWIRE On-chip Debug System.....................................................................364
30.1. Features................................................................................................................................... 364
30.2. Overview.................................................................................................................................. 364
30.3. Physical Interface.....................................................................................................................364
30.4. Software Breakpoints............................................................................................................... 365
30.5. Limitations of debugWIRE........................................................................................................365
30.6. Register Description................................................................................................................. 365
31. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................367
31.1. Features................................................................................................................................... 367
31.2. Overview.................................................................................................................................. 367
31.3. Application and Boot Loader Flash Sections............................................................................367
31.4. Read-While-Write and No Read-While-Write Flash Sections...................................................368
31.5. Entering the Boot Loader Program...........................................................................................370
31.6. Boot Loader Lock Bits.............................................................................................................. 371
31.7. Addressing the Flash During Self-Programming...................................................................... 372
31.8. Self-Programming the Flash.....................................................................................................373
31.9. Register Description................................................................................................................. 381
32. MEMPROG - Memory Programming.....................................................................384
32.1. Program And Data Memory Lock Bits...................................................................................... 384
32.2. Fuse Bits.................................................................................................................................. 385
32.3. Signature Bytes........................................................................................................................387
32.4. Calibration Byte........................................................................................................................388
32.5. Serial Number.......................................................................................................................... 388
32.6. Page Size.................................................................................................................................390
32.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................390
32.8. Parallel Programming...............................................................................................................392
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 7
Page 8
ATmega328PB
32.9. Serial Downloading.................................................................................................................. 399
33. Electrical Characteristics....................................................................................... 405
33.1. Absolute Maximum Ratings......................................................................................................405
33.2. DC Characteristics................................................................................................................... 405
33.3. Power Consumption................................................................................................................. 407
33.4. Speed Grades.......................................................................................................................... 408
33.5. Clock Characteristics................................................................................................................409
33.6. System and Reset Characteristics........................................................................................... 410
33.7. SPI Timing Characteristics....................................................................................................... 411
33.8. Two-Wire Serial Interface Characteristics................................................................................ 412
33.9. ADC Characteristics................................................................................................................. 414
33.10. Parallel Programming Characteristics......................................................................................415
34. Typical Characteristics...........................................................................................418
34.1. Active Supply Current...............................................................................................................418
34.2. Idle Supply Current...................................................................................................................421
34.3. ATmega328PB Supply Current of I/O Modules........................................................................423
34.4. Power-Down Supply Current....................................................................................................424
34.5. Pin Pull-Up............................................................................................................................... 425
34.6. Pin Driver Strength................................................................................................................... 428
34.7. Pin Threshold and Hysteresis.................................................................................................. 430
34.8. BOD Threshold.........................................................................................................................433
34.9. Analog Comparator Offset........................................................................................................436
34.10. Internal Oscillator Speed..........................................................................................................437
34.11. Current Consumption of Peripheral Units.................................................................................440
34.12. Current Consumption in Reset and Reset Pulse Width........................................................... 443
35. Register Summary.................................................................................................445
36. Instruction Set Summary....................................................................................... 449
37. Packaging Information...........................................................................................454
37.1. 32A...........................................................................................................................................454
37.2. 32-Pin VQFN............................................................................................................................455
38. Errata.....................................................................................................................456
38.1. Rev. A.......................................................................................................................................456
38.2. Rev. B.......................................................................................................................................456
38.3. Rev. C - D.................................................................................................................................457
38.4. Rev. A - D.................................................................................................................................457
39. Revision History.....................................................................................................458
The Microchip Web Site.............................................................................................. 460
Customer Change Notification Service........................................................................460
Customer Support....................................................................................................... 460
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 8
Page 9
ATmega328PB
Microchip Devices Code Protection Feature............................................................... 460
Legal Notice.................................................................................................................461
Trademarks................................................................................................................. 461
Quality Management System Certified by DNV...........................................................462
Worldwide Sales and Service......................................................................................463
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 9
Page 10
1. Description
The ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves
throughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
The core combines a rich instruction set with 32 general purpose working registers. All the 32 registers
are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega328PB provides the following features: 32 KB of In-System Programmable Flash with ReadWhile-Write capabilities, 1 KB EEPROM, 2 KB SRAM, 27 general purpose I/O lines, 32 general purpose
working registers, five flexible Timer/Counters with compare modes, internal and external interrupts, two
serial programmable USART, two byte-oriented two-wire Serial Interface (I2C), two SPI serial ports, an 8channel 10-bit ADC in TQFP and QFN/MLF package, a programmable Watchdog Timer with internal
Oscillator, Clock failure detection mechanism, and six software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, USART, two-wire Serial Interface, SPI
port, and interrupt system to continue functioning. PTC with enabling up to 24 self-cap and 144 mutualcap sensors. The Power-Down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or hardware reset. In Power-Save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
Also ability to run PTC in Power-Save mode/wake-up on touch and Dynamic ON/OFF of PTC analog and
digital portion. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer, PTC, and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/
resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption.
ATmega328PB
Description
The device is manufactured using high-density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the ATmega328PB is a powerful microcontroller that
provides a highly flexible and cost-effective solution to many embedded control applications.
The ATmega328PB is supported by a full suite of program and system development tools including C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 10
Page 11
2. Configuration Summary
Features ATmega328PB
Pin count 32
Flash (KB) 32
SRAM (KB) 2
EEPROM (KB) 1
General Purpose I/O pins 27
SPI 2
TWI (I2C) 2
USART 2
ADC 10-bit 15 ksps
ADC channels 8
ATmega328PB
Configuration Summary
AC propagation delay 400 ns (Typical)
8-bit Timer/Counters 2
16-bit Timer/Counters 3
PWM channels 10
PTC Available
Clock Failure Detector (CFD) Available
Output Compare Modulator (OCM1C2) Available
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 11
Page 12
3. Ordering Information
ATmega328PB
Ordering Information
Speed [MHz] Power Supply [V] Ordering Code
(2)
20 1.8 - 5.5 ATmega328PB-AU
ATmega328PB-AUR
ATmega328PB-MU
ATmega328PB-MUR
ATmega328PB-AN
ATmega328PB-ANR
ATmega328PB-MN
ATmega328PB-MNR
Note:
1. This device can also be supplied in wafer form. Contact your local Microchip sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape & Reel.
(3)
(3)
(3)
(3)
Package
32A
32A
32MS1
32MS1
32A
32A
32MS1
32MS1
(1)
Operational Range
Industrial
(-40°C to 85°C)
Industrial
(-40°C to 105°C)
Package Type
32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32MS1 32-pad, 5.0x5.0x0.9 mm body, Lead Pitch 0.50 mm, Very-thin Fine pitch, Quad Flat No Lead Package
(VQFN)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 12
Page 13
4. Block Diagram
CPU
USART 0
SPI 1
ADC
ADC[7:0]
AREF
RxD0
TxD0
XCK0
MISO1
MOSI1
SCK1
SS1
I/O
PORTS
D
A
T
A
B
U
S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
debugWire
I
N
/
O
U
T
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI 0
AC
AIN0
AIN1
ACO
EEPROM
EEPROMIF
PTC
X[15:0]
Y[23:0]
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 3
(16-bit)
TC 4
(16-bit)
OC3A/B
T3
ICP3
OC4A/B
T4
ICP4
TC 2
(8-bit async)
TWI 0
TWI 1
SDA0
SCL0
SDA1
SCL1
USART 1
RxD1
TxD1
XCK1
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz
XOSC
External
clock
Power
Supervision
POR/BOD &
RESET
XTAL2 /
TOSC2
RESET
XTAL1 /
TOSC1
16MHz LP
XOSC
Crystal failure detection
PCINT[27:0]
INT[1:0]
T0
OC0A
OC0B
MISO0
MOSI0
SCK0
SS0
OC2A
OC2B
PB[7:0]
PC[6 :0]
PD[7:0]
PE[3:0]
PE[3:2], PC[5:0]
AREF
PB[5:0], PE[1:0], PD[7:0]
PB[5:0], PE[1:0], PD[7:0], PE[3:2], PC[5:0]
PE[3:0], PD[7:0], PC[6:0], PB[7:0]
PD3, PD2
PB1, PB2
PD5
PB0
PB3
PD3
PD0, PD2
PE3
PE2
PD1, PD2
PE1
PE0
PD0
PD1
PD4
PC0
PE3
PC1
PE2
PC4
PC5
PE0
PE1
PB4
PB3
PB5
PD4
PD6
PD5
PB4
PB3
PB5
PB2
SPIPROG
PARPROG
PD6
PD7
PE0
Figure 4-1. Block Diagram
ATmega328PB
Block Diagram
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 13
Page 14
5. Pin Configurations
1
2
3
4
32
31
30
29
28
27
26
5
6
7
8
24
23
22
21
20
19
18
17
25
9
10
11
12
13
14
15
16
PD0 (PTCXY/OC3A/RXD0)
PD1 (PTCXY/OC4A/TXD0)
PD2 (PTCXY/INT0/OC3B/OC4B)
PC6 (RESET)
PC2 (ADC2/PTCY)
PC3 (ADC3/PTCY)
PC4 (ADC4/PTCY/SDA0)
PC5 (ADC5/PTCY/SCL0)
PC0 (ADC0/PTCY/MISO1)
PC1 (ADC1/PTCY/SCK1)
GND
PE2 (ADC6/PTCY/ICP3/SS1)
AVCC
AREF
PE3 (ADC7/PTCY/T3/MOSI1)
(XCK0/T0/PTCXY) PD4
GND
VCC
(SDA1/ICP4/ACO/PTCXY) PE0
(SCL1/T4/PTCXY) PE1
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(PTCXY/AIN1) PD7
(OC1A/PTCXY) PB1
(SS0/OC1B/PTCXY) PB2
(MISO0/RXD1/PTCXY) PB4
(OC2B/INT1/PTCXY) PD3
(OC0B/T1/PTCXY) PD5
(OC0A/PTCXY/AIN0) PD6
(ICP1/CLKO/PTCXY) PB0
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
PB5 (PTCXY/XCK1/SCK0)
Figure 5-1. 32 TQFP Pinout ATmega328PB
ATmega328PB
Pin Configurations
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 14
Page 15
Figure 5-2. 32 VQFN Pinout ATmega328PB
1
2
3
4
32
31
30
29
28
27
26
5
6
7
8
24
23
22
21
20
19
18
17
25
9
10
11
12
13
14
15
16
PD0 (PTCXY/OC3A/RXD0)
PD1 (PTCXY/OC4A/TXD0)
PD2 (PTCXY/INT0/OC3B/OC4B)
PC6 (RESET)
PC2 (ADC2/PTCY)
PC3 (ADC3/PTCY)
PC4 (ADC4/PTCY/SDA0)
PC5 (ADC5/PTCY/SCL0)
PC0 (ADC0/PTCY/MISO1)
PC1 (ADC1/PTCY/SCK1)
GND
PE2 (ADC6/PTCY/ICP3/SS1)
AVCC
AREF
PE3 (ADC7/PTCY/T3/MOSI1)
(PTCXY/AIN1) PD7
(OC1A/PTCXY) PB1
(SS0/OC1B/PTCXY) PB2
(MISO0/RXD1/PTCXY) PB4
(OC0B/T1/PTCXY) PD5
(OC0A/PTCXY/AIN0) PD6
(ICP1/CLKO/PTCXY) PB0
(XCK0/T0/PTCXY) PD4
GND
VCC
(SDA1/ICP4/ACO/PTCXY) PE0
(SCL1/T4/PTCXY) PE1
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(OC2B/INT1/PTCXY) PD3
Bottom pad should be
soldered to ground
PB5 (PTCXY/XCK1/SCK0)
ATmega328PB
Pin Configurations
5.1 Pin Descriptions
5.1.1 VCC
Digital supply voltage pin.
5.1.2 GND
Ground.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 15
Page 16
5.1.3 Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated during a reset condition even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] input
for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
5.1.4 Port C (PC[5:0])
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The PC[5:0]
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated during a reset condition even if the clock is not running.
ATmega328PB
Pin Configurations
5.1.5 PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics
of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are
not guaranteed to generate a Reset.
The various special features of Port C are elaborated in the Alternate Functions of Port C section.
5.1.6 Port D (PD[7:0])
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated during a reset condition even if the clock is not running.
5.1.7 Port E (PE[3:0])
Port E is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port E
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
E pins are tri-stated during a reset condition even if the clock is not running.
5.1.8 AV
CC
AVCC is the supply voltage pin for the A/D Converter, PC[3:0], and PE[3:2]. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that PC[6:4] use digital supply voltage, VCC.
5.1.9 AREF
AREF is the analog reference pin for the A/D Converter.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 16
Page 17
5.1.10 ADC[7:6]
In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are
powered by the analog supply and serve as 10-bit ADC channels.
ATmega328PB
Pin Configurations
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 17
Page 18
ATmega328PB
I/O Multiplexing
6. I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively, it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
No
PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C USART I2C SPI
1 PD[3] INT1 PCINT19 X3 Y11 OC2B
2 PD[4] PCINT20 X4 Y12 T0 XCK0
3 PE[0] PCINT24 ACO X8 Y16 ICP4 SDA1
4 VCC
5 GND
6 PE[1] PCINT25 X9 Y17 T4 SCL1
7 PB[6] PCINT6 XTAL1/TOSC1
8 PB[7] PCINT7 XTAL2/TOSC2
9 PD[5] PCINT21 X5 Y13 OC0B / T1
10 PD[6] PCINT22 AIN0 X6 Y14 OC0A
11 PD[7] PCINT23 AIN1 X7 Y15
12 PB[0] PCINT0 X10 Y18 CLKO ICP1
13 PB[1] PCINT1 X11 Y19 OC1A
14 PB[2] PCINT2 X12 Y20 OC1B SS0
15 PB[3] PCINT3 X13 Y21 OC2A TXD1 MOSI0
16 PB[4] PCINT4 X14 Y22 RXD1 MISO0
17 PB[5] PCINT5 X15 Y23 XCK1 SCK0
18 AVCC
19 PE[2] PCINT26 ADC6 Y6 ICP3 SS1
20 AREF
21 GND
22 PE[3] PCINT27 ADC7 Y7 T3 MOSI1
23 PC[0] PCINT8 ADC0 Y0 MISO1
24 PC[1] PCINT9 ADC1 Y1 SCK1
25 PC[2] PCINT10 ADC2 Y2
26 PC[3] PCINT11 ADC3 Y3
27 PC[4] PCINT12 ADC4 Y4 SDA0
28 PC[5] PCINT13 ADC5 Y5 SCL0
29 PC[6]/RESET PCINT14
30 PD[0] PCINT16 X0 Y8 OC3A RXD0
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 18
Page 19
ATmega328PB
I/O Multiplexing
No PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C USART I2C SPI
31 PD[1] PCINT17 X1 Y9 OC4A TXD0
32 PD[2] INT0 PCINT18 X2 Y10 OC3B / OC4B
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 19
Page 20
7. Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
ATmega328PB
Resources
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 20
Page 21
8. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
ATmega328PB
About Code Examples
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 21
Page 22
9. AVR CPU Core
Register file
Flash program
memory
Program
counter
Instruction
register
Instruction
decode
Data memory
ALU
Status
register
R0R1
R2R3
R4R5
R6R7
R8R9
R10R11
R12R13
R14R15
R16R17
R18R19
R20R21
R22R23
R24R25
R26 (XL)R27 (XH)
R28 (YL)R29 (YH)
R30 (ZL)R31 (ZH)
Stack
pointer
9.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must, therefore, be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 9-1. Block Diagram of the AVR Architecture
ATmega328PB
AVR CPU Core
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the register file, the operation is executed, and the result is
stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space
addressing – enabling efficient address calculations. One of these address pointers can be used as an
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 22
Page 23
ATmega328PB
AVR CPU Core
address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit
X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided into two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the Stack
Pointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table.
The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, SPI, and
other I/O functions. The I/O memory can be accessed directly, or as the data space locations following
those of the register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
9.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide
a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction
Set Summary section for a detailed description.
Related Links
Instruction Set Summary
9.3 Status Register
The Status register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status register is updated after all ALU operations, as specified in the instruction set
reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 23
Page 24
ATmega328PB
AVR CPU Core
The Status register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 24
Page 25
ATmega328PB
AVR CPU Core
9.3.1 Status Register
Name: SREG
Offset: 0x5F
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x3F
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
I T H S V N Z C
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – I Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable register is cleared,
none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a
bit in T can be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry flag is useful in BCD
arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag
V. See the Instruction Set Description for detailed information.
Bit 3 – V Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 25
Page 26
Bit 1 – Z Zero Flag
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 0 – C Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
9.4 General Purpose Register File
The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the register file:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 9-2. AVR CPU General Purpose Working Registers
ATmega328PB
AVR CPU Core
Most of the instructions operating on the register file have direct access to all registers, and most of them
are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user data space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
9.4.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 26
Page 27
15
XH
XL
0
X-register
707
0
R27
R26
15
YH
YL
0
Y-register
707
0
R29
R28
15
ZH
ZL
0
Z-register
707
0
R31
R30
ATmega328PB
AVR CPU Core
Figure 9-3. The X-, Y-, and Z-registers
In the different addressing modes, these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary
9.5 Stack Pointer
The Stack is mainly used for storing temporary data, local variables, and return addresses after interrupts
and subroutine calls. The Stack is implemented as growing from higher to lower memory locations. The
Stack Pointer register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack
Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point
above start of the SRAM. See the table for Stack Pointer details.
Table 9-1. Stack Pointer Instructions
Instruction Stack Pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
POP Incremented by 1 Data is popped from the stack
RET
RETI
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
Incremented by 2 Return address is popped from the stack with return from subroutine or
interrupt
return from interrupt
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 27
Page 28
ATmega328PB
AVR CPU Core
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH register will not be present.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 28
Page 29
ATmega328PB
AVR CPU Core
9.5.1 Stack Pointer Register Low and High byte
Name: SPL and SPH
Offset: 0x5D
Reset: 0x4FF
Property: When addressing I/O Registers as data space the offset address is 0x3D
The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 15 14 13 12 11 10 9 8
Access
Reset 0 0 0 0 0 1 0 0
R R R R RW RW RW RW
SP11 SP10 SP9 SP8
Bit 7 6 5 4 3 2 1 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Access
Reset 1 1 1 1 1 1 1 1
RW RW RW RW RW RW RW RW
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – SP Stack Pointer Register
SPL and SPH are combined into SP.
Related Links
Accessing 16-bit Timer/Counter Registers
9.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clk
clock division is used. The figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power unit.
, directly generated from the selected clock source for the chip. No internal
CPU
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 29
Page 30
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
ATmega328PB
AVR CPU Core
Figure 9-4. The Parallel Instruction Fetches and Instruction Executions
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU
operation using two register operands is executed and the result is stored back to the destination register.
Figure 9-5. Single Cycle ALU Operation
9.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset vector
each have a separate program vector in the program memory space. All interrupts are assigned
individual enable bits, which must be written logic one together with the global interrupt enable bit in the
Status register in order to enable the interrupt. Depending on the program counter value, interrupts may
be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and interrupt
vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vectors
can be moved to the start of the boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset vector can be moved to the start of the boot Flash section by programming the
BOOTRST Fuse.
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction
– RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program
counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 30
Page 31
ATmega328PB
AVR CPU Core
hardware clears the corresponding interrupt flag. Interrupt flags can be cleared by writing a logic one to
the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt
enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI
instruction. The following example shows how this can be used to avoid interrupts during the timed
EEPROM write sequence.
Assembly Code Example
(1)
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
(1)
1. Refer to About Code Examples.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before
any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
(1)
(1)
1. Refer to About Code Examples.
Related Links
Memory Programming
Boot Loader Support – Read-While-Write Self-Programming
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 31
Page 32
About Code Examples
9.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After
four clock cycles, the program vector address for the actual interrupt handling routine is executed. During
this four clock cycle period, the program counter is pushed onto the stack. The vector is normally a jump
to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs
when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles.
This increase comes in addition to the start-up time from the selected sleep mode. A return from an
interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter
(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in
SREG is set.
ATmega328PB
AVR CPU Core
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 32
Page 33
10. AVR Memories
0x0000
0x3FFF
Program Memory
Application Flash Section
Boot Flash Section
10.1 Overview
This section describes the different memory types in the device. The AVR architecture has two main
memory spaces, the Data Memory and the Program Memory space. In addition, the device features an
EEPROM Memory for data storage. All memory spaces are linear and regular.
10.2 In-System Reprogrammable Flash Program Memory
The ATmega328PB contains 32 Kbytes on-chip in-system reprogrammable Flash memory for program
storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K x 16.
The ATmega328PB Program Counter (PC) is 14 bits wide, thus addressing the 16K program memory
locations. The operation of the Boot Program section and associated Boot Lock bits for software
protection are described in detail in Boot Loader Support – Read-While-Write Self-Programming. Refer to
Memory Programming for the description of Flash data serial downloading using the SPI pins.
ATmega328PB
AVR Memories
Constant tables can be allocated within the entire program memory address space, using the Load
Program Memory (LPM) instruction.
Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.
Figure 10-1. Program Memory Map ATmega328PB
Related Links
BTLDR - Boot Loader Support – Read-While-Write Self-Programming
MEMPROG - Memory Programming
Instruction Execution Timing
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 33
Page 34
10.3 SRAM Data Memory
Load/Store
IN/OUT
0x0000 – 0x001F
0x0100
0x08FF
160 Ext I/O registers
64 I/O registers
32 registers
Internal SRAM
(2048x8)
0x0020 – 0x005F
0x0060 – 0x00FF
0x0000 – 0x001F
The following figure shows how the device SRAM memory is organized.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in the Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 2303 data memory locations address both the register file, the I/O memory, extended I/O
memory, and the internal data SRAM. The first 32 locations address the register file, the next 64 location
the standard I/O memory, then 160 locations of extended I/O memory, and the next 2K locations address
the internal data SRAM.
The five different addressing modes for the data memory cover:
• Direct
– The direct addressing reaches the entire data space.
• Indirect with Displacement
– The indirect with displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.
• Indirect
– In the register file, registers R26 to R31 feature the indirect addressing pointer registers.
• Indirect with Pre-decrement
– The address registers X, Y, and Z are decremented.
• Indirect with Post-increment
– The address registers X, Y, and Z are incremented.
ATmega328PB
AVR Memories
10.3.1 Data Memory Access Times
The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 2 K bytes
of internal data SRAM in the device are all accessible through all these addressing modes.
Figure 10-2. Data Memory Map with 2048 Byte Internal Data SRAM
The internal data SRAM access is performed in two clk
cycles as described in the following Figure.
CPU
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 34
Page 35
Figure 10-3. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
ATmega328PB
AVR Memories
10.4 EEPROM Data Memory
The ATmega328PB contains 1 KB of data EEPROM memory. It is organized as a separate data space, in
which single bytes can be read and written. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address registers, the EEPROM Data register, and the
EEPROM Control register.
See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programming
mode.
Related Links
MEMPROG - Memory Programming
10.4.1 EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 10-2. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write
the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or
fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower
than specified as a minimum for the clock frequency used. Refer to Preventing EEPROM Corruption for
details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to
the description of the EEPROM Control register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction
is executed.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 35
Page 36
10.4.2 Preventing EEPROM Corruption
During periods of low V
the CPU and the EEPROM to operate properly. These issues are the same as for board level systems
using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular
write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself
can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done
by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not
match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset
occurs while a write operation is in progress, the write operation will be completed provided that the
power supply voltage is sufficient.
the EEPROM data can be corrupted because the supply voltage is too low for
CC,
10.5 I/O Memory
The I/O space definition of the device is shown in the Register Summary.
ATmega328PB
AVR Memories
All device I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the
LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working
registers and the I/O space. I/O registers within the address range 0x00-0x1F are directly bit-accessible
using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using
the SBIS and SBIC instructions.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00-0x3F must be used. When
addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space
from 0x60..0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O
memory addresses should never be written.
Some of the status flags are cleared by writing a '1' to them; this is described in the flag descriptions.
Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can, therefore, be used on registers containing such status flags. The CBI and SBI instructions work with
registers 0x00-0x1F only.
The I/O and peripherals control registers are explained in later sections.
Related Links
MEMPROG - Memory Programming
Register Summary
Instruction Set Summary
10.5.1 General Purpose I/O Registers
The device contains three general purpose I/O registers; General purpose I/O register 0/1/2 (GPIOR
0/1/2). These registers can be used for storing any information, and they are particularly useful for storing
global variables and status flags. General purpose I/O registers within the address range 0x00 - 0x1F are
directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 36
Page 37
10.6 Register Description
10.6.1 Accessing 16-Bit Registers
The AVR data bus is 8-bits wide, so accessing 16-bit registers requires atomic operations. These
registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the
8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the high byte of the 16-bit register must be written before the low byte. The high
byte is then written into the temporary register. When the low byte of the 16-bit register is written, the
temporary register is copied into the high byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low
byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register
in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the
temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when
reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit
register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when
writing or reading 16-bit registers.
ATmega328PB
AVR Memories
The temporary registers can be read and written directly from user software.
Note: For more information, refer to section Accessing 16-bit Timer/Counter registers in chapter 16-bit
Timer/Counter1 with PWM.
Related Links
Accessing 16-bit Timer/Counter Registers
About Code Examples
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 37
Page 38
10.6.2 EEPROM Address Register Low and High Byte
Name: EEARL and EEARH
Offset: 0x41 [ID-000004d0]
Reset: 0xXX
Property: When addressing as I/O Register: address offset is 0x21
The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For
more details on reading and writing 16-bit registers, refer to accessing 16-bit registers in the section
above.
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega328PB
AVR Memories
Bit 15 14 13 12 11 10 9 8
Access
Reset x x
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
EEAR[9:8]
R/W R/W
EEAR[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 9:0 – EEAR[9:0] EEPROM Address
The EEPROM Address Registers, EEARH and EEARL, specify the EEPROM address in the 1 KB
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023. The initial value
of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 38
Page 39
ATmega328PB
AVR Memories
10.6.3 EEPROM Data Register
Name: EEDR
Offset: 0x40 [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x20
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
EEDR[7:0]
Bits 7:0 – EEDR[7:0] EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in
the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data
read out from the EEPROM at the address given by EEAR.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 39
Page 40
ATmega328PB
AVR Memories
10.6.4 EEPROM Control Register
Name: EECR
Offset: 0x3F [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x1F
Bit 7 6 5 4 3 2 1 0
Access
Reset x x 0 0 x 0
EEPM[1:0] EERIE EEMPE EEPE EERE
R/W R/W R/W R/W R/W R/W
Bits 5:4 – EEPM[1:0] EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action will be triggered when
writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the
new value) or to split the erase and write operations into two different operations. The programming times
for the different modes are shown in the table below. While EEPE is set, any write to EEPMn will be
ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
Table 10-1. EEPROM Mode Bits
EEPM[1:0] Typ. Programming Time Operation
00 3.4ms Erase and Write in one operation (Atomic Operation)
01 1.8ms Erase Only
10 1.8ms Write Only
11 - Reserved for future use
Bit 3 – EERIE EEPROM Ready Interrupt Enable
Writing EERIE to '1' enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE to
zero disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEPE is
cleared. The interrupt will not be generated during EEPROM write or SPM.
Bit 2 – EEMPE EEPROM Master Write Enable
The EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written.
When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selected
address.
If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software,
hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an
EEPROM write procedure.
Bit 1 – EEPE EEPROM Write Enable
The EEPROM write enable signal EEPE is the write strobe to the EEPROM. When address and data are
correctly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bit
must be written to '1' before EEPE is written to '1', otherwise, no EEPROM write takes place. The
following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not
essential):
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 40
Page 41
CAUTION
ATmega328PB
AVR Memories
1. Wait until EEPE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a '1' to EEPE.
The EEPROM cannot be programmed during a CPU write to the Flash memory. The software must check
that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if
the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being
updated by the CPU, step 2 can be omitted.
An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master
Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another
EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted
EEPROM access to fail. It is recommended to have the global interrupt flag cleared during all
the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user
software can poll this bit and wait for a zero before writing the next byte. When EEPE has been
set, the CPU is halted for two cycles before the next instruction is executed.
Bit 0 – EERE EEPROM Read Enable
The EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address is
set up in the EEAR register, the EERE bit must be written to a '1' to trigger the EEPROM read. The
EEPROM read access takes one instruction, and the requested data is available immediately. When the
EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it
is neither possible to read the EEPROM, nor to change the EEAR register.
The calibrated oscillator is used to time the EEPROM accesses. See the following table for typical
programming times for EEPROM access from the CPU.
Table 10-2. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles Typ. Programming Time
EEPROM write (from CPU) 26,368 3.3ms
The following code examples show one assembly and one C function for writing to the EEPROM. The
examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts
will occur during execution of these functions. The examples also assume that no Flash Boot Loader is
present in the software. If such code is present, the EEPROM write function must also wait for any
ongoing SPM command to finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
(1)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 41
Page 42
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
ATmega328PB
AVR Memories
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
(1)
Note: (1) Refer to About Code Examples
The following code examples show assembly and C functions for reading the EEPROM. The examples
assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
(1)
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
(1)
1. Refer to About Code Examples.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 42
Page 43
ATmega328PB
AVR Memories
10.6.5 GPIOR2 – General Purpose I/O Register 2
Name: GPIOR2
Offset: 0x4B [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x2B
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
GPIOR2[7:0]
Bits 7:0 – GPIOR2[7:0] General Purpose I/O
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 43
Page 44
ATmega328PB
AVR Memories
10.6.6 GPIOR1 – General Purpose I/O Register 1
Name: GPIOR1
Offset: 0x4A [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x2A
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
GPIOR1[7:0]
Bits 7:0 – GPIOR1[7:0] General Purpose I/O
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 44
Page 45
ATmega328PB
AVR Memories
10.6.7 GPIOR0 – General Purpose I/O Register 0
Name: GPIOR0
Offset: 0x3E [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1E
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
GPIOR0[7:0]
Bits 7:0 – GPIOR0[7:0] General Purpose I/O
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 45
Page 46
11. System Clock and Clock Options
Asynchronous
Timer/Counter
ADC AVR CPU
Flash and
EEPROM
Watchdog
Timer
System Clock
Prescaler
Clock
Multiplexer
Timer/Counter
Oscillator
Watchdog
Oscillator
Calibrated Internal
RC OSC
External Clock
Crystal
Oscillator
XTAL1
XTAL2
clk
ASY
clk
CPU
Low-frequency
Crystal Oscillator
Reset Logic
AVR Clock
Control Unit
General I/O
Modules
RAM
clk
IO
clk
FLASH
clk
ADC
Watchdog clock
TOSC1
TOSC2
clk
SYS
Peripheral Touch
Controller
clk
PTC
11.1 Clock Systems and Their Distribution
The following figure illustrates the principal clock systems in the device and their distribution. All the
clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes. The clock systems are described in the
following sections.
The system clock frequency refers to the frequency generated from the system clock prescaler. All clock
outputs from the AVR clock control unit runs in the same frequency.
Figure 11-1. Clock Distribution
ATmega328PB
System Clock and Clock Options
11.1.1 CPU Clock – clk
Related Links
Power Management and Sleep Modes
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of
such modules are the general purpose register file, the Status register, and the data memory holding the
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 46
Page 47
ATmega328PB
System Clock and Clock Options
stack pointer. Halting the CPU clock inhibits the core from performing general operations and
calculations.
11.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O
clock is also used by the External Interrupt module, but the start condition detection in the USI module is
carried out asynchronously when clk
Note: If a level triggered interrupt is used for wake-up from power-down, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears
before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
start-up time is defined by the SUT and CKSEL fuses.
11.1.3 PTC Clock - clk
PTC
The PTC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order
to reduce noise and power due to digital circuitry.
11.1.4 Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously
with the CPU clock.
11.1.5 Asynchronous Timer Clock – clk
The asynchronous timer clock allows asynchronous Timer/Counters to be clocked directly from an
external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/
Counter as a real-time counter even when the device is in sleep mode.
is halted, TWI address recognition in all sleep modes.
I/O
ASY
11.1.6 ADC Clock – clk
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order
to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
11.2 Clock Sources
The device has the following clock source options, selectable by Flash fuse bits as shown below. The
clock from the selected source is input to the AVR clock generator and routed to the appropriate modules.
Table 11-1. Device Clocking Options Select
Device Clocking Option CKSEL[3:0]
Low-Power Crystal Oscillator 1111 - 1000
Low Frequency Crystal Oscillator 0101 - 0100
Internal 128 kHz RC Oscillator 0011
Calibrated Internal RC Oscillator 0010
External Clock 0000
Reserved 0001
Note: For all fuses, '1' means unprogrammed while '0' means programmed.
ADC
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 47
Page 48
11.2.1 Default Clock Source
The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8 programmed,
resulting in 1.0 MHz system clock. The start-up time is set to maximum, and the time-out period is
enabled: CKSEL=0010, SUT=10, CKDIV8=0. This default setting ensures that all users can make their
desired clock source setting using any available programming interface.
11.2.2 Clock Start-Up Sequence
Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles
before it can be considered stable.
ATmega328PB
System Clock and Clock Options
To ensure sufficient VCC, the device issues an internal Reset with a time-out delay (t
Reset is released by all other Reset sources. See the Related Links for a description of the start
conditions for the internal Reset. The delay (t
of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in the
table below. The frequency of the Watchdog oscillator is voltage dependent.
Table 11-2. Number of Watchdog Oscillator Cycles
Typ. Time-out (VCC = 5.0V) Typ. Time-out (VCC = 3.0V)
0ms 0ms
4 ms 4.3 ms
65 ms 69 ms
Main purpose of the delay is to keep the device in Reset until it is supplied with minimum VCC. The delay
will not monitor the actual voltage, so it is required to select a delay longer than the VCC rise time. If this is
not possible, an internal or external Brown-out Detection (BOD) circuit should be used. A BOD circuit will
ensure sufficient VCC before it releases the reset, and the time out delay can be disabled. Disabling the
time-out delay without utilizing a BOD circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is considered
stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal Reset active
for a given number of clock cycles. The Reset is then released and the device will start to execute. The
recommended oscillator start-up time is dependent on the clock type, and varies from six cycles for an
externally applied clock to 32K cycles for a low frequency crystal.
) is timed from the Watchdog oscillator and the number
TOUT
) after the device
TOUT
The start-up sequence for the clock includes both the time-out delay and the start-up time when the
device starts up from Reset. When starting up from Power-save or Power-down mode, VCC is assumed to
be at a sufficient level and only the start-up time is included.
Related Links
System Control and Reset
11.2.3 Clock Source Connections
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured
for use as an on-chip oscillator, as shown in the figure below. Either a quartz crystal or a ceramic
resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors
depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic
noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in
the next table. For ceramic resonators, the capacitor values given by the manufacturer should be used.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 48
Page 49
Figure 11-2. Crystal Oscillator Connections
XTAL2
XTAL1
GND
C2
C1
11.3 Low-Power Crystal Oscillator
This Crystal Oscillator is a low-power oscillator, with reduced voltage swing on the XTAL2 output. It gives
the lowest power consumption, but is not capable of driving other clock inputs, and may be more
susceptible to noise in noisy environments.
The crystal should be connected as described in Clock Source Connections. When selecting crystals,
load capacitance must be taken into consideration. The capacitance (Ce+Ci) needed at each TOSC pin
can be calculated by using:
ATmega328PB
System Clock and Clock Options
+ = 2
where:
• Ce - is optional external capacitors. (= C1, C2 as shown in the schematics.)
• Ci - is the pin capacitance in the following table.
• CL - is the load capacitance specified by the crystal vendor.
• CS - is the total stray capacitance for one XTAL pin.
Table 11-3. Internal Capacitance of Low-Power Oscillator
32 kHz Osc. Type Internal Pad Capacitance
(XTAL1)
Internal Pad Capacitance
(XTAL2)
Ci of system oscillator (XTAL pins) 18 pF 8 pF
The Low-power Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL[3:1], as shown in the following table:
Table 11-4. Low-Power Crystal Oscillator Operating Modes
Frequency Range
CKSEL[3:1]
(2)
Absolute Limits for Total Capacitance of C1 and C2 [pF]
(1)
(4)
[MHz]
0.4 - 0.9 100
(3)
–
0.9 - 3.0 101 12 - 22
3.0 - 8.0 110 12 - 22
8.0 - 16.0 111 12 - 22
Note:
1. These are the recommended CKSEL settings for the different frequency ranges.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 49
Page 50
ATmega328PB
System Clock and Clock Options
2. This option should not be used with crystals, only with ceramic resonators.
3. If the crystal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse
can be programmed in order to divide the internal frequency by 8. It must be ensured that the
resulting divided clock meets the frequency specification of the device.
4. When selecting the external capacitor value, the stray capacitance from the PCB and device should
be deducted. The total load (Ce+Ci+Cs) on XTAL pins must not exceed 22 pF.
The CKSEL0 Fuse together with the SUT[1:0] Fuses select the start-up times, as shown in the following
table:
Table 11-5. Start-Up Times for the Low-Power Crystal Oscillator Clock Selection
Oscillator Source/Power
Conditions
Ceramic resonator, fast rising
Start-Up Time
from Power-Down
and Power-Save
Additional Delay from
Reset
(VCC = 5.0V)
258 CK 19CK + 4 ms
(1)
CKSEL0 SUT[1:0]
0 00
power
Ceramic resonator, slowly rising
258 CK 19CK + 65 ms
(1)
0 01
power
Ceramic resonator, BOD
1K CK 19CK
(2)
0 10
enabled
Ceramic resonator, fast rising
1K CK 19CK + 4 ms
(2)
0 11
power
Ceramic resonator, slowly rising
1K CK 19CK + 65 ms
(2)
1 00
power
Crystal Oscillator, BOD enabled 16K CK 19CK 1 01
Crystal Oscillator, fast rising
16K CK 19CK + 4 ms 1 10
power
Crystal Oscillator, slowly rising
16K CK 19CK + 65 ms 1 11
power
Note:
1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These options
are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at
start-up. They can also be used with crystals when not operating close to the maximum frequency
of the device and if frequency stability at start-up is not important for the application.
11.4 Low Frequency Crystal Oscillator
The Low Frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When
selecting crystals, load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into
consideration. Both values are specified by the crystal vendor. The oscillator is optimized for very low
power consumption, and thus when selecting crystals, consider the Maximum ESR Recommendations:
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 50
Page 51
System Clock and Clock Options
Table 11-6. Maximum ESR Recommendation for 32.768 kHz Crystal
ATmega328PB
Crystal CL [pF] Max. ESR [kΩ]
6.5 75
9.0 65
12.5 30
Note:
1. Maximum ESR is typical value based on characterization.
The Low Frequency Crystal Oscillator provides an internal load capacitance at each TOSC pin:
Table 11-7. Capacitance for Low Frequency Oscillator
32 kHz Osc. Type Internal Pad Capacitance
(XTAL1/TOSC1)
Ci of system oscillator (XTAL pins) 18 pF 8 pF
Ci of timer oscillator (TOSC pins) 18 pF 8 pF
The capacitance (Ce+Ci) needed at each TOSC pin can be calculated by using:
+ = 2
where:
• Ce - is optional external capacitors. (= C1, C2 as shown in Clock Source Connections.)
• Ci - is the pin capacitance in Table 11-3.
• CL - is the load capacitance specified by the crystal vendor.
• CS - is the total stray capacitance for one XTAL pin.
(1)
Internal Pad Capacitance
(XTAL2/TOSC2)
Crystals specifying a load capacitance (CL) higher than 6 pF require external capacitors applied as
described in Clock Source Connections.
The Low Frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to '0110' or
'0111',and Start-Up times are determined by the SUT Fuses, as shown in the following two tables.
Table 11-8. Start-Up Times for the Low Frequency Crystal Oscillator Clock Selection - SUT Fuses
SUT[1:0] Additional Delay from Reset (VCC = 5.0V) Recommended Usage
00 19CK Fast rising power or BOD enabled
01 19CK + 4.1 ms Slowly rising power
10 19CK + 65 ms Stable frequency at start-up
11 Reserved
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 51
Page 52
ATmega328PB
System Clock and Clock Options
Table 11-9. Start-Up Times for the Low Frequency Crystal Oscillator Clock Selection - CKSEL
Fuses
CKSEL[3:0] Start-Up Time from
Power-Down and Power-Save
(1)
0100
1K CK
0101 32K CK Stable frequency at start-up
Note:
1. This option should only be used if frequency stability at start-up is not important for the application.
11.5 Calibrated Internal RC Oscillator
By default, the internal RC oscillator provides an 8.0 MHz clock. Though voltage and temperature
dependent, this clock can be very accurately calibrated by the user. The device is shipped with the
CKDIV8 Fuse programmed.
This clock may be selected as the system clock by programming the CKSEL fuses as shown in the
following table. If selected, it will operate with no external components. During reset, hardware loads the
pre-programmed calibration value into the OSCCAL register and thereby automatically calibrates the RC
oscillator.
By changing the OSCCAL register from SW, it is possible to get a higher calibration accuracy than by
using the factory calibration.
When this oscillator is used as the chip clock, the Watchdog oscillator will still be used for the Watchdog
Timer and for the reset time-out. For more information on the pre-programmed calibration value, see
section Calibration Byte.
Recommended Usage
Table 11-10. Internal Calibrated RC Oscillator Operating Modes
Frequency Range
7.6 - 8.4 0010
(1)
[MHz] CKSEL[3:0]
(2)
Note:
1. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse
can be programmed in order to divide the internal frequency by 8.
2. The device is shipped with this option selected.
Warning: The oscillator frequency is not guaranteed to be monotonic within the given range as the
oscillator calibration contains discontinuity (see figure 8 MHz RC Oscillator Frequency vs. OSCCAL Value
in chapter Typical Characteristics.)
When this oscillator is selected, start-up times are determined by the SUT fuses:
Table 11-11. Start-Up Times for the Internal Calibrated RC Oscillator Clock Selection - SUT
Power Conditions Start-Up Time from Power-Down
Additional Delay from Reset (VCC = 5.0V) SUT[1:0]
and Power-Save
BOD enabled 6 CK 19CK
(1)
Fast rising power 6 CK 19CK + 4 ms 01
00
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 52
Page 53
ATmega328PB
System Clock and Clock Options
Power Conditions Start-Up Time from Power-Down
and Power-Save
Slow rising power 6 CK 19CK + 65 ms
Reserved 11
Note:
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
19CK + 4 ms to ensure programming mode can be entered.
2. The device is shipped with this option selected.
Related Links
System Clock Prescaler
Clock Characteristics
Calibration Byte
Internal Oscillator Speed
OSCCAL
Additional Delay from Reset (VCC = 5.0V) SUT[1:0]
(2)
11.6 128 kHz Internal Oscillator
The 128 kHz internal oscillator is a low-power oscillator providing a clock of 128 kHz. This clock may be
select as the system clock by programming the CKSEL fuses to '0011' as shown in the following table.
10
Warning: Using the 128 kHz internal oscillator as the system oscillator and Watchdog Timer
simultaneously is not recommended as this defeats one of the purposes of the Watchdog Timer.
Table 11-12. 128 kHz Internal Oscillator Operating Modes
Nominal Frequency
128 kHz 0011
Note:
1. The 128 kHz oscillator is a very low-power clock source, and is not designed for high accuracy.
When this clock source is selected, start-up times are determined by the SUT fuses:
Table 11-13. Start-Up Times for the 128 kHz Internal Oscillator
Power Conditions Start-Up Time from Power-Down
BOD enabled 6CK 19CK
Fast rising power 6CK 19CK + 4 ms 01
Slowly rising power 6CK 19CK + 65 ms 10
Reserved 11
Note:
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
19CK + 4 ms to ensure programming mode can be entered.
(1)
and Power-Save
CKSEL[3:0]
Additional Delay from Reset SUT[1:0]
(1)
00
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 53
Page 54
11.7 External Clock
EXTERNAL
CLOCK
SIGNAL
EXTCLK
GND
To drive the device from an external clock source, EXTCLK should be driven as shown in the figure
below. To run the device on an external clock, the CKSEL Fuses must be programmed to '0000':
Table 11-14. External Clock Frequency
Frequency CKSEL[3:0]
0 - 20 MHz 0000
Figure 11-3. External Clock Drive Configuration
ATmega328PB
System Clock and Clock Options
Table 11-15. Start-Up Times for the External Clock Selection - SUT
11.8 Clock Output Buffer
When this clock source is selected, start-up times are determined by the SUT Fuses:
Power Conditions Start-Up Time from Power-Down
and Power-Save
BOD enabled 6CK 19CK 00
Fast rising power 6CK 19CK + 4.1 ms 01
Slowly rising power 6CK 19CK + 65 ms 10
Reserved 11
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to
ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the
next can lead to unpredictable behavior. If changes of more than 2% are required, ensure that the MCU is
kept in Reset during the changes.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency
while still ensuring stable operation.
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to
be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
The clock also will be output during Reset, and the normal operation of I/O pin will be overridden when
the fuse is programmed. Any clock source, including the internal RC oscillator, can be selected when the
clock is output on CLKO. If the system clock prescaler is used, it is the divided system clock that is
output.
Additional Delay from Reset
(VCC = 5.0V)
SUT[1:0]
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 54
Page 55
11.9 Timer/Counter Oscillator
The device uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator.
See Low Frequency Crystal Oscillator for details on the oscillator and crystal requirements.
On this device, the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with EXTCLK. When
using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due
to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal
RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if the Enable External Clock Input bit in the
Asynchronous Status Register (ASSR.EXCLK) is written to '1'. See the description of the Asynchronous
Operation of Timer/Counter2 for further description on selecting external clock as input instead of a
32.768 kHz watch crystal.
Related Links
8-bit Timer/Counter2 with PWM and Asynchronous Operation
11.10 System Clock Prescaler
The device has a system clock prescaler and the system clock can be divided by configuring the Clock
Prescale Register (CLKPR). This feature can be used to decrease the system clock frequency and the
power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
, clk
ADC
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in
the clock system. It also ensures that no intermediate frequency is higher than neither the clock
frequency corresponding to the previous setting nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may
be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler
- even if it were readable, the exact time it takes to switch from one clock division to the other cannot be
exactly predicted. From the time the Clock Prescaler Selection bits (CLKPS[3:0]) values are written, it
takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two
active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period
corresponding to the new prescaler setting.
CPU
, and clk
are divided by a factor as shown in the CLKPR description.
FLASH
ATmega328PB
System Clock and Clock Options
,
I/O
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change
the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to '1' and all other bits in CLKPR to zero:
CLKPR=0x80.
2. Within four cycles, write the desired value to CLKPS[3:0] while writing a zero to CLKPCE:
CLKPR=0x0N.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not
interrupted.
11.11 Register Description
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 55
Page 56
ATmega328PB
System Clock and Clock Options
11.11.1 Oscillator Calibration Register
Name: OSCCAL
Offset: 0x66
Reset: Device Specific Calibration Value
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7:0 – CAL [7:0] Oscillator Calibration Value
The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process
variations away from the oscillator frequency. A preprogrammed calibration value is automatically written
to this register during chip reset, giving the factory calibrated frequency as specified in the Clock
Characteristics section of chapter Electrical Characteristics.The application software can write this
register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
the Clock Characteristics section of chapter Electrical Characteristics. Calibration outside that range is not
recommended.
CAL [7:0]
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be
affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz.
Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest
frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are
overlapping, in other words, a setting of OSCCAL=0x7F gives a higher frequency than OSCCAL=0x80.
The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the
lowest frequency in that range and a setting of 0x7F gives the highest frequency in the range.
Related Links
Calibrated Internal RC Oscillator Accuracy
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 56
Page 57
ATmega328PB
System Clock and Clock Options
11.11.2 Clock Prescaler Register
Name: CLKPR
Offset: 0x61
Reset: Refer to the bit description
Property: -
Bit 7 6 5 4 3 2 1 0
CLKPCE CLKPS [3:0]
Access
Reset 0 x x x x
R/W R/W R/W R/W R/W
Bit 7 – CLKPCE Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is
only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by
hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within
this time-out period does neither extend the time-out period nor clear the CLKPCE bit.
Bits 3:0 – CLKPS [3:0] Clock Prescaler Select
These bits define the division factor between the selected clock source and the internal system clock.
These bits can be written run-time to vary the clock frequency to suit the application requirements. As the
divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced
when a division factor is used. The division factors are given in the table below.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the
CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a
division factor of 8 at start-up. This feature should be used if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating conditions. Note that any
value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software
must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency
than the maximum frequency of the device at the present operating conditions. The device is shipped
with the CKDIV8 Fuse programmed.
Table 11-16. Clock Prescaler Select
CLKPS[3:0] Clock Division Factor
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1000 256
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 57
Page 58
ATmega328PB
System Clock and Clock Options
CLKPS[3:0] Clock Division Factor
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 58
Page 59
CFD - Clock Failure Detection mechanism
12. CFD - Clock Failure Detection mechanism
12.1 Overview
The Clock Failure Detection mechanism for the device is enabled by CFD fuse in the Extended Fuse
Byte. CFD operates with a 128 kHz internal oscillator which will be enabled automatically when CFD is
enabled.
12.2 Features
• Detection of the failure of the low power crystal oscillator and external clocks
• Operate with 128 kHz internal oscillator
• Switch the system clock to 1 MHz internal RC oscillator clock when clock failure happens
• Failure Detection Interrupt Flag (XFDIF) available for the status of CFD
12.3 Operations
The Clock Failure Detector (CFD) allows the user to monitor the low power crystal oscillator or external
clock signal. CFD monitors XOSC clock and if it fails it will automatically switch to a safe clock. When
operating on the safe clock the device will switch back to XOSC clock after Power-On or External Reset,
and continue monitoring XOSC clock for failures. The safe 1 MHz system clock is derived from the 8 MHz
internal RC system clock. After switching to safe 1 MHz clock the user can write the System Clock
Prescale Register (CLKPR) to increase the frequency. This allows configuring the safe clock in order to
fulfill the operative conditions of the microcontroller.
ATmega328PB
Because the XOSC failure is monitored by the CFD circuit operating with the internal 128 kHz oscillator,
the current consumption of the 128 kHz oscillator will be added into the total power consumption of the
chip when CFD is enabled. CFD should be enabled only if the system clock (XOSC) frequency is above
256 kHz.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 59
Page 60
Clock Failure Detection
circuit
Low Power Crystal Oscillator
128kHz Internal Oscillator
Calibrated Internal RC Oscillator
External Clock
System
clock
XOSC CKSEL
Calibrated RC Oscillator
(CKSEL: 4'b 0010
CLKPS: 4'b 0011)
XOSC Failed
CKSEL
WDT 128kHz CLK
XOSC
(External CLK/
CFD - Clock Failure Detection mechanism
Figure 12-1. System Clock Generation with CFD Mechanism
ATmega328PB
Clock Failure Detection
To start the CFD operation, the user must write a one to the CFD fuse bit in the Extended Fuse Byte
(EFB.CFD). After the start or restart of the XOSC, the CFD does not detect failure until the start-up time is
elapsed. Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored.
If the external clock is not provided, the device will automatically switch to calibrated RC oscillator output.
When the failure is detected, the failure status is asserted, i.e Failure Detection Interrupt Flag bit in the
XOSC Failure Detection Control And Status Register (XFDCSR.XFDIF) is set. The Failure Detection
interrupt flag is generated, when the Interrupt Enable bit in the XOSC Failure Detection Control And
Status Register (XFDCSR.XFDIE) is set. The XFDCSR.XFDIF reflects the current XOSC clock activity.
The detection will be automatically disabled when chip goes to power save/down sleep mode and
enabled by itself when chip enters back to active mode.
Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an
active clock. The safe clock source is the calibrated RC oscillator clock (CKSEL: 4’b0010). The clock
source can be downscaled with a configurable prescaler to ensure that the clock frequency does not
exceed the operating conditions selected by the application after switching. To use the original clock
source, the user must provide a reset. When using CFD and clock failure has occurred the system
operates using 1 MHz internal fallback clock. The system will try to resume to original clock source either
via Power-On-Reset (POR) or via external RESET.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 60
Page 61
12.4 Timing Diagram
RC clock
Ext clock
Sys clock
Xosc failed
Delayed xosc failed
The RC clock is enabled only after failure detection.
Figure 12-2. CFD Mechanism Timing Diagram
ATmega328PB
CFD - Clock Failure Detection mechanism
12.5 Register Description
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 61
Page 62
ATmega328PB
CFD - Clock Failure Detection mechanism
12.5.1 XOSC Failure Detection Control And Status Register
Name: XFDCSR
Offset: 0x62
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0
XFDIF XFDIE
R R/W
Bit 1 – XFDIF Failure Detection Interrupt Flag
This bit is set when a failure is detected, and it can be cleared only by reset.
It serves as a status bit for CFD.
Note: This bit is read-only.
Bit 0 – XFDIE Failure Detection Interrupt Enable
Setting this bit will enable the interrupt which will be issued when XFDIF is set. This bit is enable only.
Once enabled, it is not possible for the user to disable.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 62
Page 63
ATmega328PB
Power Management and Sleep Modes
13. Power Management and Sleep Modes
13.1 Overview
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power.
The device provides various sleep modes allowing the user to tailor the power consumption to the
application requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the
sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See also
BOD Disable.
13.2 Sleep Modes
The following table shows the different sleep modes, BOD disable ability, and their wake-up sources.
Table 13-1. Active Clock Domains and Wake-Up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Wake-Up Sources
Sleep Mode
CPU
clk
FLASH
clk
IO
clk
ADC
clk
clk
ASY
PTC
clk
Enabled
Main Clock
Source Enabled
Timer Oscillator
Idle Yes Yes Yes Yes Yes Yes
ADC Noise
Yes Yes Yes Yes Yes
(2)
Yes Yes Yes Yes Yes Yes Yes Yes
(2)
Yes
Reduction
Power-Down Yes
Power-Save Yes Yes Yes
Standby
Extended Standby Yes
(1)
Yes Yes
(2)
Yes Yes Yes
(5)
Yes
(2)
(2)
Yes
Yes
Note:
1. Only recommended with external crystal or resonator selected as the clock source.
2. If Timer/Counter2 is running in Asynchronous mode.
3. For INT1 and INT0, only level interrupt.
4. Start frame detection only.
5. The main clock is kept running if PTC is enabled.
(4)
ADC
WDT
Timer2
Match
INT and PCINT
TWI Address
(3)
Yes Yes
(3)
Yes Yes Yes Yes
(3)
Yes Yes Yes Yes Yes
(3)
Yes Yes Yes Yes
(3)
Yes Yes Yes Yes Yes
(2)
Ready
SPM/EEPROM
Yes Yes Yes Yes
Other I/O
USART
Software
BOD Disable
To enter any of the six sleep modes, the sleep enable bit in the Sleep Mode Control Register (SMCR.SE)
must be written to '1' and a SLEEP instruction must be executed. Sleep Mode Select bits
(SMCR.SM[2:0]) select which sleep mode (Idle, ADC Noise Reduction, Power-Down, Power-Save,
Standby, or Extended Standby) will be activated by the SLEEP instruction.
Note: The block diagram in the section System Clock and Clock Options provides an overview over the
different clock systems in the device and their distribution. This figure is helpful in selecting an appropriate
Sleep mode.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 63
Page 64
If an enabled interrupt occurs while the MCU is in a Sleep mode, the MCU wakes up. The MCU is then
halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes
execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered
when the device wakes up from sleep. If a reset occurs during Sleep mode, the MCU wakes up and
executes from the Reset vector.
Related Links
System Clock and Clock Options
13.3 BOD Disable
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the
power supply voltage during a sleep period. To save power, it is possible to disable the BOD by use of
software for some of the sleep modes. The sleep mode power consumption will then be at the same level
as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off
immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled
again. This ensures safe operation in case the VCC level has dropped during the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 μs to
ensure that the BOD is working correctly before the MCU continues executing code.
ATmega328PB
Power Management and Sleep Modes
BOD disable is controlled by the BOD Sleep bit in the MCU Control Register (MCUCR.BODS). Writing
this bit to '1' turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD active. The
default setting, BODS=0, keeps BOD active.
Note: Writing to the BODS bit is controlled by a timed sequence and an enable bit.
Related Links
MCUCR
13.4 Idle Mode
When the SM[2:0] bits are written to '000', the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, USART, analog comparator, two-wire serial interface, ADC, Timer/
Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts
clk
CPU
and clk
, while allowing the other clocks to run.
FLASH
The Idle mode enables the MCU to wake-up from external triggered interrupts as well as internal ones
like the timer overflow and USART transmit complete interrupts. If wake-up from the analog comparator
interrupt is not required, the analog comparator can be powered-down by setting the ACD bit in the
Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle
mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
13.5 ADC Noise Reduction Mode
When the SM[2:0] bits are written to '001', the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the two-wire serial
interface address watch, Timer/Counter
sleep mode basically halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC
is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC conversion
complete interrupt, only these events can wake-up the MCU from ADC Noise Reduction mode:
I/O
, clk
(1)
, and the Watchdog to continue operating (if enabled). This
CPU
, and clk
, while allowing the other clocks to run.
FLASH
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 64
Page 65
• External Reset
• Watchdog System Reset
• Watchdog Interrupt
• Brown-out Reset
• Two-wire Serial Interface Address Match
• Timer/Counter Interrupt
• SPM/EEPROM Ready Interrupt
• External Level Interrupt on INT
• Pin Change Interrupt
Note: 1. Timer/Counter will only keep running in Asynchronous mode.
Related Links
8-bit Timer/Counter2 with PWM and Asynchronous Operation
13.6 Power-Down Mode
When the SM[2:0] bits are written to '010', the SLEEP instruction makes the MCU enter the Power-Down
mode. In this mode, the external oscillator is stopped, while the external interrupts, the two-wire serial
interface address watch, and the Watchdog continue operating (if enabled).
ATmega328PB
Power Management and Sleep Modes
Only one of these events can wake up the MCU:
• External Reset
• Watchdog System Reset
• Watchdog Interrupt
• Brown-out Reset
• Two-wire Serial Interface Address Match
• External level Interrupt on INT
• Pin Change Interrupt
This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note: If a level triggered interrupt is used for wake-up from power-down, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears
before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
start-up time is defined by the SUT and CKSEL Fuses.
When waking up from the Power-Down mode, there is a delay from the wake-up condition occurs until
the wake-up becomes effective. This allows the clock to restart and become stable after having been
stopped. The wake-up period is defined by the same CKSEL fuses that define the Reset time-out period.
Related Links
System Clock and Clock Options
13.7 Power-Save Mode
When the SM[2:0] bits are written to 011, the SLEEP instruction makes the MCU enter Power-Save
mode. This mode is identical to power-down, except:
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 65
Page 66
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake-up from either timer
overflow or output compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt
enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set.
If the PTC is enabled, the main clock is kept running.
If Timer/Counter2 is not running, the Power-Down mode is recommended instead of the Power-Save
mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-Save mode. If
Timer/Counter2 is not using the asynchronous clock, the Timer/Counter oscillator is stopped during sleep.
If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Even if
the synchronous clock is running in power-save, this clock is only available for Timer/Counter2.
13.8 Standby Mode
When the SM[2:0] bits are written to '110' and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to the Power-Down mode
with the exception that the oscillator is kept running. From Standby mode, the device wakes up in six
clock cycles.
ATmega328PB
Power Management and Sleep Modes
13.9 Extended Standby Mode
When the SM[2:0] bits are written to '111' and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-Save
mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device
wakes up in six clock cycles.
13.10 Power Reduction Registers
The Power Reduction Registers (PRR1 and PRR0) provides a method to stop the clock to individual
peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O
registers cannot be read or written. Resources used by the peripheral when stopping the clock will remain
occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a
module, which is done by clearing the corresponding bit in the PRR, puts the module in the same state as
before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power
consumption. In all other sleep modes, the clock is already stopped.
13.11 Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep mode
should be selected so that as few as possible of the device’s functions are operating. All functions not
needed should be disabled. In particular, the following modules may need special consideration when
trying to achieve the lowest possible power consumption.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 66
Page 67
13.11.1 Analog-to-Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled
before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an
extended conversion.
Related Links
Analog-to-Digital Converter
13.11.2 Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. When entering ADC
Noise Reduction mode, the analog comparator should be disabled. In other sleep modes, the analog
comparator is automatically disabled. However, if the analog comparator is set up to use the internal
voltage reference as input, the analog comparator should be disabled in all sleep modes. Otherwise, the
internal voltage reference will be enabled, independent of the sleep mode.
Related Links
Analog Comparator
13.11.3 Brown-Out Detector
If the Brown-Out Detector (BOD) is not needed by the application, this module should be turned off. If the
BOD is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always
consume power. In the deeper sleep modes, this will contribute significantly to the total current
consumption.
ATmega328PB
Power Management and Sleep Modes
Related Links
System Control and Reset
13.11.4 Internal Voltage Reference
The internal voltage reference will be enabled when needed by the Brown-out Detection, the analog
comparator or the Analog-to-Digital Converter (ADC). If these modules are disabled as described in the
sections above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start-up before the output is used. If the reference is
kept on in Sleep mode, the output can be used immediately.
Related Links
System Control and Reset
13.11.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog
Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
Related Links
System Control and Reset
13.11.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most
important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock
(clk
) and the ADC clock (clk
I/O
ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is
needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Digital Input
Enable and Sleep Modes for details on which pins are enabled. If the input buffer is enabled and the input
) are stopped, the input buffers of the device will be disabled. This
ADC
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 67
Page 68
signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close
to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be
disabled by writing to the Digital Input Disable Registers (DIDR0 for ADC, DIDR1 for AC).
Related Links
Digital Input Enable and Sleep Modes
13.11.7 On-chip Debug System
If the on-chip debug system is enabled by the DWEN fuse and the chip enters Sleep mode, the main
clock source is enabled and hence always consumes power. In the deeper Sleep modes, this will
contribute significantly to the total current consumption.
13.12 Register Description
ATmega328PB
Power Management and Sleep Modes
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 68
Page 69
ATmega328PB
Power Management and Sleep Modes
13.12.1 Sleep Mode Control Register
Name: SMCR
Offset: 0x53
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x33
The Sleep Mode Control Register contains control bits for power management.
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
SM[2:0] SE
R/W R/W R/W R/W
Bits 3:1 – SM[2:0] Sleep Mode Select
The SM[2:0] bits select between the five available sleep modes.
Table 13-2. Sleep Mode Select
SM[2:0] Sleep Mode
000 Idle
001 ADC Noise Reduction
010 Power-down
011 Power-save
100 Reserved
101 Reserved
110 Standby
111 Extended Standby
(1)
(1)
Note:
1. Standby mode is only recommended for use with external crystals or resonators.
Bit 0 – SE Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,
it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP
instruction and to clear it immediately after waking up.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 69
Page 70
ATmega328PB
Power Management and Sleep Modes
13.12.2 MCU Control Register
Name: MCUCR
Offset: 0x55
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x35
The MCU control register controls the placement of the interrupt vector table in order to move interrupts
between application and boot space.
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0
BODS BODSE PUD IVSEL IVCE
R/W R/W R/W R/W R/W
Bit 6 – BODS BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is
controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both
BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be
written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS
is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared
after three clock cycles.
Bit 5 – BODSE BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is
controlled by a timed sequence.
Bit 4 – PUD Pull-up Disable
When this bit is written to one, the pull ups in the I/O ports are disabled even if the DDxn and PORTxn
registers are configured to enable the pull ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory.
When this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of
the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses.
To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to
change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 70
Page 71
ATmega328PB
Power Management and Sleep Modes
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
same cycle as IVCE is written, and interrupts remain disabled until after the instruction following the write
to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status register
is unaffected by the automatic disabling.
Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the application section. If interrupt vectors are placed in the
application section and Boot Lock bit BLB12 is programmed, interrupts are disabled while executing from
the Boot Loader section.
Bit 0 – IVCE Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware
four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as
explained in the IVSEL description above. See the code example below.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR
mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ori r17, (1<<IVSEL)
out MCUCR, r17
ret
C Code Example
void Move_interrupts(void)
{
uchar temp;
/* GET MCUCR*/
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp|(1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = temp|(1<<IVSEL);
}
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 71
Page 72
ATmega328PB
Power Management and Sleep Modes
13.12.3 Power Reduction Register 0
Name: PRR0
Offset: 0x64
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PRTWI0 PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI0 PRUSART0 PRADC
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – PRTWI0 Power Reduction TWI0
Writing a logic one to this bit shuts down the TWI 0 by stopping the clock to the module. When waking up
the TWI again, the TWI should be reinitialized to ensure proper operation.
Bit 6 – PRTIM2 Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0).
When the Timer/Counter2 is enabled, the operation will continue like before the shutdown.
Bit 5 – PRTIM0 Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is
enabled, the operation will continue like before the shutdown.
Bit 4 – PRUSART1 Power Reduction USART1
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking
up the USART again, the USART should be reinitialized to ensure proper operation.
Bit 3 – PRTIM1 Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is
enabled, the operation will continue like before the shutdown.
Bit 2 – PRSPI0 Power Reduction Serial Peripheral Interface 0
If using debugWIRE on-chip debug system, this bit should not be written to one. Writing a logic one to this
bit shuts down the Serial Peripheral Interface (SPI) by stopping the clock to the module. When waking up
the SPI again, the SPI should be reinitialized to ensure proper operation.
Bit 1 – PRUSART0 Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking
up the USART again, the USART should be reinitialized to ensure proper operation.
Bit 0 – PRADC Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The
analog comparator cannot use the ADC input MUX when the ADC is shut down.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 72
Page 73
ATmega328PB
Power Management and Sleep Modes
13.12.4 Power Reduction Register 1
Name: PRR1
Offset: 0x65
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0
PRTWI1 PRPTC PRTIM4 PRSPI1 PRTIM3
R/W R/W R/W R/W R/W
Bit 5 – PRTWI1 Power Reduction TWI1
Writing a logic one to this bit shuts down the TWI1 by stopping the clock to the module. When waking up
the TWI1 again, the TWI1 should be re initialized to ensure proper operation.
Bit 4 – PRPTC Power Reduction PTC
Writing a logic one to this bit shuts down the PTC module. When the PTC is enabled, operation will
continue like before the shutdown.
Bit 3 – PRTIM4 Power Reduction Timer/Counter4
Writing a logic one to this bit shuts down the Timer/Counter4 module. When the Timer/Counter4 is
enabled, operation will continue like before the shutdown.
Bit 2 – PRSPI1 Power Reduction Serial Peripheral Interface 1
If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to
this bit shuts down the Serial Peripheral Interface1 by stopping the clock to the module. When waking up
the SPI1 again, the SPI1 should be re initialized to ensure proper operation.
Bit 0 – PRTIM3 Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is
enabled, operation will continue like before the shutdown.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 73
Page 74
14. System Control and Reset
14.1 Resetting the AVR
During Reset, all I/O registers are set to their initial values, and the program starts execution from the
Reset vector. The instruction placed at the Reset vector must be a Relative Jump instruction (RJMP) to
the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not
used, and regular program code can be placed at these locations. This is also the case if the Reset
vector is in the application section while the interrupt vectors are in the boot section or vice versa. The
circuit diagram in the next section shows the reset logic.
The I/O ports of the AVR are immediately reset to their initial state when a Reset source goes active. This
does not require any clock source to be running.
After all Reset sources have gone inactive, a delay counter is invoked, stretching the internal Reset. This
allows the power to reach a stable level before the normal operation starts. The time-out period of the
delay counter is defined by the user through the SUT and CKSEL fuses. The different selections for the
delay period are presented in the System Clock and Clock Options chapter.
ATmega328PB
System Control and Reset
Related Links
System Clock and Clock Options
14.2 Reset Sources
The device has the following sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is less than the Power-on Reset
threshold (V
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the
minimum pulse length.
• Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog System Reset mode is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage VCC is less than the Brown-out Reset
threshold (V
).
POT
) and the Brown-out Detector is enabled.
BOT
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 74
Page 75
Figure 14-1. Reset Logic
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
ATmega328PB
System Control and Reset
14.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The POR is activated
whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A POR circuit ensures that the device is reset from power-on. Reaching the POR threshold voltage
invokes the delay counter, which determines how long the device is kept in Reset after VCC rise. The
Reset signal is activated again, without any delay, when VCC decreases below the detection level.
CC
Figure 14-2. MCU Start-up, RESET Tied to V
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 75
Page 76
Figure 14-3. MCU Start-up, RESET Extended Externally
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
CC
14.4 External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum
pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset. When the applied signal reaches the Reset Threshold Voltage (V
edge, the delay counter starts the MCU after the Time-out period (t
can be disabled by the RSTDISBL fuse.
ATmega328PB
System Control and Reset
) on its positive
RST
) has expired. The External Reset
TOUT
Figure 14-4. External Reset During Operation
14.5 Brown-out Detection
The device has an on-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during
operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the
BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike-free BOD. The hysteresis on the
detection level should be interpreted as V
BOD is enabled, and VCC decreases to a value below the trigger level (V
Brown-out Reset is immediately activated. When VCC increases above the trigger level (V
following figure), the delay counter starts the MCU after the Time-out period t
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than
t
.
BOD
BOT+
= V
BOT
+ V
HYST
/2 and V
BOT-
BOT-
= V
- V
BOT
HYST
in the following figure), the
BOT+
has expired.
TOUT
/2. When the
in the
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 76
Page 77
Figure 14-5. Brown-out Reset During Operation
V
CC
RESET
TIME-OUT
INTERNALRESET
V
BOT-
V
BOT+
t
TOUT
CK
CC
14.6 Watchdog System Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling
edge of this pulse, the delay timer starts counting the Time-out period t
Figure 14-6. Watchdog System Reset During Operation
ATmega328PB
System Control and Reset
.
TOUT
14.7 Internal Voltage Reference
14.7.1 Voltage Reference Enable Signals and Start-up Time
The device features an internal bandgap reference. This reference is used for Brown-out Detection, and it
can be used as an input to the analog comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. To save power,
the reference is not always turned ON. The reference is ON during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in
ACSR (ACSR.ACBG)).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting ACSR.ACBG or enabling the ADC, the user must
always allow the reference to start up before the output from the Analog Comparator or ADC is used. To
reduce power consumption in the Power-Down mode, the user can avoid the three conditions above to
ensure that the reference is turned OFF before entering Power-Down mode.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 77
Page 78
14.8 Watchdog Timer
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP[3:0]
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
128 kHz
OSCILLATOR
If the watchdog timer is not needed in the application, the module should be turned OFF. If the watchdog
timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
Refer to Watchdog System Reset for details on how to configure the watchdog timer.
14.8.1 Features
• Clocked from Separate On-chip Oscillator
• Three Operating modes:
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out Period from 16 ms to 8s
• Possible Hardware Fuse Watchdog Always ON (WDTON) for Fail-safe mode
14.8.2 Overview
The device has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate
on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a
given time-out value. In normal operation mode, it is required that the system uses the Watchdog Timer
Reset (WDR) instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
ATmega328PB
System Control and Reset
Figure 14-7. Watchdog Timer
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake
the device from Sleep modes, and as a general system timer. One example is to limit the maximum time
allowed for certain operations, giving an interrupt when the operation has run longer than expected. In
System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent
system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines
the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for
instance allow a safe shutdown by saving critical parameters before a system Reset.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 78
Page 79
ATmega328PB
System Control and Reset
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset
mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are
locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up
must follow timed sequences. The sequence for clearing WDE and changing time out configuration is as
follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and Watchdog
System Reset Enable (WDE) in Watchdog Timer Control Register (WDTCSR.WDCE and
WDTCSR.WDE). A logic one must be written to WDTCSR.WDE regardless of the previous value of
the WDTCSR.WDE.
2. Within the next four clock cycles, write the WDTCSR.WDE and Watchdog prescaler bits group
(WDTCSR.WDP) as desired, but with the WDTCSR.WDCE cleared. This must be done in one
operation.
The following examples show a function for turning off the Watchdog Timer. The
examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so
that no interrupts will occur during the execution of these functions.
Assembly Code Example
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
; Write '1' to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDT
ldi r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or
brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If
the code is not set up to handle the Watchdog, this might lead to an eternal loop of timeout resets. To avoid this situation, the application software should always clear the
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 79
Page 80
ATmega328PB
System Control and Reset
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization
routine, even if the Watchdog is not in use.
The following code examples shows how to change the time-out value of the Watchdog
Timer.
Assembly Code Example
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; -- Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCSR, r16
; -- Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed sequence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Note: The Watchdog Timer should be reset before any change of the WDTCSR.WDP
bits, since a change in the WDTCSR.WDP bits can result in a time out when switching to
a shorter time-out period.
14.9 Register Description
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 80
Page 81
ATmega328PB
System Control and Reset
14.9.1 MCU Status Register
Name: MCUSR
Offset: 0x54 [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x34
To make use of the Reset flags to identify a reset condition, the user should read and then Reset the
MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the
source of the reset can be found by examining the Reset Flags.
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
WDRF BORF EXTRF PORF
R/W R/W R/W R/W
Bit 3 – WDRF Watchdog System Reset Flag
This bit is set if a Watchdog system Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0'
to it.
Bit 2 – BORF Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to it.
Bit 1 – EXTRF External Reset Flag
This bit is set if an external Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to it.
Bit 0 – PORF Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a '0' to it.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 81
Page 82
ATmega328PB
System Control and Reset
14.9.2 WDTCSR – Watchdog Timer Control Register
Name: WDTCSR
Offset: 0x60 [ID-000004d0]
Reset: 0x00
Bit 7 6 5 4 3 2 1 0
WDIF WDIE WDP[3] WDCE WDE WDP[2:0]
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – WDIF Watchdog Interrupt Flag
This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is configured for
interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, WDIF is cleared by writing a '1' to it. When the I-bit in SREG and WDIE are set, the
Watchdog Timeout Interrupt is executed.
Bit 6 – WDIE Watchdog Interrupt Enable
When this bit is written to '1' and the I-bit in the Status register is set, the Watchdog Interrupt is enabled. If
WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt mode, and the
corresponding interrupt is executed if timeout in the Watchdog Timer occurs. If WDE is set, the Watchdog
Timer is in Interrupt and System Reset mode. The first timeout in the Watchdog Timer will set WDIF.
Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the
Watchdog goes to System Reset mode).
This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset mode, WDIE must be set after each interrupt. This should not be done within the interrupt
service routine itself, as this might compromise the safety function of the Watchdog System Reset mode.
If the interrupt is not executed before the next timeout, a System Reset will be applied.
Table 14-1. Watchdog Timer Configuration
WDTON
(1)
WDE WDIE Mode Action on Time-out
1 0 0 Stopped None
1 0 1 Interrupt mode Interrupt
1 1 0 System Reset mode Reset
1 1 1 Interrupt and System Reset mode Interrupt, then go to System Reset mode
0 x x System Reset mode Reset
Note: 1. WDTON Fuse set to '0' means programmed and '1' means unprogrammed.
Bit 5 – WDP[3] Watchdog Timer Prescaler 3
Bit 4 – WDCE Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or
change the prescaler bits, WDCE must be set. Once written to '1', hardware will clear WDCE after four
clock cycles. Refer to Overview in section Watchdog Timer for information on how to use WDCE.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 82
Page 83
ATmega328PB
System Control and Reset
Bit 3 – WDE Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To
clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing
failure, and a safe start-up after the failure.
Bits 2:0 – WDP[2:0] Watchdog Timer Prescaler 2, 1, and 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The
different prescaling values and their corresponding time out periods are shown in the following table.
Table 14-2. Watchdog Timer Prescale Select
WDP[3] WDP[2] WDP[1] WDP[0] Number of WDT Oscillator (Cycles) Oscillator
0 0 0 0 2K (2048) 16 ms
0 0 0 1 4K (4096) 32 ms
0 0 1 0 8K (8192) 64 ms
0 0 1 1 16K (16384) 0.125s
0 1 0 0 32K (32768) 0.25s
0 1 0 1 64K (65536) 0.5s
0 1 1 0 128K (131072) 1.0s
0 1 1 1 256K (262144) 2.0s
1 0 0 0 512K (524288) 4.0s
1 0 0 1 1024K (1048576) 8.0s
1 0 1 0 Reserved
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 83
Page 84
15. INT - Interrupts
This section describes the specifics of the interrupt handling of the device. For a general explanation of
the AVR interrupt handling, refer to the description of Reset and Interrupt Handling.
In general:
• Each Interrupt Vector occupies two instruction words for
• The Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is
affected by the IVSEL bit in MCUCR
Related Links
Reset and Interrupt Handling
15.1 Interrupt Vectors in ATmega328PB
Table 15-1. Reset and Interrupt Vectors in ATmega328PB
ATmega328PB
INT - Interrupts
Vector No
1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 INT1 External Interrupt Request 1
4 0x0006 PCINT0 Pin Change Interrupt Request 0
5 0x0008 PCINT1 Pin Change Interrupt Request 1
6 0x000A PCINT2 Pin Change Interrupt Request 2
7 0x000C WDT Watchdog Time-out Interrupt
8 0x000E TIMER2_COMPA Timer/Counter2 Compare Match A
9 0x0010 TIMER2_COMPB Timer/Coutner2 Compare Match B
10 0x0012 TIMER2_OVF Timer/Counter2 Overflow
11 0x0014 TIMER1_CAPT Timer/Counter1 Capture Event
12 0x0016 TIMER1_COMPA Timer/Counter1 Compare Match A
13 0x0018 TIMER1_COMPB Timer/Coutner1 Compare Match B
14 0x001A TIMER1_OVF Timer/Counter1 Overflow
15 0x001C TIMER0_COMPA Timer/Counter0 Compare Match A
Program Address Source Interrupts definition
Reset
16 0x001E TIMER0_COMPB Timer/Coutner0 Compare Match B
17 0x0020 TIMER0_OVF Timer/Counter0 Overflow
18 0x0022 SPI0 STC SPI1 Serial Transfer Complete
19 0x0024 USART0_RX USART0 Rx Complete
20 0x0026 USART0_UDRE USART0, Data Register Empty
21 0x0028 USART0_TX USART0, Tx Complete
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 84
Page 85
Vector No Program Address Source Interrupts definition
22 0x002A ADC ADC Conversion Complete
23 0x002C EE READY EEPROM Ready
24 0x002E ANALOG COMP Analog Comparator
25 0x0030 TWI Two-wire Serial Interface (I2C
26 0x0032 SPM READY Store Program Memory Ready
27 0x0034 USART0_START USART0 Start frame detection
28 0x0036 PCINT3 Pin Change Interrupt Request 3
29 0x0038 USART1_RX USART0 Rx Complete
30 0x003A USART1_UDRE USART0, Data Register Empty
31 0x003C USART1_TX USART0, Tx Complete
32 0x003E USART1_START USART1 Start frame detection
33 0x0040 TIMER3_CAPT Timer/Counter3 Capture Event
34 0x0042 TIMER3_COMPA Timer/Counter3 Compare Match A
ATmega328PB
INT - Interrupts
35 0x0044 TIMER3_COMPB Timer/Coutner3 Compare Match B
36 0x0046 TIMER3_OVF Timer/Counter3 Overflow
37 0x0048 CFD Clock failure detection interrrupt
38 0x004A PTC_EOC PTC End of Conversion
39 0x004C PTC_WCOMP PTC Window comparator mode
40 0x004E SPI1_STC SPI1 Serial Transfer Complete
41 0x0050 TWI1 TWI1 Transfer complete
42 0x0052 TIMER4_CAPT Timer/Counter3 Capture Event
43 0x0054 TIMER4_COMPA Timer/Counter3 Compare Match A
44 0x0056 TIMER4_COMPB Timer/Coutner3 Compare Match B
45 0x0058 TIMER4_OVF Timer/Counter3 Overflow
15.2 Register Description
15.2.1 Moving Interrupts Between Application and Boot Space
The MCU Control register controls the placement of the interrupt vector table.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 85
Page 86
ATmega328PB
INT - Interrupts
15.2.2 MCU Control Register
Name: MCUCR
Offset: 0x55
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x35
The MCU control register controls the placement of the interrupt vector table in order to move interrupts
between application and boot space.
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0
BODS BODSE PUD IVSEL IVCE
R/W R/W R/W R/W R/W
Bit 6 – BODS BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is
controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both
BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be
written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS
is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared
after three clock cycles.
Bit 5 – BODSE BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is
controlled by a timed sequence.
Bit 4 – PUD Pull-up Disable
When this bit is written to one, the pull ups in the I/O ports are disabled even if the DDxn and PORTxn
registers are configured to enable the pull ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory.
When this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of
the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses.
To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to
change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 86
Page 87
ATmega328PB
INT - Interrupts
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
same cycle as IVCE is written, and interrupts remain disabled until after the instruction following the write
to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status register
is unaffected by the automatic disabling.
Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the application section. If interrupt vectors are placed in the
application section and Boot Lock bit BLB12 is programmed, interrupts are disabled while executing from
the Boot Loader section.
Bit 0 – IVCE Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware
four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as
explained in the IVSEL description above. See the code example below.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR
mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ori r17, (1<<IVSEL)
out MCUCR, r17
ret
C Code Example
void Move_interrupts(void)
{
uchar temp;
/* GET MCUCR*/
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp|(1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = temp|(1<<IVSEL);
}
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 87
Page 88
16. EXTINT - External Interrupts
The external interrupts are triggered by the INT pins or any of the PCINT pins. Observe that, if enabled,
the interrupts will trigger even if the INT or PCINT pins are configured as outputs. This feature provides a
way of generating a software interrupt.
The Pin Change Interrupt Request 3 (PCI3) will trigger if any enabled PCINT[27:24] pin toggles. The Pin
Change Interrupt Request 2 (PCI2) will trigger if any enabled PCINT[23:16] pin toggles. The Pin Change
Interrupt Request 1 (PCI1) will trigger if any enabled PCINT[14:8] pin toggles. The Pin Change Interrupt
Request 0 (PCI0) will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK3, PCMSK2, PCMSK1
and PCMSK0 registers control which pins contribute to the pin change interrupts. Pin change interrupts
on PCINT are detected asynchronously. This implies that these interrupts can be used for waking the part
from sleep modes other than Idle mode.
The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the External Interrupt Control Register A (EICRA). When the external
interrupts are enabled and are configured as level-triggered, the interrupts will trigger as long as the pin is
held low. Note that recognition of falling or rising edge interrupts on INT requires the presence of an I/O
clock. Low level interrupt on INT is detected asynchronously. This implies that this interrupt can be used
for waking the part from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes
except Idle mode.
ATmega328PB
EXTINT - External Interrupts
Note: If a level triggered interrupt is used for wake-up from power-down, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears
before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
start-up time is defined by the SUT and CKSEL Fuses.
Related Links
System Control and Reset
Clock Systems and Their Distribution
System Clock and Clock Options
16.1 Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in the following figure.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 88
Page 89
Figure 16-1. Timing of Pin Change Interrupts
LE
D Q
D Q
clk
pin
PCINT[i] bit
(of PCMSK
n
)
D Q D Q D Q
clk
pcint_sync pcint_setflag
0
7
PCIF
n
(interrupt
flag)
PCINT[i] pin
pin_lat
pin_sync
clk
pcint_in[i]
pcint_syn
pcint_setflag
PCIF
n
pin_lat
pin_sync
pcint_in[i]
ATmega328PB
EXTINT - External Interrupts
Related Links
System Control and Reset
Clock Systems and Their Distribution
System Clock and Clock Options
16.2 Register Description
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 89
Page 90
ATmega328PB
EXTINT - External Interrupts
16.2.1 External Interrupt Control Register A
Name: EICRA
Offset: 0x69
Reset: 0x00
Property: -
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
ISC1 [1:0] ISC0 [1:0]
R/W R/W R/W R/W
Bits 3:2 – ISC1 [1:0] Interrupt Sense Control 1
The external Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT1 pin that activates the interrupt are
defined in the table below. The value on the INT1 pin is sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter
pulses are not recommended to generate an interrupt. If the low-level interrupt is selected, the low level
must be held until the completion of the currently executing instruction to generate an interrupt.
Value Description
00 The low level of INT1 generates an interrupt request.
01 Any logical change on INT1 generates an interrupt request.
10 The falling edge of INT1 generates an interrupt request.
11 The rising edge of INT1 generates an interrupt request.
Bits 1:0 – ISC0 [1:0] Interrupt Sense Control 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT0 pin that activates the interrupt are
defined in table below. The value on the INT0 pin is sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter
pulses are not guaranteed to generate an interrupt. If the low-level interrupt is selected, the low level must
be held until the completion of the currently executing instruction to generate an interrupt.
Value Description
00 The low level of INT0 generates an interrupt request.
01 Any logical change on INT0 generates an interrupt request.
10 The falling edge of INT0 generates an interrupt request.
11 The rising edge of INT0 generates an interrupt request.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 90
Page 91
ATmega328PB
EXTINT - External Interrupts
16.2.2 External Interrupt Mask Register
Name: EIMSK
Offset: 0x3D
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1D
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0
INT1 INT0
R/W R/W
Bit 1 – INT1 External Interrupt Request 1 Enable
When the INT1 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is
enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control
Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the
INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as
an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt
Vector.
Bit 0 – INT0 External Interrupt Request 0 Enable
When the INT0 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is
enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control
Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the
INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as
an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt
Vector.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 91
Page 92
ATmega328PB
EXTINT - External Interrupts
16.2.3 External Interrupt Flag Register
Name: EIFR
Offset: 0x3C
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1C
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0
INTF1 INTF0
R/W R/W
Bit 1 – INTF1 External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 will be set. If the I-bit
in SREG and the INT1 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it. This flag is always cleared when INT1 is configured as a level interrupt.
Bit 0 – INTF0 External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 will be set. If the I-bit
in SREG and the INT0 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it. This flag is always cleared when INT0 is configured as a level interrupt.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 92
Page 93
ATmega328PB
EXTINT - External Interrupts
16.2.4 Pin Change Interrupt Control Register
Name: PCICR
Offset: 0x68
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
PCIE3 PCIE2 PCIE1 PCIE0
R/W R/W R/W R/W
Bit 3 – PCIE3 Pin Change Interrupt Enable 3
When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is
enabled. Any change on any enabled PCINT[27:24] pin will cause an interrupt. The corresponding
interrupt of pin change interrupt request is executed from the PCI3 Interrupt Vector. PCINT[27:24] pins
are enabled individually by the PCMSK3 register.
Bit 2 – PCIE2 Pin Change Interrupt Enable 2
When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is
enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding
interrupt of pin change interrupt request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins
are enabled individually by the PCMSK2 register.
Bit 1 – PCIE1 Pin Change Interrupt Enable 1
When the PCIE1 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 1 is
enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt
of pin change interrupt request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are enabled
individually by the PCMSK1 register.
Bit 0 – PCIE0 Pin Change Interrupt Enable 0
When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt
of pin change interrupt request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled
individually by the PCMSK0 register.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 93
Page 94
ATmega328PB
EXTINT - External Interrupts
16.2.5 Pin Change Interrupt Flag Register
Name: PCIFR
Offset: 0x3B
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x1B
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
PCIF3 PCIF2 PCIF1 PCIF0
R/W R/W R/W R/W
Bit 3 – PCIF3 Pin Change Interrupt Flag 3
When a logic change on any PCINT[27:24] pin triggers an interrupt request, PCIF3 will be set. If the I-bit
in SREG and the PCIE3 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
'1' to it.
Bit 2 – PCIF2 Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 will be set. If the I-bit
in SREG and the PCIE2 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
'1' to it.
Bit 1 – PCIF1 Pin Change Interrupt Flag 1
When a logic change on any PCINT[14:8] pin triggers an interrupt request, PCIF1 will be set. If the I-bit in
SREG and the PCIE1 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it.
Bit 0 – PCIF0 Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 will be set. If the I-bit in
SREG and the PCIE0 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 94
Page 95
ATmega328PB
EXTINT - External Interrupts
16.2.6 Pin Change Mask Register 3
Name: PCMSK3
Offset: 0x73
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
PCINT[27:24]
R/W R/W R/W R/W
Bits 3:0 – PCINT[27:24] Pin Change Enable Mask
Each PCINT[27:24]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[27:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[27:24] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 95
Page 96
ATmega328PB
EXTINT - External Interrupts
16.2.7 Pin Change Mask Register 2
Name: PCMSK2
Offset: 0x6D
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7:0 – PCINT[23:16] Pin Change Enable Mask
Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[23:16] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
PCINT[23:16]
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 96
Page 97
ATmega328PB
EXTINT - External Interrupts
16.2.8 Pin Change Mask Register 1
Name: PCMSK1
Offset: 0x6C
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0
PCINT[14:8]
R/W R/W R/W R/W R/W R/W R/W
Bits 6:0 – PCINT[14:8] Pin Change Enable Mask
Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[15:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[15:8] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 97
Page 98
ATmega328PB
EXTINT - External Interrupts
16.2.9 Pin Change Mask Register 0
Name: PCMSK0
Offset: 0x6B
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7:0 – PCINT[7:0] Pin Change Enable Mask
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding
I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
PCINT[7:0]
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 98
Page 99
17. I/O-Ports
C
pin
Logic
R
pu
See Figure
"General Digital I/O" for
Details
Pxn
17.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This
means that the direction of one port pin can be changed without unintentionally changing the direction of
any other pin with the SBI and CBI instructions. The same applies when changing drive value (if
configured as an output) or enabling/disabling of pull-up resistors (if configured as an input). Each output
buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is
strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors
with a supply voltage invariant resistance. All I/O pins have protection diodes to both VCC and ground as
indicated in the following figure.
Figure 17-1. I/O Pin Equivalent Schematic
ATmega328PB
I/O-Ports
All registers and bit references in this section are written in general form. A lower case “x” represents the
numbering letter for the port, and a lower case “n” represents the bit number. However, when using the
register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit number
3 in Port B, here documented generally as PORTxn.
Three I/O memory address locations are allocated for each port, one each for the Data Register (Portx),
Data Direction Register (DDRx), and the Port Input Pins (PINx). The port input pins I/O location is readonly, while the data register and the data direction register are read/write. However, writing '1' to a bit in
the PINx register will result in a toggle in the corresponding bit in the data register. In addition, the Pull-up
Disable (PUD) bit in MCUCR disables the pull-up function for all pins in all ports when set.
Using the I/O port as general digital I/O is described in next section. Most port pins are multiplexed with
alternate functions for the peripheral features on the device. How each alternate function interferes with
the port pin is described in Alternate Port Functions section in this chapter. Refer to the individual module
sections for a full description of the alternate functions.
Enabling the alternate function of some of the port pins does not affect the use of the other pins in the
port as general digital I/O.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 99
Page 100
17.2 Ports as General Digital I/O
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
DLQ
Q
RESET
RESET
Q
QD
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER
The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows the
functional description of one I/O-port pin, here generically called Pxn.
Figure 17-2. General Digital I/O
ATmega328PB
I/O-Ports
(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
17.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in the register
description, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O
address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written to '1', Pxn is
configured as an output pin. If DDxn is written to '0', Pxn is configured as an input pin.
If PORTxn is written to '1' when the pin is configured as an input pin, the pull-up resistor is activated. To
switch the pull-up resistor off, PORTxn has to be written to '0' or the pin has to be configured as an output
pin. The port pins are tri-stated when the reset condition becomes active, even if no clocks are running.
If PORTxn is written to '1' when the pin is configured as an output pin, the port pin is driven high. If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 100
I/O
,
Loading...