ATmega328PB
AVR® Microcontroller with Core Independent Peripherals
and PicoPower® Technology
Introduction
The picoPower® ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves
throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed.
Features
High Performance, Low-Power AVR® 8-bit Microcontroller Family
• Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-Chip 2-Cycle Multiplier
• High Endurance Nonvolatile Memory Segments
– 32 KB of In-System Self-Programmable Flash program memory
– 1 KB EEPROM
– 2 KB Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Peripheral Features
– Peripheral Touch Controller (PTC)
• Capacitive Touch Buttons, Sliders, and Wheels
• 24 Self-Cap Channels and 144 Mutual Cap Channels
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode
– Real-Time Counter with Separate Oscillator
– Ten PWM Channels
– 8-channel 10-bit ADC
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Datasheet Complete
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ATmega328PB
– Two Programmable Serial USARTs
– Two Master/Slave SPI Serial Interfaces
– Two Byte-Oriented Two-Wire Serial Interfaces (Philips I2C Compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-Chip Analog Comparator
– Interrupt and Wake-Up on Pin Change
• Special Microcontroller Features
– Power-On Reset and Programmable Brown-Out Detection
– Internal 8 MHz Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended
Standby
– Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failure
– Individual Serial Number to Represent a Unique ID
• I/O and Packages
– 27 Programmable I/O Lines
– 32-pin TQFP and 32-pin QFN /MLF
• Operating Voltage:
– 1.8 - 5.5V
• Temperature Range:
– -40°C to 105°C
• Speed Grade:
– 0 - 4 MHz @ 1.8 - 5.5V
– 0 - 10 MHz @ 2.7 - 5.5V
– 0 - 20 MHz @ 4.5 - 5.5V
• Power Consumption at 1 MHz, 1.8V, 25°C
– Active Mode: 0.24 mA
– Power-Down Mode: 0.2 μA
– Power-Save Mode: 1.3 μA (Including 32 kHz RTC)
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Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description...............................................................................................................10
2. Configuration Summary........................................................................................... 11
3. Ordering Information................................................................................................12
4. Block Diagram......................................................................................................... 13
5. Pin Configurations................................................................................................... 14
5.1. Pin Descriptions......................................................................................................................... 15
6. I/O Multiplexing........................................................................................................18
7. Resources............................................................................................................... 20
8. About Code Examples.............................................................................................21
9. AVR CPU Core........................................................................................................ 22
9.1. Overview.................................................................................................................................... 22
9.2. ALU – Arithmetic Logic Unit....................................................................................................... 23
9.3. Status Register...........................................................................................................................23
9.4. General Purpose Register File...................................................................................................26
9.5. Stack Pointer..............................................................................................................................27
9.6. Instruction Execution Timing...................................................................................................... 29
9.7. Reset and Interrupt Handling..................................................................................................... 30
10. AVR Memories.........................................................................................................33
10.1. Overview.................................................................................................................................... 33
10.2. In-System Reprogrammable Flash Program Memory................................................................33
10.3. SRAM Data Memory.................................................................................................................. 34
10.4. EEPROM Data Memory............................................................................................................. 35
10.5. I/O Memory.................................................................................................................................36
10.6. Register Description................................................................................................................... 37
11. System Clock and Clock Options............................................................................ 46
11.1. Clock Systems and Their Distribution........................................................................................ 46
11.2. Clock Sources............................................................................................................................ 47
11.3. Low-Power Crystal Oscillator..................................................................................................... 49
11.4. Low Frequency Crystal Oscillator...............................................................................................50
11.5. Calibrated Internal RC Oscillator................................................................................................52
11.6. 128 kHz Internal Oscillator......................................................................................................... 53
11.7. External Clock............................................................................................................................ 54
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ATmega328PB
11.8. Clock Output Buffer....................................................................................................................54
11.9. Timer/Counter Oscillator.............................................................................................................55
11.10. System Clock Prescaler............................................................................................................. 55
11.11. Register Description................................................................................................................... 55
12. CFD - Clock Failure Detection mechanism............................................................. 59
12.1. Overview.................................................................................................................................... 59
12.2. Features..................................................................................................................................... 59
12.3. Operations..................................................................................................................................59
12.4. Timing Diagram.......................................................................................................................... 61
12.5. Register Description................................................................................................................... 61
13. Power Management and Sleep Modes................................................................... 63
13.1. Overview.................................................................................................................................... 63
13.2. Sleep Modes.............................................................................................................................. 63
13.3. BOD Disable...............................................................................................................................64
13.4. Idle Mode....................................................................................................................................64
13.5. ADC Noise Reduction Mode...................................................................................................... 64
13.6. Power-Down Mode.....................................................................................................................65
13.7. Power-Save Mode......................................................................................................................65
13.8. Standby Mode............................................................................................................................ 66
13.9. Extended Standby Mode............................................................................................................66
13.10. Power Reduction Registers........................................................................................................66
13.11. Minimizing Power Consumption.................................................................................................66
13.12. Register Description...................................................................................................................68
14. System Control and Reset.......................................................................................74
14.1. Resetting the AVR......................................................................................................................74
14.2. Reset Sources............................................................................................................................74
14.3. Power-on Reset..........................................................................................................................75
14.4. External Reset............................................................................................................................76
14.5. Brown-out Detection...................................................................................................................76
14.6. Watchdog System Reset............................................................................................................77
14.7. Internal Voltage Reference.........................................................................................................77
14.8. Watchdog Timer......................................................................................................................... 78
14.9. Register Description................................................................................................................... 80
15. INT - Interrupts........................................................................................................ 84
15.1. Interrupt Vectors in ATmega328PB............................................................................................ 84
15.2. Register Description................................................................................................................... 85
16. EXTINT - External Interrupts................................................................................... 88
16.1. Pin Change Interrupt Timing.......................................................................................................88
16.2. Register Description................................................................................................................... 89
17. I/O-Ports.................................................................................................................. 99
17.1. Overview.................................................................................................................................... 99
17.2. Ports as General Digital I/O......................................................................................................100
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17.3. Alternate Port Functions...........................................................................................................103
17.4. Register Description................................................................................................................. 118
18. TC0 - 8-bit Timer/Counter0 with PWM...................................................................133
18.1. Features................................................................................................................................... 133
18.2. Overview.................................................................................................................................. 133
18.3. Timer/Counter Clock Sources.................................................................................................. 135
18.4. Counter Unit............................................................................................................................. 135
18.5. Output Compare Unit............................................................................................................... 136
18.6. Compare Match Output Unit.....................................................................................................138
18.7. Modes of Operation..................................................................................................................140
18.8. Timer/Counter Timing Diagrams.............................................................................................. 144
18.9. Register Description................................................................................................................. 146
19. TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM.................................................158
19.1. Features................................................................................................................................... 158
19.2. Overview.................................................................................................................................. 158
19.3. Accessing 16-bit Timer/Counter Registers...............................................................................159
19.4. Timer/Counter Clock Sources.................................................................................................. 162
19.5. Counter Unit............................................................................................................................. 162
19.6. Input Capture Unit.................................................................................................................... 163
19.7. Compare Match Output Unit.....................................................................................................165
19.8. Output Compare Units..............................................................................................................166
19.9. Modes of Operation..................................................................................................................168
19.10. Timer/Counter Timing Diagrams.............................................................................................. 175
19.11. Register Description.................................................................................................................177
20. Timer/Counter 0, 1, 3, 4 Prescalers.......................................................................214
20.1. Internal Clock Source............................................................................................................... 214
20.2. Prescaler Reset........................................................................................................................214
20.3. External Clock Source..............................................................................................................214
20.4. Register Description................................................................................................................. 216
21. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation...................218
21.1. Features................................................................................................................................... 218
21.2. Overview.................................................................................................................................. 218
21.3. Timer/Counter Clock Sources.................................................................................................. 220
21.4. Counter Unit............................................................................................................................. 220
21.5. Output Compare Unit............................................................................................................... 221
21.6. Compare Match Output Unit.....................................................................................................223
21.7. Modes of Operation..................................................................................................................224
21.8. Timer/Counter Timing Diagrams.............................................................................................. 228
21.9. Asynchronous Operation of Timer/Counter2............................................................................229
21.10. Timer/Counter Prescaler.......................................................................................................... 231
21.11. Register Description................................................................................................................. 231
22. OCM - Output Compare Modulator....................................................................... 246
22.1. Overview.................................................................................................................................. 246
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ATmega328PB
22.2. Description............................................................................................................................... 246
23. SPI – Serial Peripheral Interface........................................................................... 248
23.1. Features................................................................................................................................... 248
23.2. Overview.................................................................................................................................. 248
23.3. SS Pin Functionality................................................................................................................. 252
23.4. Data Modes..............................................................................................................................252
23.5. Register Description................................................................................................................. 253
24. USART - Universal Synchronous Asynchronous Receiver Transceiver................262
24.1. Features................................................................................................................................... 262
24.2. Overview.................................................................................................................................. 262
24.3. Block Diagram.......................................................................................................................... 262
24.4. Clock Generation......................................................................................................................263
24.5. Frame Formats.........................................................................................................................266
24.6. USART Initialization................................................................................................................. 267
24.7. Data Transmission – The USART Transmitter......................................................................... 268
24.8. Data Reception – The USART Receiver.................................................................................. 270
24.9. Asynchronous Data Reception.................................................................................................273
24.10. Multi-Processor Communication Mode.................................................................................... 277
24.11. Examples of Baud Rate Setting............................................................................................... 278
24.12. Register Description.................................................................................................................281
25. USARTSPI - USART in SPI Mode.........................................................................291
25.1. Features................................................................................................................................... 291
25.2. Overview.................................................................................................................................. 291
25.3. Clock Generation......................................................................................................................291
25.4. SPI Data Modes and Timing.....................................................................................................292
25.5. Frame Formats.........................................................................................................................292
25.6. Data Transfer............................................................................................................................294
25.7. AVR USART MSPIM vs. AVR SPI............................................................................................295
25.8. Register Description................................................................................................................. 296
26. TWI - Two-Wire Serial Interface............................................................................ 297
26.1. Features................................................................................................................................... 297
26.2. Two-Wire Serial Interface Bus Definition..................................................................................297
26.3. Data Transfer and Frame Format.............................................................................................298
26.4. Multi-Master Bus Systems, Arbitration, and Synchronization...................................................301
26.5. Overview of the TWI Module.................................................................................................... 303
26.6. Using the TWI...........................................................................................................................305
26.7. Transmission Modes................................................................................................................ 308
26.8. Multi-Master Systems and Arbitration...................................................................................... 326
26.9. Register Description................................................................................................................. 327
27. AC - Analog Comparator....................................................................................... 335
27.1. Overview.................................................................................................................................. 335
27.2. Analog Comparator Multiplexed Input...................................................................................... 335
27.3. Register Description................................................................................................................. 336
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ATmega328PB
28. ADC - Analog-to-Digital Converter........................................................................ 340
28.1. Features................................................................................................................................... 340
28.2. Overview.................................................................................................................................. 340
28.3. Starting a Conversion...............................................................................................................342
28.4. Prescaling and Conversion Timing...........................................................................................343
28.5. Changing Channel or Reference Selection.............................................................................. 345
28.6. ADC Noise Canceler................................................................................................................ 347
28.7. ADC Conversion Result........................................................................................................... 350
28.8. Temperature Measurement...................................................................................................... 351
28.9. Register Description................................................................................................................. 351
29. PTC - Peripheral Touch Controller.........................................................................360
29.1. Features................................................................................................................................... 360
29.2. Overview.................................................................................................................................. 360
29.3. Block Diagram.......................................................................................................................... 361
29.4. Signal Description.................................................................................................................... 362
29.5. System Dependencies............................................................................................................. 362
29.6. Functional Description..............................................................................................................363
30. debugWIRE On-chip Debug System.....................................................................364
30.1. Features................................................................................................................................... 364
30.2. Overview.................................................................................................................................. 364
30.3. Physical Interface.....................................................................................................................364
30.4. Software Breakpoints............................................................................................................... 365
30.5. Limitations of debugWIRE........................................................................................................365
30.6. Register Description................................................................................................................. 365
31. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................367
31.1. Features................................................................................................................................... 367
31.2. Overview.................................................................................................................................. 367
31.3. Application and Boot Loader Flash Sections............................................................................367
31.4. Read-While-Write and No Read-While-Write Flash Sections...................................................368
31.5. Entering the Boot Loader Program...........................................................................................370
31.6. Boot Loader Lock Bits.............................................................................................................. 371
31.7. Addressing the Flash During Self-Programming...................................................................... 372
31.8. Self-Programming the Flash.....................................................................................................373
31.9. Register Description................................................................................................................. 381
32. MEMPROG - Memory Programming.....................................................................384
32.1. Program And Data Memory Lock Bits...................................................................................... 384
32.2. Fuse Bits.................................................................................................................................. 385
32.3. Signature Bytes........................................................................................................................387
32.4. Calibration Byte........................................................................................................................388
32.5. Serial Number.......................................................................................................................... 388
32.6. Page Size.................................................................................................................................390
32.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................390
32.8. Parallel Programming...............................................................................................................392
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ATmega328PB
32.9. Serial Downloading.................................................................................................................. 399
33. Electrical Characteristics....................................................................................... 405
33.1. Absolute Maximum Ratings......................................................................................................405
33.2. DC Characteristics................................................................................................................... 405
33.3. Power Consumption................................................................................................................. 407
33.4. Speed Grades.......................................................................................................................... 408
33.5. Clock Characteristics................................................................................................................409
33.6. System and Reset Characteristics........................................................................................... 410
33.7. SPI Timing Characteristics....................................................................................................... 411
33.8. Two-Wire Serial Interface Characteristics................................................................................ 412
33.9. ADC Characteristics................................................................................................................. 414
33.10. Parallel Programming Characteristics......................................................................................415
34. Typical Characteristics...........................................................................................418
34.1. Active Supply Current...............................................................................................................418
34.2. Idle Supply Current...................................................................................................................421
34.3. ATmega328PB Supply Current of I/O Modules........................................................................423
34.4. Power-Down Supply Current....................................................................................................424
34.5. Pin Pull-Up............................................................................................................................... 425
34.6. Pin Driver Strength................................................................................................................... 428
34.7. Pin Threshold and Hysteresis.................................................................................................. 430
34.8. BOD Threshold.........................................................................................................................433
34.9. Analog Comparator Offset........................................................................................................436
34.10. Internal Oscillator Speed..........................................................................................................437
34.11. Current Consumption of Peripheral Units.................................................................................440
34.12. Current Consumption in Reset and Reset Pulse Width........................................................... 443
35. Register Summary.................................................................................................445
36. Instruction Set Summary....................................................................................... 449
37. Packaging Information...........................................................................................454
37.1. 32A...........................................................................................................................................454
37.2. 32-Pin VQFN............................................................................................................................455
38. Errata.....................................................................................................................456
38.1. Rev. A.......................................................................................................................................456
38.2. Rev. B.......................................................................................................................................456
38.3. Rev. C - D.................................................................................................................................457
38.4. Rev. A - D.................................................................................................................................457
39. Revision History.....................................................................................................458
The Microchip Web Site.............................................................................................. 460
Customer Change Notification Service........................................................................460
Customer Support....................................................................................................... 460
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ATmega328PB
Microchip Devices Code Protection Feature............................................................... 460
Legal Notice.................................................................................................................461
Trademarks................................................................................................................. 461
Quality Management System Certified by DNV...........................................................462
Worldwide Sales and Service......................................................................................463
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1. Description
The ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves
throughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
The core combines a rich instruction set with 32 general purpose working registers. All the 32 registers
are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega328PB provides the following features: 32 KB of In-System Programmable Flash with ReadWhile-Write capabilities, 1 KB EEPROM, 2 KB SRAM, 27 general purpose I/O lines, 32 general purpose
working registers, five flexible Timer/Counters with compare modes, internal and external interrupts, two
serial programmable USART, two byte-oriented two-wire Serial Interface (I2C), two SPI serial ports, an 8channel 10-bit ADC in TQFP and QFN/MLF package, a programmable Watchdog Timer with internal
Oscillator, Clock failure detection mechanism, and six software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, USART, two-wire Serial Interface, SPI
port, and interrupt system to continue functioning. PTC with enabling up to 24 self-cap and 144 mutualcap sensors. The Power-Down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or hardware reset. In Power-Save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
Also ability to run PTC in Power-Save mode/wake-up on touch and Dynamic ON/OFF of PTC analog and
digital portion. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer, PTC, and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/
resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption.
ATmega328PB
Description
The device is manufactured using high-density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the ATmega328PB is a powerful microcontroller that
provides a highly flexible and cost-effective solution to many embedded control applications.
The ATmega328PB is supported by a full suite of program and system development tools including C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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DS40001906C-page 10
2. Configuration Summary
Features ATmega328PB
Pin count 32
Flash (KB) 32
SRAM (KB) 2
EEPROM (KB) 1
General Purpose I/O pins 27
SPI 2
TWI (I2C) 2
USART 2
ADC 10-bit 15 ksps
ADC channels 8
ATmega328PB
Configuration Summary
AC propagation delay 400 ns (Typical)
8-bit Timer/Counters 2
16-bit Timer/Counters 3
PWM channels 10
PTC Available
Clock Failure Detector (CFD) Available
Output Compare Modulator (OCM1C2) Available
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3. Ordering Information
ATmega328PB
Ordering Information
Speed [MHz] Power Supply [V] Ordering Code
(2)
20 1.8 - 5.5 ATmega328PB-AU
ATmega328PB-AUR
ATmega328PB-MU
ATmega328PB-MUR
ATmega328PB-AN
ATmega328PB-ANR
ATmega328PB-MN
ATmega328PB-MNR
Note:
1. This device can also be supplied in wafer form. Contact your local Microchip sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape & Reel.
(3)
(3)
(3)
(3)
Package
32A
32A
32MS1
32MS1
32A
32A
32MS1
32MS1
(1)
Operational Range
Industrial
(-40°C to 85°C)
Industrial
(-40°C to 105°C)
Package Type
32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32MS1 32-pad, 5.0x5.0x0.9 mm body, Lead Pitch 0.50 mm, Very-thin Fine pitch, Quad Flat No Lead Package
(VQFN)
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4. Block Diagram
CPU
USART 0
SPI 1
ADC
ADC[7:0]
AREF
RxD0
TxD0
XCK0
MISO1
MOSI1
SCK1
SS1
I/O
PORTS
D
A
T
A
B
U
S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
debugWire
I
N
/
O
U
T
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI 0
AC
AIN0
AIN1
ACO
EEPROM
EEPROMIF
PTC
X[15:0]
Y[23:0]
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 3
(16-bit)
TC 4
(16-bit)
OC3A/B
T3
ICP3
OC4A/B
T4
ICP4
TC 2
(8-bit async)
TWI 0
TWI 1
SDA0
SCL0
SDA1
SCL1
USART 1
RxD1
TxD1
XCK1
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz
XOSC
External
clock
Power
Supervision
POR/BOD &
RESET
XTAL2 /
TOSC2
RESET
XTAL1 /
TOSC1
16MHz LP
XOSC
Crystal failure detection
PCINT[27:0]
INT[1:0]
T0
OC0A
OC0B
MISO0
MOSI0
SCK0
SS0
OC2A
OC2B
PB[7:0]
PC[6 :0]
PD[7:0]
PE[3:0]
PE[3:2], PC[5:0]
AREF
PB[5:0], PE[1:0], PD[7:0]
PB[5:0], PE[1:0], PD[7:0], PE[3:2], PC[5:0]
PE[3:0], PD[7:0], PC[6:0], PB[7:0]
PD3, PD2
PB1, PB2
PD5
PB0
PB3
PD3
PD0, PD2
PE3
PE2
PD1, PD2
PE1
PE0
PD0
PD1
PD4
PC0
PE3
PC1
PE2
PC4
PC5
PE0
PE1
PB4
PB3
PB5
PD4
PD6
PD5
PB4
PB3
PB5
PB2
SPIPROG
PARPROG
PD6
PD7
PE0
Figure 4-1. Block Diagram
ATmega328PB
Block Diagram
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5. Pin Configurations
1
2
3
4
32
31
30
29
28
27
26
5
6
7
8
24
23
22
21
20
19
18
17
25
9
10
11
12
13
14
15
16
PD0 (PTCXY/OC3A/RXD0)
PD1 (PTCXY/OC4A/TXD0)
PD2 (PTCXY/INT0/OC3B/OC4B)
PC6 (RESET)
PC2 (ADC2/PTCY)
PC3 (ADC3/PTCY)
PC4 (ADC4/PTCY/SDA0)
PC5 (ADC5/PTCY/SCL0)
PC0 (ADC0/PTCY/MISO1)
PC1 (ADC1/PTCY/SCK1)
GND
PE2 (ADC6/PTCY/ICP3/SS1)
AVCC
AREF
PE3 (ADC7/PTCY/T3/MOSI1)
(XCK0/T0/PTCXY) PD4
GND
VCC
(SDA1/ICP4/ACO/PTCXY) PE0
(SCL1/T4/PTCXY) PE1
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(PTCXY/AIN1) PD7
(OC1A/PTCXY) PB1
(SS0/OC1B/PTCXY) PB2
(MISO0/RXD1/PTCXY) PB4
(OC2B/INT1/PTCXY) PD3
(OC0B/T1/PTCXY) PD5
(OC0A/PTCXY/AIN0) PD6
(ICP1/CLKO/PTCXY) PB0
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
PB5 (PTCXY/XCK1/SCK0)
Figure 5-1. 32 TQFP Pinout ATmega328PB
ATmega328PB
Pin Configurations
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Figure 5-2. 32 VQFN Pinout ATmega328PB
1
2
3
4
32
31
30
29
28
27
26
5
6
7
8
24
23
22
21
20
19
18
17
25
9
10
11
12
13
14
15
16
PD0 (PTCXY/OC3A/RXD0)
PD1 (PTCXY/OC4A/TXD0)
PD2 (PTCXY/INT0/OC3B/OC4B)
PC6 (RESET)
PC2 (ADC2/PTCY)
PC3 (ADC3/PTCY)
PC4 (ADC4/PTCY/SDA0)
PC5 (ADC5/PTCY/SCL0)
PC0 (ADC0/PTCY/MISO1)
PC1 (ADC1/PTCY/SCK1)
GND
PE2 (ADC6/PTCY/ICP3/SS1)
AVCC
AREF
PE3 (ADC7/PTCY/T3/MOSI1)
(PTCXY/AIN1) PD7
(OC1A/PTCXY) PB1
(SS0/OC1B/PTCXY) PB2
(MISO0/RXD1/PTCXY) PB4
(OC0B/T1/PTCXY) PD5
(OC0A/PTCXY/AIN0) PD6
(ICP1/CLKO/PTCXY) PB0
(XCK0/T0/PTCXY) PD4
GND
VCC
(SDA1/ICP4/ACO/PTCXY) PE0
(SCL1/T4/PTCXY) PE1
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(OC2B/INT1/PTCXY) PD3
Bottom pad should be
soldered to ground
PB5 (PTCXY/XCK1/SCK0)
ATmega328PB
Pin Configurations
5.1 Pin Descriptions
5.1.1 VCC
Digital supply voltage pin.
5.1.2 GND
Ground.
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Datasheet Complete
DS40001906C-page 15
5.1.3 Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated during a reset condition even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] input
for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
5.1.4 Port C (PC[5:0])
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The PC[5:0]
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated during a reset condition even if the clock is not running.
ATmega328PB
Pin Configurations
5.1.5 PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics
of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are
not guaranteed to generate a Reset.
The various special features of Port C are elaborated in the Alternate Functions of Port C section.
5.1.6 Port D (PD[7:0])
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated during a reset condition even if the clock is not running.
5.1.7 Port E (PE[3:0])
Port E is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port E
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
E pins are tri-stated during a reset condition even if the clock is not running.
5.1.8 AV
CC
AVCC is the supply voltage pin for the A/D Converter, PC[3:0], and PE[3:2]. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that PC[6:4] use digital supply voltage, VCC.
5.1.9 AREF
AREF is the analog reference pin for the A/D Converter.
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DS40001906C-page 16
5.1.10 ADC[7:6]
In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are
powered by the analog supply and serve as 10-bit ADC channels.
ATmega328PB
Pin Configurations
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Datasheet Complete
DS40001906C-page 17
ATmega328PB
I/O Multiplexing
6. I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively, it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
No
PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C USART I2C SPI
1 PD[3] INT1 PCINT19 X3 Y11 OC2B
2 PD[4] PCINT20 X4 Y12 T0 XCK0
3 PE[0] PCINT24 ACO X8 Y16 ICP4 SDA1
4 VCC
5 GND
6 PE[1] PCINT25 X9 Y17 T4 SCL1
7 PB[6] PCINT6 XTAL1/TOSC1
8 PB[7] PCINT7 XTAL2/TOSC2
9 PD[5] PCINT21 X5 Y13 OC0B / T1
10 PD[6] PCINT22 AIN0 X6 Y14 OC0A
11 PD[7] PCINT23 AIN1 X7 Y15
12 PB[0] PCINT0 X10 Y18 CLKO ICP1
13 PB[1] PCINT1 X11 Y19 OC1A
14 PB[2] PCINT2 X12 Y20 OC1B SS0
15 PB[3] PCINT3 X13 Y21 OC2A TXD1 MOSI0
16 PB[4] PCINT4 X14 Y22 RXD1 MISO0
17 PB[5] PCINT5 X15 Y23 XCK1 SCK0
18 AVCC
19 PE[2] PCINT26 ADC6 Y6 ICP3 SS1
20 AREF
21 GND
22 PE[3] PCINT27 ADC7 Y7 T3 MOSI1
23 PC[0] PCINT8 ADC0 Y0 MISO1
24 PC[1] PCINT9 ADC1 Y1 SCK1
25 PC[2] PCINT10 ADC2 Y2
26 PC[3] PCINT11 ADC3 Y3
27 PC[4] PCINT12 ADC4 Y4 SDA0
28 PC[5] PCINT13 ADC5 Y5 SCL0
29 PC[6]/RESET PCINT14
30 PD[0] PCINT16 X0 Y8 OC3A RXD0
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Datasheet Complete
DS40001906C-page 18
ATmega328PB
I/O Multiplexing
No PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C USART I2C SPI
31 PD[1] PCINT17 X1 Y9 OC4A TXD0
32 PD[2] INT0 PCINT18 X2 Y10 OC3B / OC4B
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DS40001906C-page 19
7. Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
ATmega328PB
Resources
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 20
8. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
ATmega328PB
About Code Examples
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Datasheet Complete
DS40001906C-page 21
9. AVR CPU Core
Register file
Flash program
memory
Program
counter
Instruction
register
Instruction
decode
Data memory
ALU
Status
register
R0R1
R2R3
R4R5
R6R7
R8R9
R10R11
R12R13
R14R15
R16R17
R18R19
R20R21
R22R23
R24R25
R26 (XL)R27 (XH)
R28 (YL)R29 (YH)
R30 (ZL)R31 (ZH)
Stack
pointer
9.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must, therefore, be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 9-1. Block Diagram of the AVR Architecture
ATmega328PB
AVR CPU Core
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the register file, the operation is executed, and the result is
stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space
addressing – enabling efficient address calculations. One of these address pointers can be used as an
© 2018 Microchip Technology Inc.
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DS40001906C-page 22
ATmega328PB
AVR CPU Core
address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit
X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided into two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the Stack
Pointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table.
The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, SPI, and
other I/O functions. The I/O memory can be accessed directly, or as the data space locations following
those of the register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
9.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide
a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction
Set Summary section for a detailed description.
Related Links
Instruction Set Summary
9.3 Status Register
The Status register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status register is updated after all ALU operations, as specified in the instruction set
reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
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ATmega328PB
AVR CPU Core
The Status register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
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Datasheet Complete
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ATmega328PB
AVR CPU Core
9.3.1 Status Register
Name: SREG
Offset: 0x5F
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x3F
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
I T H S V N Z C
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – I Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable register is cleared,
none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a
bit in T can be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry flag is useful in BCD
arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag
V. See the Instruction Set Description for detailed information.
Bit 3 – V Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
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DS40001906C-page 25
Bit 1 – Z Zero Flag
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 0 – C Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
9.4 General Purpose Register File
The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the register file:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 9-2. AVR CPU General Purpose Working Registers
ATmega328PB
AVR CPU Core
Most of the instructions operating on the register file have direct access to all registers, and most of them
are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user data space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
9.4.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
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DS40001906C-page 26
15
XH
XL
0
X-register
707
0
R27
R26
15
YH
YL
0
Y-register
707
0
R29
R28
15
ZH
ZL
0
Z-register
707
0
R31
R30
ATmega328PB
AVR CPU Core
Figure 9-3. The X-, Y-, and Z-registers
In the different addressing modes, these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary
9.5 Stack Pointer
The Stack is mainly used for storing temporary data, local variables, and return addresses after interrupts
and subroutine calls. The Stack is implemented as growing from higher to lower memory locations. The
Stack Pointer register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack
Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point
above start of the SRAM. See the table for Stack Pointer details.
Table 9-1. Stack Pointer Instructions
Instruction Stack Pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
POP Incremented by 1 Data is popped from the stack
RET
RETI
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
Incremented by 2 Return address is popped from the stack with return from subroutine or
interrupt
return from interrupt
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ATmega328PB
AVR CPU Core
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH register will not be present.
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ATmega328PB
AVR CPU Core
9.5.1 Stack Pointer Register Low and High byte
Name: SPL and SPH
Offset: 0x5D
Reset: 0x4FF
Property: When addressing I/O Registers as data space the offset address is 0x3D
The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 15 14 13 12 11 10 9 8
Access
Reset 0 0 0 0 0 1 0 0
R R R R RW RW RW RW
SP11 SP10 SP9 SP8
Bit 7 6 5 4 3 2 1 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Access
Reset 1 1 1 1 1 1 1 1
RW RW RW RW RW RW RW RW
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – SP Stack Pointer Register
SPL and SPH are combined into SP.
Related Links
Accessing 16-bit Timer/Counter Registers
9.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clk
clock division is used. The figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power unit.
, directly generated from the selected clock source for the chip. No internal
CPU
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clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
ATmega328PB
AVR CPU Core
Figure 9-4. The Parallel Instruction Fetches and Instruction Executions
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU
operation using two register operands is executed and the result is stored back to the destination register.
Figure 9-5. Single Cycle ALU Operation
9.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset vector
each have a separate program vector in the program memory space. All interrupts are assigned
individual enable bits, which must be written logic one together with the global interrupt enable bit in the
Status register in order to enable the interrupt. Depending on the program counter value, interrupts may
be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and interrupt
vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vectors
can be moved to the start of the boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset vector can be moved to the start of the boot Flash section by programming the
BOOTRST Fuse.
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction
– RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program
counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and
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