Datasheet ATmega324PB Datasheet
ATmega324PB
AVR Microcontroller with Core Independent Peripherals
and PicoPower technology
Introduction
The picoPower® ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves
throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed.
Feature
High Performance, Low Power AVR® 8-Bit Microcontroller Family
• Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-Chip 2-cycle Multiplier
• High Endurance Non-Volatile Memory Segments
– 32KBytes of In-System Self-Programmable Flash Program Memory
– 1KBytes EEPROM
– 2KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 Years at 85°C
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-Scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits Through the JTAG Interface
• Peripheral Features
– Peripheral Touch Controller (PTC)
• Capacitive Touch Buttons, Sliders and Wheels
• 32 Self-Sap Channels and 256 Mutual Cap Channels
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
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ATmega324PB
– Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Ten PWM Channels
– 8-Channel 10-Bit ADC
• Differential Mode with Selectable Gain at 1×, 10× or 200×
– Three Programmable Serial USARTs
– Two Master/Slave SPI Serial Interfaces
– Two Byte-oriented 2-wire Serial Interfaces (Philips I2C Compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal 8 MHz Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended
Standby
– Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failure
– Individual Serial Number to Represent a Unique ID
• I/O and Packages
– 39 Programmable I/O Lines
– 44-Pin TQFP and 44-Pin QFN /MLF
• Operating Voltage:
– 1.8 - 5.5V
• Temperature Range:
– -40°C to 105°C
• Speed Grade:
– 0 - 4MHz @ 1.8 - 5.5V
– 0 - 10MHz @ 2.7 - 5.5.V
– 0 - 20MHz @ 4.5 - 5.5V
• Power Consumption at 1MHz, 1.8V, 25°C
– Active Mode: 0.24mA
– Power-Down Mode: 0.2μA
– Power-Save Mode: 1.3μA (Including 32kHz RTC)
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DS40001908A-page 2
Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description...............................................................................................................10
2. Configuration Summary........................................................................................... 11
3. Ordering Information ...............................................................................................12
4. Block Diagram......................................................................................................... 13
5. Pin Configurations................................................................................................... 14
5.1. Pin Descriptions......................................................................................................................... 14
6. I/O Multiplexing........................................................................................................16
7. General Information.................................................................................................18
7.1. Resources.................................................................................................................................. 18
7.2. About Code Examples................................................................................................................18
8. AVR CPU Core........................................................................................................ 19
8.1. Overview.................................................................................................................................... 19
8.2. ALU – Arithmetic Logic Unit....................................................................................................... 20
8.3. Status Register...........................................................................................................................20
8.4. General Purpose Register File...................................................................................................22
8.5. Stack Pointer..............................................................................................................................23
8.6. Accessing 16-bit Registers.........................................................................................................24
8.7. Instruction Execution Timing...................................................................................................... 24
8.8. Reset and Interrupt Handling..................................................................................................... 25
9. AVR Memories.........................................................................................................28
9.1. Overview.................................................................................................................................... 28
9.2. In-System Reprogrammable Flash Program Memory................................................................28
9.3. SRAM Data Memory.................................................................................................................. 29
9.4. EEPROM Data Memory............................................................................................................. 30
9.5. I/O Memory.................................................................................................................................31
9.6. Register Description...................................................................................................................32
10. System Clock and Clock Options............................................................................ 38
10.1. Clock Systems and Their Distribution........................................................................................ 38
10.2. Clock Sources............................................................................................................................ 39
10.3. Low Frequency Crystal Oscillator...............................................................................................41
10.4. Low Power Crystal Oscillator..................................................................................................... 42
10.5. Calibrated Internal RC Oscillator................................................................................................44
10.6. 128kHz Internal Oscillator.......................................................................................................... 45
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10.7. External Clock............................................................................................................................ 45
10.8. Timer/Counter Oscillator.............................................................................................................46
10.9. Clock Output Buffer....................................................................................................................47
10.10. System Clock Prescaler............................................................................................................. 47
10.11. Register Description...................................................................................................................47
11. CFD - Clock Failure Detection mechanism............................................................. 50
11.1. Overview.................................................................................................................................... 50
11.2. Features..................................................................................................................................... 50
11.3. Operations..................................................................................................................................50
11.4. Timing Diagram..........................................................................................................................52
11.5. Register Description...................................................................................................................52
12. PM - Power Management and Sleep Modes...........................................................53
12.1. Sleep Modes.............................................................................................................................. 53
12.2. BOD Disable...............................................................................................................................53
12.3. Idle Mode....................................................................................................................................54
12.4. ADC Noise Reduction Mode...................................................................................................... 54
12.5. Power-Down Mode.....................................................................................................................55
12.6. Power-Save Mode......................................................................................................................55
12.7. Standby Mode............................................................................................................................ 56
12.8. Extended Standby Mode............................................................................................................56
12.9. Power Reduction Registers........................................................................................................56
12.10. Minimizing Power Consumption.................................................................................................56
12.11. Register Description...................................................................................................................58
13. SCRST - System Control and Reset....................................................................... 63
13.1. Resetting the AVR...................................................................................................................... 63
13.2. Reset Sources............................................................................................................................63
13.3. Power-on Reset..........................................................................................................................64
13.4. External Reset............................................................................................................................65
13.5. Brown-out Detection...................................................................................................................65
13.6. Watchdog System Reset............................................................................................................66
13.7. Internal Voltage Reference.........................................................................................................66
13.8. Watchdog Timer......................................................................................................................... 67
13.9. Register Description...................................................................................................................69
14. INT- Interrupts..........................................................................................................73
14.1. Interrupt Vectors in ATmega324PB............................................................................................ 73
14.2. Register Description...................................................................................................................76
15. External Interrupts................................................................................................... 78
15.1. EXINT - External Interrupts........................................................................................................ 78
16. I/O-Ports.................................................................................................................. 86
16.1. Overview.................................................................................................................................... 86
16.2. Ports as General Digital I/O........................................................................................................87
16.3. Alternate Port Functions.............................................................................................................90
16.4. Register Description.................................................................................................................106
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17. TC0 - 8-bit Timer/Counter0 with PWM...................................................................114
17.1. Features................................................................................................................................... 114
17.2. Overview...................................................................................................................................114
17.3. Timer/Counter Clock Sources...................................................................................................116
17.4. Counter Unit............................................................................................................................. 116
17.5. Output Compare Unit................................................................................................................117
17.6. Compare Match Output Unit.....................................................................................................119
17.7. Modes of Operation..................................................................................................................120
17.8. Timer/Counter Timing Diagrams.............................................................................................. 124
17.9. Register Description.................................................................................................................126
18. TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM.................................................134
18.1. Features................................................................................................................................... 134
18.2. Overview.................................................................................................................................. 134
18.3. Accessing 16-bit Timer/Counter Registers...............................................................................135
18.4. Timer/Counter Clock Sources.................................................................................................. 138
18.5. Counter Unit............................................................................................................................. 138
18.6. Input Capture Unit.................................................................................................................... 139
18.7. Compare Match Output Unit.....................................................................................................141
18.8. Output Compare Units..............................................................................................................142
18.9. Modes of Operation..................................................................................................................144
18.10. Timer/Counter Timing Diagrams.............................................................................................. 151
18.11. Register Description.................................................................................................................153
19. Timer/Counter 0, 1, 3, 4 Prescalers.......................................................................179
19.1. Internal Clock Source...............................................................................................................179
19.2. Prescaler Reset........................................................................................................................179
19.3. External Clock Source..............................................................................................................179
19.4. Register Description.................................................................................................................180
20. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation...................182
20.1. Features................................................................................................................................... 182
20.2. Overview.................................................................................................................................. 182
20.3. Timer/Counter Clock Sources.................................................................................................. 184
20.4. Counter Unit............................................................................................................................. 184
20.5. Output Compare Unit............................................................................................................... 185
20.6. Compare Match Output Unit.....................................................................................................187
20.7. Modes of Operation..................................................................................................................188
20.8. Timer/Counter Timing Diagrams.............................................................................................. 192
20.9. Asynchronous Operation of Timer/Counter2............................................................................193
20.10. Timer/Counter Prescaler.......................................................................................................... 195
20.11. Register Description.................................................................................................................195
21. OCM - Output Compare Modulator....................................................................... 205
21.1. Overview.................................................................................................................................. 205
21.2. Description............................................................................................................................... 205
22. SPI – Serial Peripheral Interface........................................................................... 207
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22.1. Features................................................................................................................................... 207
22.2. Overview.................................................................................................................................. 207
22.3. SS Pin Functionality................................................................................................................. 211
22.4. Data Modes.............................................................................................................................. 211
22.5. Register Description.................................................................................................................212
23. USART - Universal Synchronous Asynchronous Receiver Transceiver................218
23.1. Features................................................................................................................................... 218
23.2. Overview.................................................................................................................................. 218
23.3. Block Diagram..........................................................................................................................218
23.4. Clock Generation......................................................................................................................219
23.5. Frame Formats.........................................................................................................................222
23.6. USART Initialization................................................................................................................. 223
23.7. Data Transmission – The USART Transmitter......................................................................... 224
23.8. Data Reception – The USART Receiver..................................................................................226
23.9. Asynchronous Data Reception.................................................................................................230
23.10. Multi-Processor Communication Mode.................................................................................... 234
23.11. Examples of Baud Rate Setting............................................................................................... 234
23.12. Register Description.................................................................................................................237
24. USARTSPI - USART in SPI Mode.........................................................................245
24.1. Features................................................................................................................................... 245
24.2. Overview.................................................................................................................................. 245
24.3. Clock Generation......................................................................................................................245
24.4. SPI Data Modes and Timing.....................................................................................................246
24.5. Frame Formats.........................................................................................................................246
24.6. Data Transfer............................................................................................................................248
24.7. AVR USART MSPIM vs. AVR SPI............................................................................................249
24.8. Register Description.................................................................................................................250
25. TWI - 2-wire Serial Interface..................................................................................251
25.1. Features................................................................................................................................... 251
25.2. Two-Wire Serial Interface Bus Definition..................................................................................251
25.3. Data Transfer and Frame Format.............................................................................................252
25.4. Multi-master Bus Systems, Arbitration, and Synchronization...................................................255
25.5. Overview of the TWI Module....................................................................................................256
25.6. Using the TWI...........................................................................................................................259
25.7. Transmission Modes................................................................................................................ 262
25.8. Multi-master Systems and Arbitration...................................................................................... 278
25.9. Register Description.................................................................................................................280
26. AC - Analog Comparator....................................................................................... 285
26.1. Overview.................................................................................................................................. 285
26.2. Analog Comparator Multiplexed Input......................................................................................285
26.3. Register Description.................................................................................................................286
27. ADC - Analog to Digital Converter.........................................................................289
27.1. Features................................................................................................................................... 289
27.2. Overview.................................................................................................................................. 289
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27.3. Starting a Conversion...............................................................................................................291
27.4. Prescaling and Conversion Timing...........................................................................................292
27.5. Changing Channel or Reference Selection..............................................................................295
27.6. ADC Noise Canceler................................................................................................................ 297
27.7. ADC Conversion Result........................................................................................................... 301
27.8. Register Description.................................................................................................................303
28. PTC - Peripheral Touch Controller.........................................................................309
28.1. Overview.................................................................................................................................. 309
28.2. Features................................................................................................................................... 309
28.3. Block Diagram..........................................................................................................................310
28.4. Signal Description.................................................................................................................... 310
28.5. System Dependencies............................................................................................................. 310
28.6. Functional Description..............................................................................................................312
29. JTAG Interface and On-chip Debug System......................................................... 313
29.1. Features................................................................................................................................... 313
29.2. Overview.................................................................................................................................. 313
29.3. TAP – Test Access Port............................................................................................................314
29.4. TAP Controller..........................................................................................................................315
29.5. Using the Boundary-scan Chain...............................................................................................316
29.6. Using the On-chip Debug System............................................................................................316
29.7. On-chip Debug Specific JTAG Instructions..............................................................................317
29.8. Using the JTAG Programming Capabilities..............................................................................317
29.9. Bibliography..............................................................................................................................318
29.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................318
29.11. Data Registers..........................................................................................................................319
29.12. Boundry-scan Specific JTAG Instructions................................................................................320
29.13. Boundary-scan Chain...............................................................................................................322
29.14. ATmega324PB Boundary-scan Order......................................................................................325
29.15. Boundary-scan Description Language Files............................................................................ 327
29.16. Register Description.................................................................................................................327
30. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................331
30.1. Features................................................................................................................................... 331
30.2. Overview.................................................................................................................................. 331
30.3. Application and Boot Loader Flash Sections............................................................................331
30.4. Read-While-Write and No Read-While-Write Flash Sections...................................................332
30.5. Entering the Boot Loader Program...........................................................................................334
30.6. Boot Loader Lock Bits.............................................................................................................. 335
30.7. Addressing the Flash During Self-Programming...................................................................... 336
30.8. Self-Programming the Flash.....................................................................................................337
30.9. Register Description.................................................................................................................345
31. MEMPROG- Memory Programming......................................................................347
31.1. Program And Data Memory Lock Bits......................................................................................347
31.2. Fuse Bits.................................................................................................................................. 348
31.3. Signature Bytes........................................................................................................................350
31.4. Calibration Byte........................................................................................................................350
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31.5. Serial Number.......................................................................................................................... 351
31.6. Page Size.................................................................................................................................353
31.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................354
31.8. Parallel Programming...............................................................................................................356
31.9. Serial Downloading.................................................................................................................. 363
31.10. Programming Via the JTAG Interface...................................................................................... 368
32. Electrical Characteristics....................................................................................... 383
32.1. Absolute Maximum Ratings......................................................................................................383
32.2. DC Characteristics................................................................................................................... 383
32.3. Speed Grades.......................................................................................................................... 385
32.4. Clock Characteristics................................................................................................................386
32.5. System and Reset Characteristics........................................................................................... 387
32.6. SPI Timing Characteristics.......................................................................................................388
32.7. Two-wire Serial Interface Characteristics.................................................................................389
32.8. ADC Characteristics.................................................................................................................391
32.9. Parallel Programming Characteristics...................................................................................... 394
33. Typical Characteristics...........................................................................................397
33.1. Active Supply Current...............................................................................................................397
33.2. Idle Supply Current...................................................................................................................401
33.3. Supply Current of IO Modules .................................................................................................403
33.4. Power-down Supply Current.................................................................................................... 404
33.5. Pin Pull-Up............................................................................................................................... 406
33.6. Pin Driver Strength...................................................................................................................409
33.7. Pin Threshold and Hysteresis...................................................................................................411
33.8. BOD Threshold.........................................................................................................................414
33.9. Analog Comparator Offset........................................................................................................417
33.10. Internal Oscillator Speed..........................................................................................................418
33.11. Current Consumption of Peripheral Units.................................................................................421
33.12. Current Consumption in Reset and Reset Pulse Width........................................................... 424
34. Register Summary.................................................................................................426
35. Instruction Set Summary....................................................................................... 431
36. Packaging Information...........................................................................................435
36.1. 44-pin TQFP.............................................................................................................................435
36.2. 44-pin VQFN............................................................................................................................ 436
37. Errata.....................................................................................................................437
37.1. Rev.A-H.................................................................................................................................... 437
37.2. Rev. I........................................................................................................................................ 437
37.3. Rev. J - K..................................................................................................................................437
38. Datasheet Revision History................................................................................... 438
The Microchip Web Site.............................................................................................. 440
Customer Change Notification Service........................................................................440
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ATmega324PB
Customer Support....................................................................................................... 440
Microchip Devices Code Protection Feature............................................................... 440
Legal Notice.................................................................................................................441
Trademarks................................................................................................................. 441
Quality Management System Certified by DNV...........................................................442
Worldwide Sales and Service......................................................................................443
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1. Description
The ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves
throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed.
The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega324PB provides the following features: 32K bytes of In-System Programmable Flash with
Read-While-Write capabilities, 1Kbytes EEPROM, 2Kbytes SRAM, 39 general purpose I/O lines, 32
general purpose working registers, five flexible Timer/Counters with compare modes, internal and
external interrupts, three serial programmable USART, two byte-oriented 2-wire Serial Interface (I2C), two
SPI serial port, a 8-channel 10-bit ADC with optional differential input stage with programmable gain, a
programmable Watchdog Timer with internal Oscillator, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the On-chip Debug system and programming, Clock failure detection mechanism
and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning.
PTC with enabling up to 32 self-cap and 256 mutual-cap sensors. The Power-down mode saves the
register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to
maintain a timer base while the rest of the device is sleeping. Also ability to run PTC in power-save mode/
wake-up on touch and Dynamic on/off of PTC analog and digital portion. The ADC Noise Reduction mode
stops the CPU and all I/O modules except asynchronous timer, PTC, and ADC to minimize switching
noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest
of the device is sleeping. This allows very fast start-up combined with low power consumption.
ATmega324PB
The device is manufactured using high density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the ATmega324PB is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega324PB is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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2. Configuration Summary
Features ATmega324PB
Pin count 44
Flash (KB) 32
SRAM (KB) 2
EEPROM (KB) 1
General Purpose I/O lines 39
SPI 2
TWI (I2C) 2
USART 3
ADC 10-bit 15ksps
Differential ADC mode Available
ADC channels 8
ATmega324PB
AC 1
8-bit Timer/Counters 2
16-bit Timer/Counters 3
PWM channels 10
PTC Available
Peripheral Touch Controller (PTC) channels (X- x Y-Lines) for mutual capacitance 256 (16 x 16)
Peripheral Touch Controller (PTC) channels for self capacitance (Y-Lines only) 32
Clock Failure Detector (CFD) Available
Output Compare Modulator (OCM1C2) Available
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3. Ordering Information
ATmega324PB
Speed [MHz] Power Supply [V] Ordering Code
20 1.8 - 5.5
ATmega324PB-AU
ATmega324PB-AUR
ATmega324PB-MU
ATmega324PB-MUR
ATmega324PB-AN
ATmega324PB-ANR
ATmega324PB-MN
ATmega324PB-MNR
Note: 1. This device can also be supplied in wafer form. Contact your local sales office for detailed
ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS
directive). Also Halide free and fully Green.
3. Tape & Reel.
(2)
(3)
(3)
(3)
(3)
Package
44A
44A
44M1
44M1
44A
44A
44M1
44M1
(1)
Operational Range
Industrial
(-40°C to 85°C)
Industrial
(-40°C to 105°C)
Package Type
44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
44M1 44-pad, 7 x 7 x 0.9mm body, Lead Pitch 0.50mm, Very-thin Fine pitch, Quad Flat No Lead Package/Quad
Flat No-Lead/Micro Lead Frame Package (VQFN/QFN/MLF)
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4. Block Diagram
CPU
USART 0
ADC
ADC[7:0]
AREF
RxD0
TxD0
XCK0
I/O
PORTS
D
A
T
A
B
U
S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
JTAG
I
N
/
O
U
T
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI 0
AC
AIN0
AIN1
ACO
ADCMUX
EEPROM
EEPROMIF
PTC
X[15:0]
Y[31:0]
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 3
(16-bit)
TC 4
(16-bit)
OC3A/B
T3
ICP3
OC4A/B
T4
ICP4
TC 2
(8-bit async)
TWI 0
TWI 1
SDA0
SCL0
SDA1
SCL1
USART 1
USART 2
RxD1
TxD1
XCK1
RxD2
TxD2
XCK2
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz
XOSC
External
clock
Power
Supervision
POR/BOD &
RESET
TOSC2
XTAL2
RESET
XTAL1
TOSC1
16MHz LP
XOSC
TCK
TMS
TDI
TDO
Crystal failure detection
PCINT[38:0]
INT[2:0]
T0
OC0A
OC0B
MISO0
MOSI0
SCK0
SS0
OC2A
OC2B
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[6:0]
SPI 1
MISO1
MOSI1
SCK1
SS1
Figure 4-1. Block Diagram
ATmega324PB
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DS40001908A-page 13
5. Pin Configurations
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
1
2
3
4
43
42
41
40
39
38
37
5
6
7
8
35
3422
21
20
19
18
17
36
9
10
11
12
13
14
15
16
AVCC
RESET
GND
VCC
(XTAL1) PE1
(XTAL2) PE0
PC7 (TOSC2)
PE4 (AREF)
GND
PB0 (PTCY/T0/XCK0)
PB1 (PTCY/T1/CLKO)
PB2 (AIN0/PTCY/INT2)
(MOSI0/ICP3/PTCY) PB5
(MISO0/OC3A/PTCY) PB6
44
32
31
30
29
28
27
26
24
23
25
33
(SCK0/OC3B/OC4B/PTCY) PB7
PB3 (AIN1/PTCY/OC0A)
PB4 (PTCY/OC0B/SS0)
PE5 (SDA1)
PE6 (SCL1)
PA0 (ADC0/PTCY)
PA1 (ADC1/PTCY)
PA2 (ADC2/PTCY)
PA3 (ADC3/PTCY)
PA4 (ADC4/PTCY)
PA5 (ADC5/PTCY)
PA6 (ADC6/PTCY)
PA7 (ADC7/PTCY)
PC6 (TOSC1)
PC4 (PTCXY/OC4A/TDO)
PC5 (PTCXY/ACO/TDI)
(TMS/ICP4/PTCXY) PC3
(TCK/T4/PTCXY) PC2
(SDA0/PTCXY) PC1
(SCL0/PTCXY) PC0
(MOSI1/TXD2/PTCXY) PE3
(MISO1/RXD2/PTCXY) PE2
(SS1/ICP1/OC2B/PTCXY) PD6
(OC1A/PTCXY) PD5
(XCK1/OC1B/PTCXY) PD4
(TXD1/INT1/PTCXY) PD3
(RXD1/INT0/PTCXY) PD2
(TXD0/PTCXY) PD1
(RXD0/T3/PTCXY) PD0
Figure 5-1. Pinout ATmega324PB
ATmega324PB
5.1 Pin Descriptions
5.1.1 VCC
Digital supply voltage.
5.1.2 GND
Ground.
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5.1.3 Port A (PA[7:0])
This port serves as analog inputs to the Analog-to-digital Converter.
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
5.1.4 Port B (PB[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
This port also serves the functions of various special features.
5.1.5 Port C (PC[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
ATmega324PB
This port also serves the functions of the JTAG interface, along with special features.
5.1.6 Port D (PD[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
This port also serves the functions of various special features.
5.1.7 Port E (PE6:0) XTAL1/XTAL2/AREF
This is a 7-bit bi-directional GPIO port with internal pull-up resistors (selected for each pin). The Port E
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated. Port pins
are tri-stated during a reset condition, even if the clock is not running. PE0 and PE1 are multiplexed with
XTAL1 and XTAL2 input. PE4 is multiplexed with AREF for the A/D Converter.
5.1.8 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a reset.
5.1.9 AVCC
AVCC is the supply voltage pin for Port A, PE4 (AREF) and the Analog-to-digital Converter. It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to
VCC through a low-pass filter.
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6. I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
No. PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
1 PB[5] PCINT13 Y29 ICP3 MOSI0
2 PB[6] PCINT14 Y30 OC3A MISO0
3 PB[7] PCINT15 Y31 OC3B OC4B SCK0
4 RESET
5 VCC
6 GND
7 PE[0] PCINT32 XTAL2
8 PE[1] PCINT33 XTAL1
9 PD[0] PCINT24 X0 Y8 T3 RxD0
10 PD[1] PCINT25 X1 Y9 TxD0
11 PD[2] INT0 PCINT26 X2 Y10 RxD1
12 PD[3] INT1 PCINT27 X3 Y11 TXD1
13 PD[4] PCINT28 X4 Y12 OC1B XCK1
14 PD[5] PCINT29 X5 Y13 OC1A
15 PD[6] PCINT30 X6 Y14 OC2B ICP1 SS1
16 PD[7] PCINT31 X7 Y15 OC2A XCK2 SCK1
17 PE[2] X8 Y16 RxD2 MISO1
18 PE[3] X9 Y17 TxD2 MOSI1
19 PC[0] PCINT16 X10 Y18 SCL0
20 PC[1] PCINT17 X11 Y19 SDA0
21 PC[2] PCINT18 X12 Y20 T4 TCK
22 PC[3] PCINT19 X13 Y21 ICP4 TMS
23 PC[4] PCINT20 X14 Y22 OC4A TDO
24 PC[5] PCINT21 ACO X15 Y23 TDI
25 PC[6] PCINT22 TOSC1
26 PC[7] PCINT23 TOSC2
27 AVCC
28 GND
29 PE[4] AREF
30 PA[7] PCINT7 ADC7 Y7
31 PA[6] PCINT6 ADC6 Y6
32 PA[5] PCINT5 ADC5 Y5
33 PA[4] PCINT4 ADC4 Y4
34 PA[3] PCINT3 ADC3 Y3
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ATmega324PB
No. PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
35 PA[2] PCINT2 ADC2 Y2
36 PA[1] PCINT1 ADC1 Y1
37 PA[0] PCINT0 ADC0 Y0
38 PE[5] SDA1
39 PE[6] SCL1
40 PB[0] PCINT8 Y24 T0 XCK0
41 PB[1] PCINT9 Y25 CLKO T1
42 PB[2] INT2 PCINT10 AIN0 Y26
43 PB[3] PCINT11 AIN1 Y27 OC0A
44 PB[4] PCINT12 Y28 OC0B SS0
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7. General Information
7.1 Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
7.2 About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confer with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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8. AVR CPU Core
Register file
Flash program
memory
Program
counter
Instruction
register
Instruction
decode
Data memory
ALU
Status
register
R0R1
R2R3
R4R5
R6R7
R8R9
R10R11
R12R13
R14R15
R16R17
R18R19
R20R21
R22R23
R24R25
R26 (XL)R27 (XH)
R28 (YL)R29 (YH)
R30 (ZL)R31 (ZH)
Stack
pointer
8.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 8-1. Block Diagram of the AVR Architecture
ATmega324PB
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
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The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt
Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from
0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide
a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction
Set Summary section for a detailed description.
Related Links
Instruction Set Summary
8.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set
Reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
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8.3.1 Status Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: SREG
Offset: 0x5F
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x3F
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
I T H S V N Z C
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared,
none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T: Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in
BCD arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S: Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the Instruction Set Description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
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Bit 0 – C: Carry Flag
15
XH
XL
0
X-register
707
0
R27
R26
15
YH
YL
0
Y-register
707
0
R29
R28
15
ZH
ZL
0
Z-register
707
0
R31
R30
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
8.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 8-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user Data Space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
ATmega324PB
8.4.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
Figure 8-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary
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8.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to
lower memory locations. The Stack Pointer Register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack
Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point
above start of the SRAM. See the table for Stack Pointer details.
Table 8-1. Stack Pointer Instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
ATmega324PB
CALL
ICALL
RCALL
POP Incremented by 1 Data is popped from the stack
RET
RETI
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
8.5.1 Stack Pointer Register Low and High byte
The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
Incremented by 2 Return address is popped from the stack with return from subroutine or
return from interrupt
Name: SPL and SPH
Offset: 0x5D
Reset: 0x8FF
Property: When addressing I/O Registers as data space the offset address is 0x3D
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Bit 15 14 13 12 11 10 9 8
Access
Reset 0 0 0 0 1 0 0 0
Bit 7 6 5 4 3 2 1 0
Access
Reset 1 1 1 1 1 1 1 1
R R R R RW RW RW RW
RW RW RW RW RW RW RW RW
SP[7:0]
Bits 11:0 – SP[11:0]: Stack Pointer Register
SPL and SPH are combined into SP.
8.6 Accessing 16-bit Registers
The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These
registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the
8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte
is then written into the temporary register. When the high byte of the 16-bit register is written, the
temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
SP[11:8]
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low
byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register
in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the
temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when
reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit
register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when
writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
8.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clk
clock division is used. The Figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
, directly generated from the selected clock source for the chip. No internal
CPU
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clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
ATmega324PB
Figure 8-4. The Parallel Instruction Fetches and Instruction Executions
The following figure shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 8-5. Single Cycle ALU Operation
8.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector
each have a separate program vector in the program memory space. All interrupts are assigned
individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the
Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may
be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt
Vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors
can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programming
the BOOTRST Fuse.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program
Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and
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ATmega324PB
hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic
one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled,
or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI
instruction. The following example shows how this can be used to avoid interrupts during the timed
EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
(1)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
(1)
1. Refer to About Code Examples.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before
any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
(1)
(1)
1. Refer to About Code Examples.
Related Links
Memory Programming
Boot Loader Support – Read-While-Write Self-Programming
About Code Examples
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8.8.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After
four clock cycles the program vector address for the actual interrupt handling routine is executed. During
this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump
to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs
when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles.
This increase comes in addition to the start-up time from the selected sleep mode. A return from an
interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter
(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in
SREG is set.
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9. AVR Memories
0x0000
0x3FFF
Program Memory
Application Flash Section
Boot Flash Section
9.1 Overview
This section describes the different memory types in the device. The AVR architecture has two main
memory spaces, the Data Memory and the Program Memory space. In addition, the device features an
EEPROM Memory for data storage. All memory spaces are linear and regular.
9.2 In-System Reprogrammable Flash Program Memory
The ATmega324PB contains 32K bytes on-chip in-system reprogrammable Flash memory for program
storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32K x 16. For
software security, the Flash Program memory space is divided into two sections - Boot Loader Section
and Application Program Section in the device .
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega324PB Program
Counter (PC) is 15 bits wide, thus addressing the 32K program memory locations. The operation of the
Boot Program section and associated Boot Lock bits for software protection are described in detail in
Boot Loader Support – Read-While-Write Self-Programming. Refer to Memory Programming for the
description on Flash data serial downloading using the SPI pins or the JTAG interface.
ATmega324PB
Constant tables can be allocated within the entire program memory address space, using the Load
Program Memory (LPM) instruction.
Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.
Figure 9-1. Program Memory Map ATmega324PB
Related Links
BTLDR - Boot Loader Support – Read-While-Write Self-Programming
MEMPROG- Memory Programming
Instruction Execution Timing
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9.3 SRAM Data Memory
(2048x8)
0x08FF
The following figure shows how the device SRAM Memory is organized.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60
- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 4352 data memory locations address both the Register File, the I/O memory, Extended I/O
memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64
location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096
locations address the internal data SRAM.
The five different addressing modes for the data memory cover:
• Direct
– The direct addressing reaches the entire data space.
• Indirect with Displacement
– The Indirect with Displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.
• Indirect
– In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
• Indirect with Pre-decrement
– The address registers X, Y, and Z are decremented.
• Indirect with Post-increment
– The address registers X, Y, and Z are incremented.
ATmega324PB
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2K
bytes of internal data SRAM in the device are all accessible through all these addressing modes.
Figure 9-2. Data Memory Map with 2048 byte internal data SRAM
9.3.1 Data Memory Access Times
The internal data SRAM access is performed in two clk
cycles as described in the following Figure.
CPU
© 2017 Microchip Technology Inc.
Datasheet Complete
DS40001908A-page 29
Figure 9-3. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
ATmega324PB
9.4 EEPROM Data Memory
The ATmega324PB contains 1K bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following,
specifying the EEPROM Address registers, the EEPROM Data register, and the EEPROM Control
register.
See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programming
mode.
Related Links
MEMPROG- Memory Programming
9.4.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 9-2. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall
slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. Please refer to Preventing EEPROM Corruption for
details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to
the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction
is executed.
© 2017 Microchip Technology Inc.
Datasheet Complete
DS40001908A-page 30
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