Datasheet ATmega324PB Datasheet

ATmega324PB
AVR Microcontroller with Core Independent Peripherals
and PicoPower technology

Introduction

The picoPower® ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power consumption versus processing speed.

Feature

High Performance, Low Power AVR® 8-Bit Microcontroller Family
Advanced RISC Architecture – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20MHz – On-Chip 2-cycle Multiplier
High Endurance Non-Volatile Memory Segments – 32KBytes of In-System Self-Programmable Flash Program Memory – 1KBytes EEPROM – 2KBytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data Retention: 20 Years at 85°C – Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-Scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits Through the JTAG Interface
Peripheral Features – Peripheral Touch Controller (PTC)
Capacitive Touch Buttons, Sliders and Wheels
32 Self-Sap Channels and 256 Mutual Cap Channels
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
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ATmega324PB
Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Ten PWM Channels – 8-Channel 10-Bit ADC
Differential Mode with Selectable Gain at 1×, 10× or 200× – Three Programmable Serial USARTs – Two Master/Slave SPI Serial Interfaces – Two Byte-oriented 2-wire Serial Interfaces (Philips I2C Compatible) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change
Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal 8 MHz Calibrated Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended
Standby – Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failure – Individual Serial Number to Represent a Unique ID
I/O and Packages – 39 Programmable I/O Lines – 44-Pin TQFP and 44-Pin QFN /MLF
Operating Voltage: – 1.8 - 5.5V
Temperature Range: – -40°C to 105°C
Speed Grade: – 0 - 4MHz @ 1.8 - 5.5V – 0 - 10MHz @ 2.7 - 5.5.V – 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25°C – Active Mode: 0.24mA – Power-Down Mode: 0.2μA – Power-Save Mode: 1.3μA (Including 32kHz RTC)
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Table of Contents

Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description...............................................................................................................10
2. Configuration Summary........................................................................................... 11
3. Ordering Information ...............................................................................................12
4. Block Diagram......................................................................................................... 13
5. Pin Configurations................................................................................................... 14
5.1. Pin Descriptions......................................................................................................................... 14
6. I/O Multiplexing........................................................................................................16
7. General Information.................................................................................................18
7.1. Resources.................................................................................................................................. 18
7.2. About Code Examples................................................................................................................18
8. AVR CPU Core........................................................................................................ 19
8.1. Overview.................................................................................................................................... 19
8.2. ALU – Arithmetic Logic Unit....................................................................................................... 20
8.3. Status Register...........................................................................................................................20
8.4. General Purpose Register File...................................................................................................22
8.5. Stack Pointer..............................................................................................................................23
8.6. Accessing 16-bit Registers.........................................................................................................24
8.7. Instruction Execution Timing...................................................................................................... 24
8.8. Reset and Interrupt Handling..................................................................................................... 25
9. AVR Memories.........................................................................................................28
9.1. Overview.................................................................................................................................... 28
9.2. In-System Reprogrammable Flash Program Memory................................................................28
9.3. SRAM Data Memory.................................................................................................................. 29
9.4. EEPROM Data Memory............................................................................................................. 30
9.5. I/O Memory.................................................................................................................................31
9.6. Register Description...................................................................................................................32
10. System Clock and Clock Options............................................................................ 38
10.1. Clock Systems and Their Distribution........................................................................................ 38
10.2. Clock Sources............................................................................................................................ 39
10.3. Low Frequency Crystal Oscillator...............................................................................................41
10.4. Low Power Crystal Oscillator..................................................................................................... 42
10.5. Calibrated Internal RC Oscillator................................................................................................44
10.6. 128kHz Internal Oscillator.......................................................................................................... 45
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ATmega324PB
10.7. External Clock............................................................................................................................ 45
10.8. Timer/Counter Oscillator.............................................................................................................46
10.9. Clock Output Buffer....................................................................................................................47
10.10. System Clock Prescaler............................................................................................................. 47
10.11. Register Description...................................................................................................................47
11. CFD - Clock Failure Detection mechanism............................................................. 50
11.1. Overview.................................................................................................................................... 50
11.2. Features..................................................................................................................................... 50
11.3. Operations..................................................................................................................................50
11.4. Timing Diagram..........................................................................................................................52
11.5. Register Description...................................................................................................................52
12. PM - Power Management and Sleep Modes...........................................................53
12.1. Sleep Modes.............................................................................................................................. 53
12.2. BOD Disable...............................................................................................................................53
12.3. Idle Mode....................................................................................................................................54
12.4. ADC Noise Reduction Mode...................................................................................................... 54
12.5. Power-Down Mode.....................................................................................................................55
12.6. Power-Save Mode......................................................................................................................55
12.7. Standby Mode............................................................................................................................ 56
12.8. Extended Standby Mode............................................................................................................56
12.9. Power Reduction Registers........................................................................................................56
12.10. Minimizing Power Consumption.................................................................................................56
12.11. Register Description...................................................................................................................58
13. SCRST - System Control and Reset....................................................................... 63
13.1. Resetting the AVR...................................................................................................................... 63
13.2. Reset Sources............................................................................................................................63
13.3. Power-on Reset..........................................................................................................................64
13.4. External Reset............................................................................................................................65
13.5. Brown-out Detection...................................................................................................................65
13.6. Watchdog System Reset............................................................................................................66
13.7. Internal Voltage Reference.........................................................................................................66
13.8. Watchdog Timer......................................................................................................................... 67
13.9. Register Description...................................................................................................................69
14. INT- Interrupts..........................................................................................................73
14.1. Interrupt Vectors in ATmega324PB............................................................................................ 73
14.2. Register Description...................................................................................................................76
15. External Interrupts................................................................................................... 78
15.1. EXINT - External Interrupts........................................................................................................ 78
16. I/O-Ports.................................................................................................................. 86
16.1. Overview.................................................................................................................................... 86
16.2. Ports as General Digital I/O........................................................................................................87
16.3. Alternate Port Functions.............................................................................................................90
16.4. Register Description.................................................................................................................106
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ATmega324PB
17. TC0 - 8-bit Timer/Counter0 with PWM...................................................................114
17.1. Features................................................................................................................................... 114
17.2. Overview...................................................................................................................................114
17.3. Timer/Counter Clock Sources...................................................................................................116
17.4. Counter Unit............................................................................................................................. 116
17.5. Output Compare Unit................................................................................................................117
17.6. Compare Match Output Unit.....................................................................................................119
17.7. Modes of Operation..................................................................................................................120
17.8. Timer/Counter Timing Diagrams.............................................................................................. 124
17.9. Register Description.................................................................................................................126
18. TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM.................................................134
18.1. Features................................................................................................................................... 134
18.2. Overview.................................................................................................................................. 134
18.3. Accessing 16-bit Timer/Counter Registers...............................................................................135
18.4. Timer/Counter Clock Sources.................................................................................................. 138
18.5. Counter Unit............................................................................................................................. 138
18.6. Input Capture Unit.................................................................................................................... 139
18.7. Compare Match Output Unit.....................................................................................................141
18.8. Output Compare Units..............................................................................................................142
18.9. Modes of Operation..................................................................................................................144
18.10. Timer/Counter Timing Diagrams.............................................................................................. 151
18.11. Register Description.................................................................................................................153
19. Timer/Counter 0, 1, 3, 4 Prescalers.......................................................................179
19.1. Internal Clock Source...............................................................................................................179
19.2. Prescaler Reset........................................................................................................................179
19.3. External Clock Source..............................................................................................................179
19.4. Register Description.................................................................................................................180
20. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation...................182
20.1. Features................................................................................................................................... 182
20.2. Overview.................................................................................................................................. 182
20.3. Timer/Counter Clock Sources.................................................................................................. 184
20.4. Counter Unit............................................................................................................................. 184
20.5. Output Compare Unit............................................................................................................... 185
20.6. Compare Match Output Unit.....................................................................................................187
20.7. Modes of Operation..................................................................................................................188
20.8. Timer/Counter Timing Diagrams.............................................................................................. 192
20.9. Asynchronous Operation of Timer/Counter2............................................................................193
20.10. Timer/Counter Prescaler.......................................................................................................... 195
20.11. Register Description.................................................................................................................195
21. OCM - Output Compare Modulator....................................................................... 205
21.1. Overview.................................................................................................................................. 205
21.2. Description............................................................................................................................... 205
22. SPI – Serial Peripheral Interface........................................................................... 207
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ATmega324PB
22.1. Features................................................................................................................................... 207
22.2. Overview.................................................................................................................................. 207
22.3. SS Pin Functionality................................................................................................................. 211
22.4. Data Modes.............................................................................................................................. 211
22.5. Register Description.................................................................................................................212
23. USART - Universal Synchronous Asynchronous Receiver Transceiver................218
23.1. Features................................................................................................................................... 218
23.2. Overview.................................................................................................................................. 218
23.3. Block Diagram..........................................................................................................................218
23.4. Clock Generation......................................................................................................................219
23.5. Frame Formats.........................................................................................................................222
23.6. USART Initialization................................................................................................................. 223
23.7. Data Transmission – The USART Transmitter......................................................................... 224
23.8. Data Reception – The USART Receiver..................................................................................226
23.9. Asynchronous Data Reception.................................................................................................230
23.10. Multi-Processor Communication Mode.................................................................................... 234
23.11. Examples of Baud Rate Setting............................................................................................... 234
23.12. Register Description.................................................................................................................237
24. USARTSPI - USART in SPI Mode.........................................................................245
24.1. Features................................................................................................................................... 245
24.2. Overview.................................................................................................................................. 245
24.3. Clock Generation......................................................................................................................245
24.4. SPI Data Modes and Timing.....................................................................................................246
24.5. Frame Formats.........................................................................................................................246
24.6. Data Transfer............................................................................................................................248
24.7. AVR USART MSPIM vs. AVR SPI............................................................................................249
24.8. Register Description.................................................................................................................250
25. TWI - 2-wire Serial Interface..................................................................................251
25.1. Features................................................................................................................................... 251
25.2. Two-Wire Serial Interface Bus Definition..................................................................................251
25.3. Data Transfer and Frame Format.............................................................................................252
25.4. Multi-master Bus Systems, Arbitration, and Synchronization...................................................255
25.5. Overview of the TWI Module....................................................................................................256
25.6. Using the TWI...........................................................................................................................259
25.7. Transmission Modes................................................................................................................ 262
25.8. Multi-master Systems and Arbitration...................................................................................... 278
25.9. Register Description.................................................................................................................280
26. AC - Analog Comparator....................................................................................... 285
26.1. Overview.................................................................................................................................. 285
26.2. Analog Comparator Multiplexed Input......................................................................................285
26.3. Register Description.................................................................................................................286
27. ADC - Analog to Digital Converter.........................................................................289
27.1. Features................................................................................................................................... 289
27.2. Overview.................................................................................................................................. 289
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ATmega324PB
27.3. Starting a Conversion...............................................................................................................291
27.4. Prescaling and Conversion Timing...........................................................................................292
27.5. Changing Channel or Reference Selection..............................................................................295
27.6. ADC Noise Canceler................................................................................................................ 297
27.7. ADC Conversion Result........................................................................................................... 301
27.8. Register Description.................................................................................................................303
28. PTC - Peripheral Touch Controller.........................................................................309
28.1. Overview.................................................................................................................................. 309
28.2. Features................................................................................................................................... 309
28.3. Block Diagram..........................................................................................................................310
28.4. Signal Description.................................................................................................................... 310
28.5. System Dependencies............................................................................................................. 310
28.6. Functional Description..............................................................................................................312
29. JTAG Interface and On-chip Debug System......................................................... 313
29.1. Features................................................................................................................................... 313
29.2. Overview.................................................................................................................................. 313
29.3. TAP – Test Access Port............................................................................................................314
29.4. TAP Controller..........................................................................................................................315
29.5. Using the Boundary-scan Chain...............................................................................................316
29.6. Using the On-chip Debug System............................................................................................316
29.7. On-chip Debug Specific JTAG Instructions..............................................................................317
29.8. Using the JTAG Programming Capabilities..............................................................................317
29.9. Bibliography..............................................................................................................................318
29.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................318
29.11. Data Registers..........................................................................................................................319
29.12. Boundry-scan Specific JTAG Instructions................................................................................320
29.13. Boundary-scan Chain...............................................................................................................322
29.14. ATmega324PB Boundary-scan Order......................................................................................325
29.15. Boundary-scan Description Language Files............................................................................ 327
29.16. Register Description.................................................................................................................327
30. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................331
30.1. Features................................................................................................................................... 331
30.2. Overview.................................................................................................................................. 331
30.3. Application and Boot Loader Flash Sections............................................................................331
30.4. Read-While-Write and No Read-While-Write Flash Sections...................................................332
30.5. Entering the Boot Loader Program...........................................................................................334
30.6. Boot Loader Lock Bits.............................................................................................................. 335
30.7. Addressing the Flash During Self-Programming...................................................................... 336
30.8. Self-Programming the Flash.....................................................................................................337
30.9. Register Description.................................................................................................................345
31. MEMPROG- Memory Programming......................................................................347
31.1. Program And Data Memory Lock Bits......................................................................................347
31.2. Fuse Bits.................................................................................................................................. 348
31.3. Signature Bytes........................................................................................................................350
31.4. Calibration Byte........................................................................................................................350
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ATmega324PB
31.5. Serial Number.......................................................................................................................... 351
31.6. Page Size.................................................................................................................................353
31.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................354
31.8. Parallel Programming...............................................................................................................356
31.9. Serial Downloading.................................................................................................................. 363
31.10. Programming Via the JTAG Interface...................................................................................... 368
32. Electrical Characteristics....................................................................................... 383
32.1. Absolute Maximum Ratings......................................................................................................383
32.2. DC Characteristics................................................................................................................... 383
32.3. Speed Grades.......................................................................................................................... 385
32.4. Clock Characteristics................................................................................................................386
32.5. System and Reset Characteristics........................................................................................... 387
32.6. SPI Timing Characteristics.......................................................................................................388
32.7. Two-wire Serial Interface Characteristics.................................................................................389
32.8. ADC Characteristics.................................................................................................................391
32.9. Parallel Programming Characteristics...................................................................................... 394
33. Typical Characteristics...........................................................................................397
33.1. Active Supply Current...............................................................................................................397
33.2. Idle Supply Current...................................................................................................................401
33.3. Supply Current of IO Modules .................................................................................................403
33.4. Power-down Supply Current.................................................................................................... 404
33.5. Pin Pull-Up............................................................................................................................... 406
33.6. Pin Driver Strength...................................................................................................................409
33.7. Pin Threshold and Hysteresis...................................................................................................411
33.8. BOD Threshold.........................................................................................................................414
33.9. Analog Comparator Offset........................................................................................................417
33.10. Internal Oscillator Speed..........................................................................................................418
33.11. Current Consumption of Peripheral Units.................................................................................421
33.12. Current Consumption in Reset and Reset Pulse Width........................................................... 424
34. Register Summary.................................................................................................426
35. Instruction Set Summary....................................................................................... 431
36. Packaging Information...........................................................................................435
36.1. 44-pin TQFP.............................................................................................................................435
36.2. 44-pin VQFN............................................................................................................................ 436
37. Errata.....................................................................................................................437
37.1. Rev.A-H.................................................................................................................................... 437
37.2. Rev. I........................................................................................................................................ 437
37.3. Rev. J - K..................................................................................................................................437
38. Datasheet Revision History................................................................................... 438
The Microchip Web Site.............................................................................................. 440
Customer Change Notification Service........................................................................440
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ATmega324PB
Customer Support....................................................................................................... 440
Microchip Devices Code Protection Feature............................................................... 440
Legal Notice.................................................................................................................441
Trademarks................................................................................................................. 441
Quality Management System Certified by DNV...........................................................442
Worldwide Sales and Service......................................................................................443
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1. Description

The ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power consumption versus processing speed.
The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega324PB provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1Kbytes EEPROM, 2Kbytes SRAM, 39 general purpose I/O lines, 32 general purpose working registers, five flexible Timer/Counters with compare modes, internal and external interrupts, three serial programmable USART, two byte-oriented 2-wire Serial Interface (I2C), two SPI serial port, a 8-channel 10-bit ADC with optional differential input stage with programmable gain, a programmable Watchdog Timer with internal Oscillator, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, Clock failure detection mechanism and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. PTC with enabling up to 32 self-cap and 256 mutual-cap sensors. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. Also ability to run PTC in power-save mode/ wake-up on touch and Dynamic on/off of PTC analog and digital portion. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, PTC, and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.
ATmega324PB
The device is manufactured using high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the ATmega324PB is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega324PB is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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DS40001908A-page 10

2. Configuration Summary

Features ATmega324PB
Pin count 44
Flash (KB) 32
SRAM (KB) 2
EEPROM (KB) 1
General Purpose I/O lines 39
SPI 2
TWI (I2C) 2
USART 3
ADC 10-bit 15ksps
Differential ADC mode Available
ADC channels 8
ATmega324PB
AC 1
8-bit Timer/Counters 2
16-bit Timer/Counters 3
PWM channels 10
PTC Available
Peripheral Touch Controller (PTC) channels (X- x Y-Lines) for mutual capacitance 256 (16 x 16)
Peripheral Touch Controller (PTC) channels for self capacitance (Y-Lines only) 32
Clock Failure Detector (CFD) Available
Output Compare Modulator (OCM1C2) Available
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3. Ordering Information

ATmega324PB
Speed [MHz] Power Supply [V] Ordering Code
20 1.8 - 5.5
ATmega324PB-AU ATmega324PB-AUR ATmega324PB-MU ATmega324PB-MUR
ATmega324PB-AN ATmega324PB-ANR ATmega324PB-MN ATmega324PB-MNR
Note: 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. Tape & Reel.
(2)
(3)
(3)
(3)
(3)
Package
44A 44A 44M1 44M1
44A 44A 44M1 44M1
(1)
Operational Range
Industrial (-40°C to 85°C)
Industrial (-40°C to 105°C)
Package Type
44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
44M1 44-pad, 7 x 7 x 0.9mm body, Lead Pitch 0.50mm, Very-thin Fine pitch, Quad Flat No Lead Package/Quad
Flat No-Lead/Micro Lead Frame Package (VQFN/QFN/MLF)
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4. Block Diagram

CPU
USART 0
ADC
ADC[7:0]
AREF
RxD0 TxD0 XCK0
I/O
PORTS
D A T A B U S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
JTAG
I
N
/ O U T
D A T A B U S
TC 0
(8-bit)
SPI 0
AC
AIN0 AIN1 ACO ADCMUX
EEPROM
EEPROMIF
PTC
X[15:0] Y[31:0]
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 3
(16-bit)
TC 4
(16-bit)
OC3A/B
T3
ICP3
OC4A/B
T4
ICP4
TC 2
(8-bit async)
TWI 0
TWI 1
SDA0 SCL0
SDA1 SCL1
USART 1
USART 2
RxD1 TxD1 XCK1
RxD2 TxD2 XCK2
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz XOSC
External
clock
Power Supervision POR/BOD &
RESET
TOSC2
XTAL2
RESET
XTAL1
TOSC1
16MHz LP
XOSC
TCK TMS
TDI
TDO
Crystal failure detection
PCINT[38:0]
INT[2:0]
T0 OC0A OC0B
MISO0 MOSI0 SCK0 SS0
OC2A OC2B
PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE[6:0]
SPI 1
MISO1 MOSI1 SCK1 SS1
Figure 4-1. Block Diagram
ATmega324PB
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DS40001908A-page 13

5. Pin Configurations

Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
1
2
3
4
43
42
41
40
39
38
37
5
6
7
8
35
3422
21
20
19
18
17
36
9
10
11
12
13
14
15
16
AVCC
RESET

GND

VCC

(XTAL1) PE1
(XTAL2) PE0
PC7 (TOSC2)
PE4 (AREF)
GND
PB0 (PTCY/T0/XCK0)
PB1 (PTCY/T1/CLKO)
PB2 (AIN0/PTCY/INT2)
(MOSI0/ICP3/PTCY) PB5
(MISO0/OC3A/PTCY) PB6
44
32
31
30
29
28
27
26
24
23
25
33
(SCK0/OC3B/OC4B/PTCY) PB7
PB3 (AIN1/PTCY/OC0A)
PB4 (PTCY/OC0B/SS0)
PE5 (SDA1)
PE6 (SCL1)
PA0 (ADC0/PTCY)
PA1 (ADC1/PTCY)
PA2 (ADC2/PTCY)
PA3 (ADC3/PTCY)
PA4 (ADC4/PTCY)
PA5 (ADC5/PTCY)
PA6 (ADC6/PTCY)
PA7 (ADC7/PTCY)
PC6 (TOSC1)
PC4 (PTCXY/OC4A/TDO)
PC5 (PTCXY/ACO/TDI)
(TMS/ICP4/PTCXY) PC3
(TCK/T4/PTCXY) PC2
(SDA0/PTCXY) PC1
(SCL0/PTCXY) PC0
(MOSI1/TXD2/PTCXY) PE3
(MISO1/RXD2/PTCXY) PE2
(SS1/ICP1/OC2B/PTCXY) PD6
(OC1A/PTCXY) PD5
(XCK1/OC1B/PTCXY) PD4
(TXD1/INT1/PTCXY) PD3
(RXD1/INT0/PTCXY) PD2
(TXD0/PTCXY) PD1
(RXD0/T3/PTCXY) PD0
Figure 5-1. Pinout ATmega324PB
ATmega324PB

5.1 Pin Descriptions

5.1.1 VCC
Digital supply voltage.
5.1.2 GND
Ground.
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DS40001908A-page 14

5.1.3 Port A (PA[7:0])

This port serves as analog inputs to the Analog-to-digital Converter.
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated during a reset condition, even if the clock is not running.

5.1.4 Port B (PB[7:0])

This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated during a reset condition, even if the clock is not running.
This port also serves the functions of various special features.

5.1.5 Port C (PC[7:0])

This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated during a reset condition, even if the clock is not running.
ATmega324PB
This port also serves the functions of the JTAG interface, along with special features.

5.1.6 Port D (PD[7:0])

This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated during a reset condition, even if the clock is not running.
This port also serves the functions of various special features.

5.1.7 Port E (PE6:0) XTAL1/XTAL2/AREF

This is a 7-bit bi-directional GPIO port with internal pull-up resistors (selected for each pin). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. Port pins are tri-stated during a reset condition, even if the clock is not running. PE0 and PE1 are multiplexed with XTAL1 and XTAL2 input. PE4 is multiplexed with AREF for the A/D Converter.

5.1.8 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

5.1.9 AVCC

AVCC is the supply voltage pin for Port A, PE4 (AREF) and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
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6. I/O Multiplexing

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
No. PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
1 PB[5] PCINT13 Y29 ICP3 MOSI0
2 PB[6] PCINT14 Y30 OC3A MISO0
3 PB[7] PCINT15 Y31 OC3B OC4B SCK0
4 RESET
5 VCC
6 GND
7 PE[0] PCINT32 XTAL2
8 PE[1] PCINT33 XTAL1
9 PD[0] PCINT24 X0 Y8 T3 RxD0
10 PD[1] PCINT25 X1 Y9 TxD0
11 PD[2] INT0 PCINT26 X2 Y10 RxD1
12 PD[3] INT1 PCINT27 X3 Y11 TXD1
13 PD[4] PCINT28 X4 Y12 OC1B XCK1
14 PD[5] PCINT29 X5 Y13 OC1A
15 PD[6] PCINT30 X6 Y14 OC2B ICP1 SS1
16 PD[7] PCINT31 X7 Y15 OC2A XCK2 SCK1
17 PE[2] X8 Y16 RxD2 MISO1
18 PE[3] X9 Y17 TxD2 MOSI1
19 PC[0] PCINT16 X10 Y18 SCL0
20 PC[1] PCINT17 X11 Y19 SDA0
21 PC[2] PCINT18 X12 Y20 T4 TCK
22 PC[3] PCINT19 X13 Y21 ICP4 TMS
23 PC[4] PCINT20 X14 Y22 OC4A TDO
24 PC[5] PCINT21 ACO X15 Y23 TDI
25 PC[6] PCINT22 TOSC1
26 PC[7] PCINT23 TOSC2
27 AVCC
28 GND
29 PE[4] AREF
30 PA[7] PCINT7 ADC7 Y7
31 PA[6] PCINT6 ADC6 Y6
32 PA[5] PCINT5 ADC5 Y5
33 PA[4] PCINT4 ADC4 Y4
34 PA[3] PCINT3 ADC3 Y3
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No. PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
35 PA[2] PCINT2 ADC2 Y2
36 PA[1] PCINT1 ADC1 Y1
37 PA[0] PCINT0 ADC0 Y0
38 PE[5] SDA1
39 PE[6] SCL1
40 PB[0] PCINT8 Y24 T0 XCK0
41 PB[1] PCINT9 Y25 CLKO T1
42 PB[2] INT2 PCINT10 AIN0 Y26
43 PB[3] PCINT11 AIN1 Y27 OC0A
44 PB[4] PCINT12 Y28 OC0B SS0
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7. General Information

7.1 Resources

A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.

7.2 About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confer with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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8. AVR CPU Core

Register file
Flash program
memory
Program
counter
Instruction
register
Instruction
decode
Data memory
ALU
Status
register
R0R1
R2R3
R4R5
R6R7
R8R9
R10R11
R12R13
R14R15
R16R17
R18R19
R20R21
R22R23
R24R25
R26 (XL)R27 (XH)
R28 (YL)R29 (YH)
R30 (ZL)R31 (ZH)
Stack
pointer

8.1 Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
Figure 8-1. Block Diagram of the AVR Architecture
ATmega324PB
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
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The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

8.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction Set Summary section for a detailed description.
Related Links
Instruction Set Summary

8.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
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8.3.1 Status Register

When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  SREG Offset:  0x5F Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x3F
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
I T H S V N Z C
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
Bit 6 – T: Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in BCD arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S: Sign Flag, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the Instruction Set Description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction Set Description for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information.
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Bit 0 – C: Carry Flag
15
XH
XL
0
X-register
707
0
R27
R26
15
YH
YL
0
Y-register
707
0
R29
R28
15
ZH
ZL
0
Z-register
707
0
R31
R30
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information.

8.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 8-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in the figure, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
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8.4.1 The X-register, Y-register, and Z-register

The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in the figure.
Figure 8-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary
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8.5 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM. See the table for Stack Pointer details.
Table 8-1. Stack Pointer Instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
ATmega324PB
CALL
ICALL
RCALL
POP Incremented by 1 Data is popped from the stack
RET
RETI
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

8.5.1 Stack Pointer Register Low and High byte

The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
Incremented by 2 Return address is popped from the stack with return from subroutine or
return from interrupt
Name:  SPL and SPH Offset:  0x5D Reset:  0x8FF Property: When addressing I/O Registers as data space the offset address is 0x3D
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Bit 15 14 13 12 11 10 9 8
Access
Reset 0 0 0 0 1 0 0 0
Bit 7 6 5 4 3 2 1 0
Access
Reset 1 1 1 1 1 1 1 1
R R R R RW RW RW RW
RW RW RW RW RW RW RW RW
SP[7:0]
Bits 11:0 – SP[11:0]: Stack Pointer Register
SPL and SPH are combined into SP.

8.6 Accessing 16-bit Registers

The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
SP[11:8]
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.

8.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk clock division is used. The Figure below shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
, directly generated from the selected clock source for the chip. No internal
CPU
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clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
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Figure 8-4. The Parallel Instruction Fetches and Instruction Executions
The following figure shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
Figure 8-5. Single Cycle ALU Operation

8.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. They have determined priority levels: The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and
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hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
The Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit)
(1)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */
(1)
1. Refer to About Code Examples.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
(1)
(1)
1. Refer to About Code Examples.
Related Links
Memory Programming Boot Loader Support – Read-While-Write Self-Programming About Code Examples
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8.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
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9. AVR Memories

0x0000
0x3FFF
Program Memory
Application Flash Section
Boot Flash Section

9.1 Overview

This section describes the different memory types in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All memory spaces are linear and regular.

9.2 In-System Reprogrammable Flash Program Memory

The ATmega324PB contains 32K bytes on-chip in-system reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32K x 16. For software security, the Flash Program memory space is divided into two sections - Boot Loader Section and Application Program Section in the device .
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega324PB Program Counter (PC) is 15 bits wide, thus addressing the 32K program memory locations. The operation of the Boot Program section and associated Boot Lock bits for software protection are described in detail in Boot Loader Support – Read-While-Write Self-Programming. Refer to Memory Programming for the description on Flash data serial downloading using the SPI pins or the JTAG interface.
ATmega324PB
Constant tables can be allocated within the entire program memory address space, using the Load Program Memory (LPM) instruction.
Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.
Figure 9-1. Program Memory Map ATmega324PB
Related Links
BTLDR - Boot Loader Support – Read-While-Write Self-Programming MEMPROG- Memory Programming Instruction Execution Timing
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9.3 SRAM Data Memory

(2048x8)
0x08FF
The following figure shows how the device SRAM Memory is organized.
The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60
- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 4352 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096 locations address the internal data SRAM.
The five different addressing modes for the data memory cover:
Direct – The direct addressing reaches the entire data space.
Indirect with Displacement – The Indirect with Displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.
Indirect – In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
Indirect with Pre-decrement – The address registers X, Y, and Z are decremented.
Indirect with Post-increment – The address registers X, Y, and Z are incremented.
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The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2K bytes of internal data SRAM in the device are all accessible through all these addressing modes.
Figure 9-2. Data Memory Map with 2048 byte internal data SRAM

9.3.1 Data Memory Access Times

The internal data SRAM access is performed in two clk
cycles as described in the following Figure.
CPU
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Figure 9-3. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
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9.4 EEPROM Data Memory

The ATmega324PB contains 1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address registers, the EEPROM Data register, and the EEPROM Control register.
See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programming mode.
Related Links
MEMPROG- Memory Programming

9.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 9-2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. Please refer to Preventing EEPROM Corruption for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
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9.4.2 Preventing EEPROM Corruption

During periods of low V the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
the EEPROM data can be corrupted because the supply voltage is too low for
CC,

9.5 I/O Memory

The I/O space definition of the device is shown in the Register Summary.
All device I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00-0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
ATmega324PB
When using the I/O specific commands IN and OUT, the I/O addresses 0x00-0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60..0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a '1' to them; this is described in the flag descriptions. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00-0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
Related Links
MEMPROG- Memory Programming
Instruction Set Summary

9.5.1 General Purpose I/O Registers

The device contains three General Purpose I/O Registers, General Purpose I/O Register 0/1/2 (GPIOR 0/1/2). These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
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9.6 Register Description

9.6.1 Accessing 16-bit Registers

The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers.
ATmega324PB
The temporary registers can also be read and written directly from user software.

9.6.2 EEPROM Address Register Low and High Byte

The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  EEARL and EEARH Offset:  0x41 [ID-000004d0] Reset:  0xXX Property: When addressing as I/O Register: address offset is 0x21
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ATmega324PB
Bit 15 14 13 12 11 10 9 8
Access
Reset x x x x
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x

9.6.3 EEPROM Data Register

EEAR[11:8]
R/W R/W R/W R/W
EEAR[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 11:0 – EEAR[11:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1K Bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  EEDR Offset:  0x40 [ID-000004d0] Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x20
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
EEDR[7:0]
Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

9.6.4 EEPROM Control Register

Name:  EECR Offset:  0x3F [ID-000004d0] Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x1F
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ATmega324PB
Bit 7 6 5 4 3 2 1 0
Access
Reset x x 0 0 x 0
EEPM[1:0] EERIE EEMPE EEPE EERE
R/W R/W R/W R/W R/W R/W
Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations into two different operations. The Programming times for the different modes are shown in the table below. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
Table 9-1. EEPROM Mode Bits
EEPM[1:0] Programming Time Operation
00 3.4ms Erase and Write in one operation (Atomic Operation)
01 1.8ms Erase Only
10 1.8ms Write Only
11 - Reserved for future use
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.
Bit 2 – EEMPE: EEPROM Master Write Enable
The EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written. When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selected address.
If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
Bit 1 – EEPE: EEPROM Write Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bit must be written to '1' before EEPE is written to '1', otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEPE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a '1' to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only
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ATmega324PB
relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted.
Caution: 
An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a '1' to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. See the following table for typical programming times for EEPROM access from the CPU.
Table 9-2. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles Typ. Programming Time
EEPROM write (from CPU) 26,368 3.3ms
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
Assembly Code Example
EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret
(1)
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
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(1)
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ATmega324PB
/* Wait for completion of previous write */ while(EECR & (1<<EEPE)) ; /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); }
Note:  (1) Please refer to About Code Examples
The following code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
Assembly Code Example
EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret
(1)
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{ /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) ; /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; }
(1)
1. Refer to About Code Examples.

9.6.5 GPIOR2 – General Purpose I/O Register 2

When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  GPIOR2 Offset:  0x4B [ID-000004d0] Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x2B
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ATmega324PB
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7:0 – GPIOR2[7:0]: General Purpose I/O

9.6.6 GPIOR1 – General Purpose I/O Register 1

When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  GPIOR1 Offset:  0x4A [ID-000004d0] Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x2A
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
GPIOR2[7:0]
GPIOR1[7:0]
Bits 7:0 – GPIOR1[7:0]: General Purpose I/O

9.6.7 GPIOR0 – General Purpose I/O Register 0

When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  GPIOR0 Offset:  0x3E [ID-000004d0] Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x1E
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
GPIOR0[7:0]
Bits 7:0 – GPIOR0[7:0]: General Purpose I/O
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10. System Clock and Clock Options

Asynchronous
Timer/Counter
ADC AVR CPU
Flash and EEPROM
Watchdog
Timer
System Clock
Prescaler
Clock
Multiplexer
Timer/Counter
Oscillator
Watchdog Oscillator
Calibrated Internal
RC OSC
External Clock
Crystal
Oscillator
XTAL1
XTAL2
clk
ASY
clk
CPU
Low-frequency
Crystal Oscillator
Reset Logic
AVR Clock
Control Unit
General I/O
Modules
RAM
clk
IO
clk
FLASH
clk
ADC
Watchdog clock
TOSC1
TOSC2
clk
SYS
Peripheral Touch
Controller
clk
PTC

10.1 Clock Systems and Their Distribution

The following figure illustrates the principal clock systems in the device and their distribution. All the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes. The clock systems are described in the following sections.
The system clock frequency refers to the frequency generated from the System Clock Prescaler. All clock outputs from the AVR Clock Control Unit runs in the same frequency.
Figure 10-1. Clock Distribution
ATmega324PB
10.1.1 CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
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ATmega324PB
10.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but the start condition detection in the USI module is carried out asynchronously when clk
Note:  If a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses.
10.1.3 PTC Clock - clk
PTC
The PTC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise and power due to digital circuitry.
10.1.4 Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.
10.1.5 Asynchronous Timer Clock – clk
The Asynchronous Timer clock allows Asynchronous Timer/Counters to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/ Counter as a real-time counter even when the device is in sleep mode.
is halted, TWI address recognition in all sleep modes.
I/O
ASY
10.1.6 ADC Clock – clk
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

10.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 10-1. Device Clocking Options Select
Device Clocking Option CKSEL[3:0]
Low Power Crystal Oscillator 1111 - 1000
Low Frequency Crystal Oscillator 0101 - 0100
Internal 128kHz RC Oscillator 0011
Calibrated Internal RC Oscillator 0010
External Clock 0000
Reserved 0001
ADC
Note:  For all fuses, '1' means unprogrammed while '0' means programmed.

10.2.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The start-up time is set to maximum, and the time-out period is
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enabled: CKSEL=0010, SUT=10, CKDIV8=0. This default setting ensures that all users can make their desired clock source setting using any available programming interface.

10.2.2 Clock Start-up Sequence

Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable.
ATmega324PB
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (t
) after the device
TOUT
reset is released by all other reset sources. See the Related Links for a description of the start conditions for the internal reset. The delay (t
) is timed from the Watchdog Oscillator and the number of cycles in
TOUT
the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in the Table below. The frequency of the Watchdog Oscillator is voltage dependent.
Table 10-2. Number of Watchdog Oscillator Cycles
Typ. Time-out (VCC = 5.0V) Typ. Time-out (VCC = 3.0V)
0ms 0ms
4ms 4.3ms
65ms 69ms
Main purpose of the delay is to keep the device in reset until it is supplied with minimum VCC. The delay will not monitor the actual voltage, so it is required to select a delay longer than the VCC rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, VCC is assumed to be at a sufficient level and only the start-up time is included.

10.2.3 Clock Source Connections

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in the Figure below. Either a quartz crystal or a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in the next Table. For ceramic resonators, the capacitor values given by the manufacturer should be used.
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Figure 10-2. Crystal Oscillator Connections
XTAL2
XTAL1
GND
C2
C1

10.3 Low Frequency Crystal Oscillator

The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into consideration. Both values are specified by the crystal vendor. The oscillator is optimized for very low power consumption, and thus when selecting crystals, consider the Maximum ESR Recommendations:
Table 10-3. Maximum ESR Recommendation for 32.768kHz Crystal
Crystal CL [pF] Max. ESR [kΩ]
ATmega324PB
9.0 65
12.5 30
The Low-frequency Crystal Oscillator provides an internal load capacitance at each TOSC pin:
Table 10-4. Internal capacitance of Low-Frequency Oscillator
32kHz Osc. Type Internal Pad Capacitance
(XTAL1/TOSC1)
Ci of system oscillator (XTAL pins) 6pF 6pF
Ci of timer oscillator (TOSC pins) 4pF 4pF
The capacitance (Ce+Ci) needed at each XTAL/TOSC pin can be calculated by using:
+ = 2 
where:
Ce - is optional external capacitors. (=C1, C2 as shown in Figure 10-2)
Ci - is the pin capacitance in Table 10-4.
CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor.
CS - is the total stray capacitance for one TOSC pin.
Crystals specifying a load capacitance (CL) higher than 6pF require external capacitors applied according to above formula.
Internal Pad Capacitance (XTAL2/TOSC2)
When this oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in the following table.
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ATmega324PB
Table 10-5. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
Power Conditions Start-up Time from
Power-down and Power-
Additional Delay from Reset (VCC = 5.0V)
CKSEL[0] SUT[1:0]
save
BOD enabled 1K CK 14CK
Fast rising power 1K CK 14CK + 4ms
Slowly rising power 1K CK 14CK + 65ms
(1)
(1)
(1)
0 00
0 01
0 10
Reserved 0 11
BOD enabled 32K CK 14CK 1 00
Fast rising power 32K CK 14CK + 4ms 1 01
Slowly rising power 32K CK 14CK + 65ms 1 10
Reserved 1 11
Note: 
1. This option should only be used if frequency stability at start-up is not important for the application.
Related Links
Clock Source Connections

10.4 Low Power Crystal Oscillator

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments.
The crystal should be connected as described in Clock Source Connections. When selecting crystals, load capacitance must be taken into consideration. The capacitance (Ce+Ci) needed at each TOSC pin can be calculated by using:
+ = 2 
where:
Ce - is optional external capacitors. (= C1, C2 as shown in Figure 10-2)
Ci - is the pin capacitance in Table 10-6.
CL - is the load capacitance specified by the crystal vendor.
CS - is the total stray capacitance for one XTAL pin.
Table 10-6. Internal capacitance of Low-Power Oscillator
32kHz Osc. Type Internal Pad Capacitance
Ci of system oscillator (XTAL pins) 6pF 6pF
The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL[3:1], as shown in the following table:
(XTAL1)
Internal Pad Capacitance (XTAL2)
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Table 10-7. Low Power Crystal Oscillator Operating Modes
Frequency Range
CKSEL[3:1]
(2)
Range for total capacitance of C1 and C2 [pF]
[MHz]
0.4 - 0.9 100
(3)
0.9 - 3.0 101 12 - 22
3.0 - 8.0 110 12 - 22
8.0 - 16.0 111 12 - 22
Note: 
1. If the crystal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse
can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.
2. This is the recommended CKSEL settings for the difference frequency ranges.
3. This option should not be used with crystals, only with ceramic resonators.
4. The range of the
capacitance should not be larger than the value given in this table.
The CKSEL0 Fuse together with the SUT[1:0] Fuses select the start-up times, as shown in the following table:
(1)
(4)
Table 10-8. Start-up Times for the Low Power Crystal Oscillator Clock Selection
Oscillator Source / Power Conditions
Ceramic resonator, fast rising power 258 CK 14CK + 4ms
Ceramic resonator, slowly rising
Start-up Time from Power-down and Power-save
Additional Delay from Reset (VCC = 5.0V)
258 CK 14CK + 65ms
(1)
(1)
CKSEL0 SUT[1:0]
0 00
0 01
power
Ceramic resonator, BOD enabled 1K CK 14CK
Ceramic resonator, fast rising power 1K CK 14CK + 4ms
Ceramic resonator, slowly rising
1K CK 14CK + 65ms
(2)
(2)
(2)
0 10
0 11
1 00
power
Crystal Oscillator, BOD enabled 16K CK 14CK 1 01
Crystal Oscillator, fast rising power 16K CK 14CK + 4ms 1 10
Crystal Oscillator, slowly rising power 16K CK 14CK + 65ms 1 11
Note: 
1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at
start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
Related Links
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Clock Source Connections

10.5 Calibrated Internal RC Oscillator

By default, the internal RC oscillator provides an 8.0MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 fuse programmed.
This clock may be selected as the system clock by programming the CKSEL fuses as shown in the following table. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL register and thereby automatically calibrates the RC Oscillator.
By changing the OSCCAL register from SW, it is possible to get a higher calibration accuracy than by using the factory calibration.
When this oscillator is used as the chip clock, the Watchdog oscillator will still be used for the Watchdog Timer and for the reset time-out.
Table 10-9. Internal Calibrated RC Oscillator Operating Modes
ATmega324PB
Frequency Range
7.3 - 8.1 0010
(1)
[MHz] CKSEL[3:0]
(2)
Note: 
1. If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 fuse can
be programmed in order to divide the internal frequency by 8.
2. The device is shipped with this option selected.
When this oscillator is selected, start-up times are determined by the SUT fuses:
Table 10-10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection - SUT
Power Conditions Start-up Time from Power-down and
Additional Delay from Reset (VCC = 5V) SUT[1:0]
Power-save
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4ms 01
Slow rising power 6 CK 14CK + 65ms 10
Reserved 11
Note: 
1. The device is shipped with this option selected.
(1)
Related Links
Clock Characteristics
System Clock Prescaler
Calibration Byte
OSCCAL
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10.6 128kHz Internal Oscillator

The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. This clock may be select as the system clock by programming the CKSEL Fuses to '0011':
Table 10-11. 128kHz Internal Oscillator Operating Modes
ATmega324PB
Nominal Frequency
128kHz 0011
Note: 
1. The 128kHz oscillator is a very low power clock source, and is not designed for high accuracy.
When this clock source is selected, start-up times are determined by the SUT Fuses:
Table 10-12. Start-Up Times for the 128kHz Internal Oscillator
Power Conditions Start-Up Time from Power-down and Power-
save
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4ms 01
Slowly rising power 6 CK 14CK + 65ms 10
Reserved 11
(1)
CKSEL[3:0]
Additional Delay from Reset SUT[1:0]

10.7 External Clock

To drive the device from an external clock source, EXTCLK should be driven as shown in the Figure below. To run the device on an external clock, the CKSEL Fuses must be programmed to '0000':
Table 10-13. External Clock Frequency
Frequency
0 - 20MHz 0000
Note: 
1. If the cryatal frequency exceeds the specification of the device (depends on VCC), the CKDIV8
(1)
Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.
CKSEL[3:0]
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Figure 10-3. External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
EXTCLK
GND
When this clock source is selected, start-up times are determined by the SUT Fuses:
Table 10-14. Start-Up Times for the External Clock Selection - SUT
ATmega324PB
Power Conditions Start-Up Time from Power-down
and Power-save
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4ms 01
Slowly rising power 6 CK 14CK + 65ms 10
Reserved 11
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation.
Related Links
System Clock Prescaler
Additional Delay from Reset (VCC =
5.0V)

10.8 Timer/Counter Oscillator

The device uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See Low Frequency Crystal Oscillator for details on the oscillator and crystal requirements.
SUT[1:0]
On this device, the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if the Enable External Clock Input bit in the Asynchronous Status Register (ASSR.EXCLK) is written to '1'. See the description of the Asynchronous Operation of Timer/Counter2 for further description on selecting external clock as input instead of a
32.768kHz watch crystal.
Related Links
Low Frequency Crystal Oscillator
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OCR2B
ASSR

10.9 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.

10.10 System Clock Prescaler

The device has a system clock prescaler, and the system clock can be divided by configuring the Clock Prescale Register (CLKPR). This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk clk
, clk
ADC
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the Clock Prescaler Selection bits (CLKPS[3:0]) values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
CPU
, and clk
are divided by a factor as shown in the CLKPR description.
FLASH
ATmega324PB
,
I/O
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to '1' and all other bits in CLKPR to zero:
CLKPR=0x80.
2. Within four cycles, write the desired value to CLKPS[3:0] while writing a zero to CLKPCE:
CLKPR=0x0N
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
Related Links
CLKPR

10.11 Register Description

10.11.1 Oscillator Calibration Register

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ATmega324PB
Name:  OSCCAL Offset:  0x66 Reset:  Device Specific Calibration Value Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7:0 – CAL [7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in the Clock Characteristics section of Electrical Characteristics chapter.. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in the Clock Characteristics section of Electrical Characteristics chapter.. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.
CAL [7:0]
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL=0x7F gives a higher frequency than OSCCAL=0x80.
The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range.

10.11.2 Clock Prescaler Register

Name:  CLKPR Offset:  0x61 Reset:  Refer to the bit description Property: -
Bit 7 6 5 4 3 2 1 0
CLKPCE CLKPS [3:0]
Access
Reset 0 x x x x
R/W R/W R/W R/W R/W
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.
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ATmega324PB
Bits 3:0 – CLKPS [3:0]: Clock Prescaler Select
These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the table below.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Table 10-15. Clock Prescaler Select
CLKPS[3:0] Clock Division Factor
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1000 256
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
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11. CFD - Clock Failure Detection mechanism

11.1 Overview

The Clock Failure Detection mechanism for the device is enabled by CFD fuse in the Extended Fuse Byte. CFD operates with 128kHz internal oscillator which will be enabled automatically when CFD is enabled.

11.2 Features

Detection for the failure of the low power crystal oscillator and external clocks
Operate with 128kHz internal oscillator
Switch the clock to internal RC oscillator clock when clock failure happens
Failure Detection Interrupt Flag (XFDIF) available for the status of CFD

11.3 Operations

The Clock Failure Detector (CFD) allows the user to monitor the low power crystal oscillator or external clock signal. CFD monitors XOSC clock and if it fails it will automatically switch to a safe clock. When operating on safe clock the device will switch back to XOSC clock after Power-On or External Reset, and continue monitoring XOSC clock for failures. The safe clock is derived from the 8MHz internal RC system clock. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller.
ATmega324PB
Because the XOSC failure is monitored by the CFD circuit operating with the internal 128kHz oscillator, the current consumption of the 128kHz oscillator will be added into the total power consumption of the chip when CFD is enabled. CFD should be enabled only if the system clock (XOSC) frequency is above 256kHz.
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Figure 11-1. System Clock Generation with CFD Mechanism
Clock Failure Detection
circuit
Low Power Crystal Oscillator
128kHz Internal Oscillator
Calibrated Internal RC Oscillator
External Clock
System
clock
XOSC CKSEL
Calibrated RC Oscillator
(CKSEL: 4'b 0010)
XOSC Failed
CKSEL
WDT 128kHz CLK
XOSC
(External CLK/
ATmega324PB
Clock Failure Detection
To start the CFD operation, the user must write a one to the CFD fuse bit in the Extended Fuse Byte (EFB.CFD). After the start or restart of the XOSC, the CFD does not detect failure until the start-up time is elapsed. Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored.
If the external clock is not provided, the device will automatically switch to calibrated RC oscillator output.
When the failure is detected, the failure status is asserted, i.e Failure Detection Interrupt Flag bit in the XOSC Failure Detection Control And Status Register (XFDCSR.XFDIF) is set. The Failure Detection interrupt flag is generated, when the Interrupt Enable bit in the XOSC Failure Detection Control And Status Register (XFDCSR.XFDIE) is set. The XFDCSR.XFDIF reflects the current XOSC clock activity.
The detection will be automatically disabled when chip goes to power save/down sleep mode and enabled by itself when chip enters back to active mode.
Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an active clock. The safe clock source is the calibrated RC oscillator clock (CKSEL: 4’b0010). The clock source can be downscaled with a configurable prescaler to ensure that the clock frequency does not exceed the operating conditions selected by the application after switching. To use to original clock source, user must provide a reset. When using CFD and clock failure has occurred the system operates using 1MHz internal fallback clock. The system will try to resume to original clock source either via Power-On-Reset (POR) or via external RESET.
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11.4 Timing Diagram

RC clock
Ext clock
Sys clock
Xosc failed
Delayed xosc failed
The RC clock is enabled only after failure detection.
Figure 11-2. CFD mechanism timing diagram
ATmega324PB

11.5 Register Description

11.5.1 XOSC Failure Detection Control And Status Register

Name:  XFDCSR Offset:  0x62 Reset:  0x00 Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0
XFDIF XFDIE
R R/W
Bit 1 – XFDIF:  Failure Detection Interrupt Flag
This bit is set when a failure is detected, and it can be cleared only by reset.
It serves as status bit for CFD.
Note:  This bit is read only.
Bit 0 – XFDIE: Failure Detection Interrupt Enable
Setting this bit will enable the interrupt which will be issued when XFDIF is set. This bit is enable only. Once enabled, it is not possible for the user to disable.
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ATmega324PB

12. PM - Power Management and Sleep Modes

12.1 Sleep Modes

The following Table shows the different sleep modes, BOD disable ability and their wake-up sources.
Table 12-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains Oscillators Wake-up Sources Software
clk
CPU
Idle Yes Yes Yes Yes Yes Yes
ADC Noise Reduction
Power-down Yes
Power-save Yes Yes Yes
(1)
Standby
Extended Standby
Note: 
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT2, INT1 and INT0, only level interrupt.
4. Start frame detection, only.
5. Main clock is kept running if PTC is enabled.
FLASH
clkIOclk
clk
ADC
Yes Yes Yes Yes Yes
clk
ASY
PTC
(2)
Yes
Yes Yes Yes
Main Clock Source Enabled
Yes Yes
Timer Oscillator Enabled
(5)
Yes
INT and PCINT
(2)
Yes Yes Yes Yes Yes Yes Yes Yes
(2)
Yes
(2)
Yes
(2)
Yes
TWI Address Match
(3)
Yes Yes
(3)
Yes Yes Yes Yes
(3)
Yes Yes Yes Yes Yes
(3)
Yes Yes Yes Yes
(3)
Yes Yes Yes Yes Yes
Timer2 SPM/
EEPROM Ready
(2)
Yes Yes Yes Yes
ADC WDT USART
Other I/O
BOD DisableSleep Mode clk
(4)
To enter any of the six sleep modes, the Sleep Enable bit in the Sleep Mode Control Register (SMCR.SE) must be written to '1' and a SLEEP instruction must be executed. Sleep Mode Select bits (SMCR.SM[2:0]) select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction.
Note:  The block diagram in the section System Clock and Clock Options provides an overview over the different clock systems in the device, and their distribution. This figure is helpful in selecting an appropriate sleep mode.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Related Links
Clock Systems and Their Distribution

12.2 BOD Disable

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see also section Fuse Bits), the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is
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automatically enabled again. This ensures safe operation in case the VCC level has dropped during the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60μs to ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by the BOD Sleep bit in the MCU Control Register (MCUCR.BODS). Writing this bit to '1' turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD active. The default setting, BODS=0, keeps BOD active.
Note:  Writing to the BODS bit is controlled by a timed sequence and an enable bit.
Related Links
MCUCR
Fuse Bits

12.3 Idle Mode

When the SM[2:0] bits are written to '000', the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, 2-wire Serial Interface, ADC, Timer/ Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk
and clk
CPU
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
, while allowing the other clocks to run.
FLASH
ATmega324PB
Related Links
ACSR

12.4 ADC Noise Reduction Mode

When the SM[2:0] bits are written to '001', the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire Serial Interface address watch, Timer/Counter sleep mode basically halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion Complete interrupt, only these events can wake up the MCU from ADC Noise Reduction mode:
External Reset
Watchdog System Reset
Watchdog Interrupt
Brown-out Reset
2-wire Serial Interface address match
Timer/Counter interrupt
SPM/EEPROM ready interrupt
External level interrupt on INT
Pin change interrupt
I/O
, clk
(1)
, and the Watchdog to continue operating (if enabled). This
CPU
, and clk
, while allowing the other clocks to run.
FLASH
Note:  1. Timer/Counter will only keep running in asynchronous mode.
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Related Links
8-bit Timer/Counter2 with PWM and Asynchronous Operation

12.5 Power-Down Mode

When the SM[2:0] bits are written to '010', the SLEEP instruction makes the MCU enter Power-Down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).
Only one of these events can wake up the MCU:
External Reset
Watchdog System Reset
Watchdog Interrupt
Brown-out Reset
2-wire Serial Interface address match
External level interrupt on INT
Pin change interrupt
This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note:  If a level triggered interrupt is used for wake-up from Power-Down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses.
ATmega324PB
When waking up from Power-Down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period.
Related Links
Clock Sources
EXINT - External Interrupts

12.6 Power-Save Mode

When the SM[2:0] bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, except:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.
If the PTC is enabled, the main clock is kept running.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Even if the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2.
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12.7 Standby Mode

When the SM[2:0] bits are written to '110' and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-Down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

12.8 Extended Standby Mode

When the SM[2:0] bits are written to '111' and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-Save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles.

12.9 Power Reduction Registers

The Power Reduction Registers (PRR2, PRR1 and PRR0) provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the corresponding bit in the PRR, puts the module in the same state as before shutdown.
ATmega324PB
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

12.10 Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

12.10.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
Related Links
Analog-to-Digital Converter

12.10.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode.
Related Links
Analog Comparator
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12.10.3 Brown-Out Detector

If the Brown-Out Detector (BOD) is not needed by the application, this module should be turned off. If the BOD is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
Related Links
System Control and Reset

12.10.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-Out Detection, the Analog Comparator or the Analog-to-Digital Converter. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately.
Related Links
System Control and Reset

12.10.5 Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
ATmega324PB
Related Links
System Control and Reset

12.10.6 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
) and the ADC clock (clk
I/O
ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Digital Input Enable and Sleep Modes for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0 for ADC, DIDR1 for AC).
Related Links
Digital Input Enable and Sleep Modes

12.10.7 On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
) are stopped, the input buffers of the device will be disabled. This
ADC
There are three alternative ways to disable the OCD system:
Disable the OCDEN Fuse
Disable the JTAGEN Fuse
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ATmega324PB
Write one to the JTD bit in MCUCR

12.11 Register Description

12.11.1 Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  SMCR Offset:  0x53 Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x33
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
SM[2:0] SE
R/W R/W R/W R/W
Bits 3:1 – SM[2:0]: Sleep Mode Select
The SM[2:0] bits select between the five available sleep modes.
Table 12-2. Sleep Mode Select
SM[2:0] Sleep Mode
000 Idle
001 ADC Noise Reduction
010 Power-down
011 Power-save
100 Reserved
101 Reserved
110 Standby
111 Extended Standby
(1)
(1)
Note: 
1. Standby mode is only recommended for use with external crystals or resonators.
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.
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ATmega324PB

12.11.2 MCU Control Register

The MCU Control Register controls the placement of the Interrupt Vector table in order to move interrupts between application and boot space.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  MCUCR Offset:  0x55 Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x35
Bit 7 6 5 4 3 2 1 0
JTD BODS BODSE PUD IVSEL IVCE
Access
Reset 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Bit 7 – JTD
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system.
Bit 6 – BODS: BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence.
Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
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ATmega324PB
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:  If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section.
Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<<IVCE) out MCUCR, r16
; Move interrupts to Boot Flash section
ori r17, (1<<IVSEL) out MCUCR, r17 ret
C Code Example
void Move_interrupts(void)
{ uchar temp;
/* GET MCUCR*/
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp|(1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = temp|(1<<IVSEL); }

12.11.3 Power Reduction Register 0

Name:  PRR0 Offset:  0x64 Reset:  0x00 Property: -
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ATmega324PB
Bit 7 6 5 4 3 2 1 0
PRTWI0 PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI0 PRUSART0 PRADC
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – PRTWI0: Power Reduction TWI0
Writing a logic one to this bit shuts down the TWI 0 by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.
Bit 6 – PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.
Bit 5 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.
Bit 4 – PRUSART1: Power Reduction USART1
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re initialized to ensure proper operation.
Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.
Bit 2 – PRSPI0: Power Reduction Serial Peripheral Interface 0
If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.
Bit 1 – PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re initialized to ensure proper operation.
Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

12.11.4 Power Reduction Register 1

Name:  PRR1 Offset:  0x65 Reset:  0x00 Property: -
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Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0

12.11.5 Power Reduction Register 2

PRTIM4 PRTIM3
R/W R/W
Bit 1 – PRTIM4: Power Reduction Timer/Counter4
Writing a logic one to this bit shuts down the Timer/Counter4 module. When the Timer/Counter4 is enabled, operation will continue like before the shutdown.
Bit 0 – PRTIM3: Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown.
Name:  PRR2 Offset:  0x63 Reset:  0x00 Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0
PRPTC PRUSART2 PRSPI1 PRTWI1
R/W R/W R/W R/W
Bit 3 – PRPTC: Power Reduction PTC
Writing a logic one to this bit shuts down the PTC module. When the PTC is enabled, operation will continue like before the shutdown.
Bit 2 – PRUSART2: Power Reduction USART2
Writing a logic one to this bit shuts down the USART2 by stopping the clock to the module. When waking up the USART2 again, the USART2 should be re initialized to ensure proper operation.
Bit 1 – PRSPI1: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.
Bit 0 – PRTWI1: Power Reduction TWI1
Writing a logic one to this bit shuts down the TWI1 by stopping the clock to the module. When waking up the TWI1 again, the TWI1 should be re initialized to ensure proper operation.
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13. SCRST - System Control and Reset

13.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an Absolute Jump instruction (JMP) to the reset handling routine for . If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in the next section shows the reset logic.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in the System Clock and Clock Options chapter.
Related Links
System Clock and Clock Options
ATmega324PB

13.2 Reset Sources

The device has the following sources of reset:
Power-on Reset. The MCU is reset when the supply voltage is less than the Power-on Reset
threshold (V
External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the
minimum pulse length.
Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog System Reset mode is enabled.
Brown-out Reset. The MCU is reset when the supply voltage VCC is less than the Brown-out Reset
threshold (V
JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the
scan chains of the JTAG system. Refer to the section IEEE 1149.1 (JTAG) Boundary-scan for details.
).
POT
) and the Brown-out Detector is enabled.
BOT
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Figure 13-1. Reset Logic
Pull-up Resistor
SPIKE FILTER
Watchdog Oscillator
Clock
Generator
Delay Counters
INTERNAL RESET
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
ATmega324PB
Related Links
IEEE 1149.1 (JTAG) Boundary-scan

13.3 Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in Reset after VCC rise. The Reset signal is activated again, without any delay, when VCC decreases below the detection level.
Figure 13-2. MCU Start-up, RESET Tied to V
CC
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Figure 13-3. MCU Start-up, RESET Extended Externally
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
CC

13.4 External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (V edge, the delay counter starts the MCU after the Time-out period (t can be disabled by the RSTDISBL fuse.
ATmega324PB
) on its positive
RST
) has expired. The External Reset
TOUT
Figure 13-4. External Reset During Operation

13.5 Brown-out Detection

The device has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V V
/2. When the BOD is enabled, and VCC decreases to a value below the trigger level (V
HYST
following figure), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (V expired.
in the following figure), the delay counter starts the MCU after the Time-out period t
BOT+
BOT+
= V
BOT
+ V
HYST
/2 and V
BOT-
= V
BOT-
BOT
in the
TOUT
-
has
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than t
.
BOD
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Figure 13-5. Brown-out Reset During Operation
V
CC
RESET
TIME-OUT
INTERNALRESET
V
BOT-
V
BOT+
t
TOUT
CK
CC

13.6 Watchdog System Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t
Figure 13-6. Watchdog System Reset During Operation
TOUT
ATmega324PB
.

13.7 Internal Voltage Reference

13.7.1 Voltage Reference Enable Signals and Start-up Time

The device features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. To save power, the reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in
ACSR (ACSR.ACBG)).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting ACSR.ACBG or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-Down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-Down mode.
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13.8 Watchdog Timer

128kHz
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0 WDP1 WDP2 WDP3
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
Refer to Watchdog System Reset for details on how to configure the watchdog timer.

13.8.1 Features

Clocked from separate On-chip Oscillator
Three operating modes: – Interrupt – System Reset – Interrupt and System Reset
Selectable Time-out period from 16ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

13.8.2 Overview

The device has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the Watchdog Timer Reset (WDR) instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.
ATmega324PB
Figure 13-7. Watchdog Timer
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
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The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and Watchdog
System Reset Enable (WDE) in Watchdog Timer Control Register (WDTCSR.WDCE and WDTCSR.WDE). A logic one must be written to WDTCSR.WDE regardless of the previous value of the WDTCSR.WDE.
2. Within the next four clock cycles, write the WDTCSR.WDE and Watchdog prescaler bits group
(WDTCSR.WDP) as desired, but with the WDTCSR.WDCE cleared. This must be done in one operation.
The following examples show a function for turning off the Watchdog Timer. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
Assembly Code Example
WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<<WDRF)) out MCUSR, r16 ; Write '1' to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out lds r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16 ; Turn off WDT ldi r16, (0<<WDE) sts WDTCSR, r16 ; Turn on global interrupt sei ret
C Code Example
void WDT_off(void)
{ __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); }
Note:  If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time­out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use.
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ATmega324PB
The following code examples shows how to change the time-out value of the Watchdog Timer.
Assembly Code Example
WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16 ; -- Got four cycles to set the new values from here - ; Set new prescaler(time-out) value = 64K cycles (~0.5 s) ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) sts WDTCSR, r16 ; -- Finished setting new values, used 2 cycles - ; Turn on global interrupt sei ret
C Code Example
void WDT_Prescaler_Change(void)
{ __disable_interrupt(); __watchdog_reset(); /* Start timed sequence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */ WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); }
Note:  The Watchdog Timer should be reset before any change of the WDTCSR.WDP bits, since a change in the WDTCSR.WDP bits can result in a time-out when switching to a shorter time-out period.

13.9 Register Description

13.9.1 MCU Status Register

To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  MCUSR Offset:  0x54 [ID-000004d0] Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x34
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Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0
JTRF WDRF BORF EXTRF PORF
R/W R/W R/W R/W R/W
Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to it.
Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to it.
Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to it.
Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a '0' to it.

13.9.2 WDTCSR – Watchdog Timer Control Register

Name:  WDTCSR Offset:  0x60 [ID-000004d0] Reset:  0x00
Bit 7 6 5 4 3 2 1 0
WDIF WDIE WDP[3] WDCE WDE WDP[2:0]
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 – WDIF: Watchdog Interrupt Flag
This bit is set when a timeout occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a '1' to it. When the I-bit in SREG and WDIE are set, the Watchdog Timeout Interrupt is executed.
Bit 6 – WDIE: Watchdog Interrupt Enable
When this bit is written to '1' and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if timeout in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first timeout in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode).
This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety function of the Watchdog System Reset mode. If the interrupt is not executed before the next timeout, a System Reset will be applied.
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Table 13-1. Watchdog Timer Configuration
ATmega324PB
WDTON
1 0 0 Stopped None
1 0 1 Interrupt Mode Interrupt
1 1 0 System Reset Mode Reset
1 1 1 Interrupt and System Reset Mode Interrupt, then go to System Reset Mode
0 x x System Reset Mode Reset
Note:  1. WDTON Fuse set to '0' means programmed and '1' means unprogrammed.
Bit 5 – WDP[3]: Watchdog Timer Prescaler 3
Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to '1', hardware will clear WDCE after four clock cycles. Refer to Overview for how to use WDCE.
Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.
(1)
WDE WDIE Mode Action on Time-out
Bits 2:0 – WDP[2:0]: Watchdog Timer Prescaler 2, 1, and 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding timeout periods are shown in the following table.
Table 13-2. Watchdog Timer Prescale Select
WDP[3] WDP[2] WDP[1] WDP[0] Number of WDT Oscillator (Cycles) Oscillator
0 0 0 0 2K (2048) 16ms
0 0 0 1 4K (4096) 32ms
0 0 1 0 8K (8192) 64ms
0 0 1 1 16K (16384) 0.125s
0 1 0 0 32K (32768) 0.25s
0 1 0 1 64K (65536) 0.5s
0 1 1 0 128K (131072) 1.0s
0 1 1 1 256K (262144) 2.0s
1 0 0 0 512K (524288) 4.0s
1 0 0 1 1024K (1048576) 8.0s
1 0 1 0 Reserved
1 0 1 1
1 1 0 0
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ATmega324PB
WDP[3] WDP[2] WDP[1] WDP[0] Number of WDT Oscillator (Cycles) Oscillator
1 1 0 1
1 1 1 0
1 1 1 1
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14. INT- Interrupts

This section describes the specifics of the interrupt handling of the device. For a general explanation of the AVR interrupt handling, refer to the description of Reset and Interrupt Handling.
In general:
Each Interrupt Vector occupies .
The Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is
affected by the IVSEL bit in MCUCR.
Related Links
Reset and Interrupt Handling

14.1 Interrupt Vectors in ATmega324PB

Table 14-1. Reset and Interrupt Vectors in ATmega324PB
Vector No
1 0x0000
Program Address
(1)
(2)
Source Interrupts definition
RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System
Reset
ATmega324PB
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 INT1 External Interrupt Request 1
4 0x0006 INT2 External Interrupt Request 2
5 0x0008 PCINT0 Pin Change Interrupt Request 0
6 0x000A PCINT1 Pin Change Interrupt Request 1
7 0x000C PCINT2 Pin Change Interrupt Request 2
8 0x000E PCINT3 Pin Change Interrupt Request 3
9 0x0010 WDT Watchdog Time-out Interrupt
10 0x0012 TIMER2_COMPA Timer/Counter2 Compare Match A
11 0x0014 TIMER2_COMPB Timer/Coutner2 Compare Match B
12 0x0016 TIMER2_OVF Timer/Counter2 Overflow
13 0x0018 TIMER1_CAPT Timer/Counter1 Capture Event
14 0x001A TIMER1_COMPA Timer/Counter1 Compare Match A
15 0x001C TIMER1_COMPB Timer/Coutner1 Compare Match B
16 0x001E TIMER1_OVF Timer/Counter1 Overflow
17 0x0020 TIMER0_COMPA Timer/Counter0 Compare Match A
18 0x0022 TIMER0_COMPB Timer/Coutner0 Compare Match B
19 0x0024 TIMER0_OVF Timer/Counter0 Overflow
20 0x0026 SPI0_STC SPI0 Serial Transfer Complete
21 0x0028 USART0_RX USART0 Rx Complete
22 0x002A USART0_UDRE USART0, Data Register Empty
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ATmega324PB
Vector No Program Address
23 0x002C USART0_TX USART0, Tx Complete
24 0x002E ANALOG_COMP Analog Comparator
25 0x0030 ADC ADC Conversion Complete
26 0x0032 EE_READY EEPROM Ready
27 0x0034 TWI0 TWI0 Transfer complete
28 0x0036 SPM_READY Store Program Memory Ready
29 0x0038 USART1_RX USART1 Rx Complete
30 0x003A USART1_UDRE USART1, Data Register Empty
31 0x003C USART1_TX USART0, Tx Complete
32 0x003E TIMER3_CAPT Timer/Counter3 Capture Event
33 0x0040 TIMER3_COMPA Timer/Counter3 Compare Match A
34 0x0042 TIMER3_COMPB Timer/Coutner3 Compare Match B
35 0x0044 TIMER3_OVF Timer/Counter3 Overflow
36 0x0046 USART0_START USART0 Start Frame detection
37 0x0048 USART1_START USART1 Start Frame detection
(2)
Source Interrupts definition
38 0x004A PCINT4 Pin Change Interrupt 4
39 0x004C CFD Crystal Failure Detection
40 0x004E PTC_EOC PTC End of Conversion
41 0x0050 PTC_WCOMP PTC Window comparator mode
42 0x0052 SPI1_STC SPI1 Serial Transfer Complete
43 0x0054 TWI1 TWI1 Transfer complete
44 0x0056 TIMER4_CAPT Timer/Counter4 Capture Event
45 0x0058 TIMER4_COMPA Timer/Counter4 Compare Match A
46 0x005A TIMER4_COMPB Timer/Coutner4 Compare Match B
47 0x005C TIMER4_OVF Timer/Counter4 Overflow
48 0x005E USART2_RX USART2 Rx Complete
49 0x0060 USART2_UDRE USART2, Data Register Empty
50 0x0062 USART2_TX USART2, Tx Complete
51 0x0064 USART2_START USART2 Start Frame detection
Note: 
1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at
reset, see Memory programming
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash
Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.
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ATmega324PB
The table below shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.
Table 14-2. Reset and Interrupt Vectors placement
BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x0000 0x0002
1 1 0x0000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x0002
0 1 Boot Reset Address Boot Reset Address + 0x0002
Note:  The Boot Reset Address is shown in Table Boot size configuration in Boot Loader Parameters. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments 0x00000 RESET: ldi r16,high(RAMEND) ; Main program start 0x00001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x00002 ldi r16,low(RAMEND) 0x00003 out SPL,r16 0x00004 sei ; Enable interrupts 0x00005 <instr> xxx
;
.org 0x1F002 0x1F002 jmp EXT_INT0 ; IRQ0 Handler 0x1F004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x1FO36 jmp SPM_RDY ; SPM Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments .org 0x0002 0x00002 jmp EXT_INT0 ; IRQ0 Handler 0x00004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x00036 jmp SPM_RDY ; SPM Ready Handler
;
.org 0x1F000 0x1F000 RESET: ldi r16,high(RAMEND) ; Main program start 0x1F001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x1F002 ldi r16,low(RAMEND) 0x1F003 out SPL,r16 0x1F004 sei ; Enable interrupts 0x1F005 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
;
.org 0x1F000 0x1F000 jmp RESET ; Reset handler 0x1F002 jmp EXT_INT0 ; IRQ0 Handler
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0x1F004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x1F036 jmp SPM_RDY ; SPM Ready Handler
;
0x1F03E RESET: ldi r16,high(RAMEND) ; Main program start 0x1F03F out SPH,r16 ; Set Stack Pointer to top of RAM 0x1F040 ldi r16,low(RAMEND) 0x1F041 out SPL,r16 0x1F042 sei ; Enable interrupts 0x1FO43 <instr> xxx

14.2 Register Description

14.2.1 Moving Interrupts Between Application and Boot Space

The MCU Control Register controls the placement of the Interrupt Vector table.

14.2.2 MCU Control Register

The MCU Control Register controls the placement of the Interrupt Vector table in order to move interrupts between application and boot space.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
ATmega324PB
Name:  MCUCR Offset:  0x55 Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x35
Bit 7 6 5 4 3 2 1 0
JTD BODS BODSE PUD IVSEL IVCE
Access
Reset 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Bit 7 – JTD
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system.
Bit 6 – BODS: BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
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ATmega324PB
Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence.
Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:  If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section.
Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<<IVCE) out MCUCR, r16
; Move interrupts to Boot Flash section
ori r17, (1<<IVSEL) out MCUCR, r17 ret
C Code Example
void Move_interrupts(void)
{ uchar temp;
/* GET MCUCR*/
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp|(1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = temp|(1<<IVSEL); }
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15. External Interrupts

15.1 EXINT - External Interrupts

The External Interrupts are triggered by the INT pin or any of the PCINT pins. Observe that, if enabled, the interrupts will trigger even if the INT or PCINT pins are configured as outputs. This feature provides a way of generating a software interrupt.
The Pin Change Interrupt Request 4 (PCI4) will trigger if any enabled PCINT[38:32] pin toggles. The Pin Change Interrupt Request 3 (PCI3) will trigger if any enabled PCINT[31:24] pin toggles. The Pin Change Interrupt Request 2 (PCI2) will trigger if any enabled PCINT[23:16] pin toggles. The Pin Change Interrupt Request 1 (PCI1) will trigger if any enabled PCINT[15:8] pin toggles. The Pin Change Interrupt Request 0 (PCI0) will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK4, PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.
The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Register A (EICRA). When the external interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT requires the presence of an I/O clock. Low level interrupt on INT is detected asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
ATmega324PB
Note:  Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses.
Related Links
System Clock and Clock Options

15.1.1 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in the following figure.
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Figure 15-1. Timing of pin change interrupts
LE
D Q
D Q
clk
pin_lat pin_sync pcint_in[i]
pin
PCINT[i] bit
(of PCMSK
n
)
D Q D Q D Q
clk
pcint_sync pcint_set/flag
0
7
PCIF
n
(interrupt
flag)
PCINT[i] pin
pin_lat
pin_sync
clk
pcint_in[i]
pcint_syn
pcint_set/flag
PCIF
n
ATmega324PB

15.1.2 Register Description

15.1.2.1 External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Name:  EICRA Offset:  0x69 Reset:  0x00 Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0
Bits 5:4 – ISC2 [1:0]: Interrupt Sense Control 2
ISC2 [1:0] ISC1 [1:0] ISC0 [1:0]
The External Interrupt 2 is activated by the external pin INT2 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT2 pin that activate the interrupt are defined in table below. The value on the INT2 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
R/W R/W R/W R/W R/W R/W
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ATmega324PB
Value Description
00 The low level of INT2 generates an interrupt request. 01 Any logical change on INT2 generates an interrupt request. 10 The falling edge of INT2 generates an interrupt request. 11 The rising edge of INT2 generates an interrupt request.
Bits 3:2 – ISC1 [1:0]: Interrupt Sense Control 1
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in the table below. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
Value Description
00 The low level of INT1 generates an interrupt request. 01 Any logical change on INT1 generates an interrupt request. 10 The falling edge of INT1 generates an interrupt request. 11 The rising edge of INT1 generates an interrupt request.
Bits 1:0 – ISC0 [1:0]: Interrupt Sense Control 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in table below. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
Value Description
00 The low level of INT0 generates an interrupt request. 01 Any logical change on INT0 generates an interrupt request. 10 The falling edge of INT0 generates an interrupt request. 11 The rising edge of INT0 generates an interrupt request.
15.1.2.2 External Interrupt Mask Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  EIMSK Offset:  0x3D Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x1D
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ATmega324PB
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0
INT2 INT1 INT0
R/W R/W R/W
Bit 2 – INT2: External Interrupt Request 2 Enable
When the INT2 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is enabled. The Interrupt Sense Control2 bits 1/0 (ISC21 and ISC20) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT2 pin or level sensed. Activity on the pin will cause an interrupt request even if INT2 is configured as an output. The corresponding interrupt of External Interrupt Request 2 is executed from the INT2 Interrupt Vector.
Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
15.1.2.3 External Interrupt Flag Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  EIFR Offset:  0x3C Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x1C
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0
INTF2 INTF1 INTF0
R/W R/W R/W
Bit 2 – INTF2: External Interrupt Flag 2
When an edge or logic change on the INT2 pin triggers an interrupt request, INTF2 will be set. If the I-bit in SREG and the INT2 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it. This flag is always cleared when INT2 is configured as a level interrupt.
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ATmega324PB
Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 will be set. If the I-bit in SREG and the INT1 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it. This flag is always cleared when INT1 is configured as a level interrupt.
Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 will be set. If the I-bit in SREG and the INT0 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it. This flag is always cleared when INT0 is configured as a level interrupt.
15.1.2.4 Pin Change Interrupt Control Register
Name:  PCICR Offset:  0x68 Reset:  0x00 Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0
PCIE4 PCIE3 PCIE2 PCIE1 PCIE0
R/W R/W R/W R/W R/W
Bit 4 – PCIE4: Pin Change Interrupt Enable 4
When the PCIE4 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 4 is enabled. Any change on any enabled PCINT[39:32] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI4 Interrupt Vector. PCINT[39:32] pins are enabled individually by the PCMSK4 Register.
Bit 3 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is enabled. Any change on any enabled PCINT[31:24] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3 Interrupt Vector. PCINT[31:24] pins are enabled individually by the PCMSK3 Register.
Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins are enabled individually by the PCMSK2 Register.
Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 1 is enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are enabled individually by the PCMSK1 Register.
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ATmega324PB
Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register.
15.1.2.5 Pin Change Interrupt Flag Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name:  PCIFR Offset:  0x3B Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x1B
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0
PCIF4 PCIF3 PCIF2 PCIF1 PCIF0
R/W R/W R/W R/W R/W
Bit 4 – PCIF4: Pin Change Interrupt Flag 4
When a logic change on any PCINT[39:32] pin triggers an interrupt request, PCIF4 will be set. If the I-bit in SREG and the PCIE4 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it.
Bit 3 – PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT[31:24] pin triggers an interrupt request, PCIF3 will be set. If the I-bit in SREG and the PCIE3 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it.
Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 will be set. If the I-bit in SREG and the PCIE2 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it.
Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[15:8] pin triggers an interrupt request, PCIF1 will be set. If the I-bit in SREG and the PCIE1 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it.
Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 will be set. If the I-bit in SREG and the PCIE0 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to it.
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ATmega324PB
15.1.2.6 Pin Change Mask Register 0
Name:  PCMSK0 Offset:  0x6B Reset:  0x00 Property: -
Bit 7 6 5 4 3 2 1 0
PCINT 7 PCINT 6 PCINT 5 PCINT 4 PCINT 3 PCINT 2 PCINT 1 PCINT 0
Access
Reset 0 0 0 0 0 0 0 0
15.1.2.7 Pin Change Mask Register 1
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT : Pin Change Enable Mask
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
Name:  PCMSK1 Offset:  0x6C Reset:  0x00 Property: -
Bit 7 6 5 4 3 2 1 0
PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT8, PCINT9, PCINT10, PCINT11, PCINT12, PCINT13, PCINT14, PCINT15: Pin Change Enable Mask
Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[15:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[15:8] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
15.1.2.8 Pin Change Mask Register 2
Name:  PCMSK2 Offset:  0x6D Reset:  0x00 Property: -
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ATmega324PB
Bit 7 6 5 4 3 2 1 0
PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16
Access
Reset 0 0 0 0 0 0 0 0
15.1.2.9 Pin Change Mask Register 3
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT16, PCINT17, PCINT18, PCINT19, PCINT20, PCINT21, PCINT22, PCINT23: Pin Change Enable Mask
Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[23:16] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
Name:  PCMSK3 Offset:  0x73 Reset:  0x00 Property: -
PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT24, PCINT25, PCINT26, PCINT27, PCINT28, PCINT29, PCINT30, PCINT31: Pin Change Enable Mask
Each PCINT[31:24]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[31:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[31:24] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
15.1.2.10 Pin Change Mask Register 4
Name:  PCMSK4 Offset:  0x74 Reset:  0x00 Property: -
Bit 7 6 5 4 3 2 1 0
Access
Reset 0 0 0 0 0 0 0
PCINT38 PCINT37 PCINT36 PCINT35 PCINT34 PCINT33 PCINT32
R/W R/W R/W R/W R/W R/W R/W
Bits 0, 1, 2, 3, 4, 5, 6 – PCINT32, PCINT33, PCINT34, PCINT35, PCINT36, PCINT37, PCINT38: Pin Change Enable Mask
Each PCINT[38:32]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[38:32] is set and the PCIE4 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[38:32] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
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16. I/O-Ports

C
pin
Logic
R
pu
See Figure
"General Digital I/O" for
Details
Pxn

16.1 Overview

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in the following figure.
Figure 16-1. I/O Pin Equivalent Schematic
ATmega324PB
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn.
Four I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, Pull-up Enable Register – PUEx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/ write. However, writing '1' to a bit in the PINx Register will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in next section. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Alternate Port Functions section in this chapter. Refer to the individual module sections for a full description of the alternate functions.
Enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.
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16.2 Ports as General Digital I/O

clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
DLQ
Q
RESET
RESET
Q
QD
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER
The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows the functional description of one I/O-port pin, here generically called Pxn.
Figure 16-2. General Digital I/O
ATmega324PB
(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports.

16.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in the Register Description, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written to '1', Pxn is configured as an output pin. If DDxn is written to '0', Pxn is configured as an input pin.
If PORTxn is written to '1' when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written to '0' or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written to '1' when the pin is configured as an output pin, the port pin is driven high. If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low.
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,
I/O
DS40001908A-page 87

16.2.2 Toggling the Pin

XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI instruction can be used to toggle one single bit in a port.

16.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high­impedance environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
The following table summarizes the control signals for the pin value.
Table 16-1. Port Pin Configurations
ATmega324PB
DDxn PORTxn PUD
I/O Pull-up Comment
(in MCUCR)
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)

16.2.4 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Ports as General Digital I/O, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. The following figure shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t
pd,max
and t
respectively.
pd,min
Figure 16-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded
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out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
ATmega324PB
region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the following figure. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 16-4. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Assembly Code Example
... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17 ; Insert nop for synchronization nop ; Read port pins in r16,PINB ...
(1)
Note:  1. For the assembly program, two temporary registers are used to minimize the
time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
C Code Example
unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */
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i = PINB; ...

16.2.5 Digital Input Enable and Sleep Modes

As shown in the figure of General Digital I/O, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in Alternate Port Functions section in this chapter.

If a logic high level is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

16.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
ATmega324PB
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
16.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. The following figure shows how the port pin control signals from the simplified Figure 16-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
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clk
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
DLQ
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
Q D
CLR
Q
Q D
CLR
Q
QD
CLR
PINxn
PORTxn
DDxn
DATA BUS
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL
Pxn
I/O
0
1
WPx: WRITE PINx
WPx
ATmega324PB
Figure 16-5. Alternate Port Functions
(1)
Note:  1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
The following table summarizes the function of the overriding signals. The pin and port indexes from previous figure are not shown in the succeeding tables. The overriding signals are generated internally in
I/O
,
the modules having the alternate function.
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Table 16-2. Generic Description of Overriding Signals for Alternate Functions
ATmega324PB
Signal Name
PUOE Pull-up Override
PUOV Pull-up Override
DDOE Data Direction
DDOV Data Direction
PVOE Port Value
PVOV Port Value
DIEOE Digital Input
DIEOV Digital Input
Full Name Description
Enable
Value
Override Enable
Override Value
Override Enable
Override Value
Enable Override Enable
Enable Override Value
If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.
If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.
If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).
DI Digital Input This is the Digital Input to alternate functions. In the figure, the signal is
connected to the output of the Schmitt Trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.
AIO Analog Input/
Output
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

16.3.1 Alternate Functions of Port A

The Port A pins with alternate functions are shown in the table below:
Table 16-3. Port A Pins Alternate Functions
Port Pin Alternate Functions
PA7
PA6
This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally.
ADC7 (ADC input channel 7) PCINT7 (Pin Change Interrupt 7)
ADC6 (ADC input channel 6) PCINT6 (Pin Change Interrupt 6)
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Port Pin Alternate Functions
ATmega324PB
PA5
PA4
PA3
PA2
PA1
PA0
ADC5 (ADC input channel 5) PCINT5 (Pin Change Interrupt 5)
ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4)
ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3)
ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2)
ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1)
ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0)
The alternate pin configuration is as follows:
ADC[7:0]/PCINT[7:0] – Port A, Bit [7:0] – ADC[7:0]: Analog to Digital Converter Channels [7:0]. – PCINT[7:0]: Pin Change Interrupt source [7:0]. The PA[7:0] pins can serve as external
interrupt sources.
Table 16-4. Overriding Signals for Alternate Functions in PA7...PA4
Signal Name
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
DIEOE PCINT7 • PCIE0 +
DIEOV PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0
DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT
AIO ADC7 INPUT ADC6 INPUT ADC5 INPUT ADC4 INPUT
PA7/ADC7/ PCINT7 PA6/ADC6/ PCINT6 PA5/ADC5/ PCINT5 PA4/ADC4/ PCINT4
ADC7D
PCINT6 • PCIE0 + ADC6D
PCINT5 • PCIE0 + ADC5D
PCINT4 • PCIE0 + ADC4D
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Table 16-5. Overriding Signals for Alternate Functions in PA3...PA0
ATmega324PB
Signal Name
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
DIEOE PCINT3 • PCIE0 +
DIEOV PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 • PCIE0 PCINT0 • PCIE0
DI PCINT3 INPUT PCINT2 INPUT PCINT1 INPUT PCINT0 INPUT
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

16.3.2 Alternate Functions of Port B

Table 16-6. Port B Pins Alternate Functions
PA3/ADC3/ PCINT3 PA2/ADC2/ PCINT2 PA1/ADC1/ PCINT1 PA0/ADC0/ PCINT0
PCINT2 • PCIE0 +
ADC3D
The Port B pins with alternate functions are shown in the table below:
ADC2D
PCINT1 • PCIE0 + ADC1D
PCINT0 • PCIE0 + ADC0D
Port Pin Alternate Functions
PB7 SCK0 (SPI0 Bus Master clock input)
OC3B (Timer/Counter 3 Output Compare Match B Output)
OC4B (Timer/Counter 4 Output Compare Match B Output)
PCINT15 (Pin Change Interrupt 15)
PB6 MISO0 (SPI0 Bus Master Input/Slave Output)
OC3A (Timer/Counter 3 Output Compare Match A Output)
PCINT14 (Pin Change Interrupt 14)
PB5 MOSI0 (SPI0 Bus Master Output/Slave Input)
ICP3 (Timer/Counter3 Input Capture Trigger)
PCINT13 (Pin Change Interrupt 13)
PB4 SS0 (SPI0 Slave Select input)
OC0B (Timer/Counter 0 Output Compare Match B Output)
PCINT12 (Pin Change Interrupt 12)
PB3 AIN1 (Analog Comparator Negative Input)
OC0A (Timer/Counter 0 Output Compare Match A Output)
PCINT11 (Pin Change Interrupt 11)
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Port Pin Alternate Functions
PB2 AIN0 (Analog Comparator Positive Input)
INT2 (External Interrupt 2 Input)
PCINT10 (Pin Change Interrupt 10)
PB1 T1 (Timer/Counter 1 External Counter Input)
CLKO (Divided System Clock Output)
PCINT9 (Pin Change Interrupt 9)
PB0 T0 (Timer/Counter 0 External Counter Input)
XCK0 (USART0 External Clock Input/Output)
PCINT8 (Pin Change Interrupt 8)
The alternate pin configuration is as follows:
SCK0/OC3B/OC4B/PCINT15 – Port B, Bit 7 – SCK0: Master Clock output, Slave Clock input pin for SPI0 channel. When the SPI0 is
enabled as a slave, this pin is configured as an input regardless of the setting of DDRB7. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDRB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit.
OC3B: Output Compare Match B output. The PB7 pin can serve as an external output for the
Timer/Counter3 Output Compare. The pin has to be configured as an output (DDRB7 set “1”) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.
OC4B: Output Compare Match B output. The PB7 pin can serve as an external output for the
Timer/Counter4 Output Compare. The pin has to be configured as an output (DDRB7 set “1”) to serve this function. The OC4B pin is also the output pin for the PWM mode timer function.
PCINT15: Pin Change Interrupt source 15. The PB7 pin can serve as an external interrupt
source.
MISO0/OC3A/PCINT14 – Port B, Bit 6 – MISO0: Master Data input, Slave Data output pin for SPI0 channel. When the SPI0 is enabled
as a master, this pin is configured as an input regardless of the setting of DDRB6. When the SPI0 is enabled as a slave, the data direction of this pin is controlled by DDRB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit.
OC3A: Output Compare Match A output. The PB6 pin can serve as an external output for the
Timer/Counter3 Output Compare. The pin has to be configured as an output (DDRB6 set “1”) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function.
PCINT14: Pin Change Interrupt source 14. The PB6 pin can serve as an external interrupt
source.
ATmega324PB
MOSI0/ICP3/PCINT13 – Port B, Bit 5 – MOSI0: SPI0 Master Data output, Slave Data input for SPI0 channel. When the SPI0 is
enabled as a slave, this pin is configured as an input regardless of the setting of DDRB5. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDRB5.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. – ICP3: Input Capture Pin 3. The PB5 pin can act as an input capture pin for Timer/Counter3. – PCINT13: Pin Change Interrupt source 13. The PB5 pin can serve as an external interrupt
source.
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ATmega324PB
SS0/OC0B/PCINT12 – Port B, Bit 4 – SS0: Slave Port Select input. When the SPI0 is enabled as a slave, this pin is configured as
an input regardless of the setting of DDRB4. As a slave, the SPI0 is activated when this pin is driven low. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDRB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit.
OC0B: Output Compare Match B output. The PB4 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDRB4 set “1”) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
PCINT12: Pin Change Interrupt source 12. The PB4 pin can serve as an external interrupt
source.
AIN1/OC0A/PCINT11– Port B, Bit 3 – AIN1: Analog Comparator Negative input. This pin is directly connected to the negative input
of the Analog Comparator.
OC0A: Output Compare Match A output. The PB3 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDRB3 set “1”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.
PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt
source.
AIN0/INT2/PCINT10 – Port B, Bit 2 – AIN0: Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
INT2: External Interrupt source 2. The PB2 pin can serve as an External Interrupt source to
the MCU.
PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt
source.
T1/CLKO/PCINT9 – Port B, Bit 1 – T1: Timer/Counter1 counter source. – CLKO: Divided System Clock: The divided system clock can be output on the PB1 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDRB1 settings. It will also be output during reset.
PCINT9: Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt
source.
T0/XCK0/PCINT8 – Port B, Bit 0 – T0: Timer/Counter0 counter source. – XCK0: USART0 External clock. The Data Direction Register (DDRB0) controls whether the
clock is output (DDRB0 set “1”) or input (DDRB0 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode.
PCINT8: Pin Change Interrupt source 8. The PB0 pin can serve as an external interrupt
source.
Table 16-7 and Table 16-8 relate the alternate functions of Port B to the overriding signals shown in Figure 16-5. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is
divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
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Table 16-7. Overriding Signals for Alternate Functions in PB7...PB4
ATmega324PB
Signal Name
PUOE SPE0 • MSTR SPE0 • MSTR SPE0 • MSTR SPE0 • MSTR
PUOV PORTB7 • PUD PORTB6 • PUD PORTB5 • PUD PORTB4 • PUD
DDOE SPE0 • MSTR SPE0 • MSTR SPE0 • MSTR SPE0 • MSTR
DDOV 0 0 0 0
PVOE
PVOV SCK0 OUTPUT + OC3B/
DIEOE PCINT15 • PCIE1 PCINT14 • PCIE1 PCINT13 • PCIE1 PCINT12 • PCIE1
DIEOV 1 1 1 1
DI
AIO - -
PB7/SCK0/OC3B/OC4B/ PCINT15
SPE0 • MSTR OC3B/OC4B ENABLE
OC4B
SCK0 INPUT PCINT15 INPUT
PB6/MISO0/OC3A/ PCINT14
SPE0 • MSTR OC3A ENABLE
SPI0 SLAVE OUTPUT + OC3A
SPI0 MSTR INPUT PCINT14 INPUT
PB5/MOSI0/ICP3/ PCINT13
SPE0 • MSTR OC0B ENABLE
SPI0 MSTR OUTPUT OC0B
SPI0 SLAVE INPUT ICP3 INPUT PCINT13 INPUT
PB4/SS0/OC0B/ PCINT12
SPI SS0 PCINT12 INPUT
Table 16-8. Overriding Signals for Alternate Functions in PB3...PB0
Signal Name
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 CKOUT 0
DDOV 0 0 CKOUT 0
PVOE OC0A ENABLE 0 CKOUT UMSEL
PVOV OC0A 0 CLK I/O XCK0 OUTPUT
DIEOE PCINT11 • PCIE1
DIEOV 1 1 1 1
DI PCINT11 INPUT
PB3/AIN1/OC0A/PCINT11 PB2/AIN0/INT2/PCINT10 PB1/T1/CLKO/PCINT9 PB0/T0/XCK0/PCINT8
INT2 ENABLE
PCINT10 • PCIE1
INT2 INPUT PCINT10 INPUT
PCINT9 • PCIE1 PCINT8 • PCIE1
T1 INPUT PCINT9 INPUT
T0 INPUT XCK0 INPUT PCINT8 INPUT
AIO AIN1 INPUT AIN0 INPUT
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16.3.3 Alternate Functions of Port C

The Port C pins with alternate functions are shown in the table below:
Table 16-9. Port C Pins Alternate Functions
Port Pin Alternate Function
PC7 TOSC2 (Timer Oscillator pin 2)
PCINT23 (Pin Change Interrupt 23)
PC6 TOSC1 (Timer Oscillator pin 1)
PCINT22 (Pin Change Interrupt 22)
PC5 ACO
TDI (JTAG Test Data Input)
PCINT21 (Pin Change Interrupt 21)
PC4 OC4A (Timer/Counter 4 Output Compare Match A Output)
TDO (JTAG Test Data Output)
PCINT20 (Pin Change Interrupt 20)
ATmega324PB
PC3 ICP4 (Timer/Counter4 Input Capture Trigger)
TMS (JTAG Test Mode Select)
PCINT19 (Pin Change Interrupt 19)
PC2 T4 (Timer/Counter 4 External Counter Input)
TCK (JTAG Test Clock)
PCINT18 (Pin Change Interrupt 18)
PC1 SDA0 (two-wire Serial Bus0 Data Input/Output Line)
PCINT17 (Pin Change Interrupt 17)
PC0 SCL0 (two-wire Serial Bus0 Clock Line)
PCINT16 (Pin Change Interrupt 16)
The alternate pin configuration is as follows:
TOSC2/PCINT23 – Port C, Bit 7 – TOSC2, Timer Oscillator pin 2. The PC7 pin can serve as an external interrupt source to the
MCU.
PCINT23: Pin Change Interrupt source 23. The PC7 pin can serve as an external interrupt
source.
TOSC1/PCINT22 – Port C, Bit 6 – TOSC1, Timer Oscillator pin 1. The PC6 pin can serve as an external interrupt source to the
MCU.
PCINT22: Pin Change Interrupt source 22. The PC6 pin can serve as an external interrupt
source.
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Datasheet Complete
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ATmega324PB
TDI/PCINT21 – Port C, Bit 5 – TDI: JTAG Test Data Input – PCINT21: Pin Change Interrupt source 21. The PC5 pin can serve as an external interrupt
source.
OC4A/TDO/PCINT20 – Port C, Bit 4 – OC4A: Timer/Counter 4 Output Compare Match A Output – TDO: JTAG Test Data Output – PCINT20: Pin Change Interrupt source 20. The PC4 pin can serve as an external interrupt
source.
TMS/ICP4/PCINT19 – Port C, Bit 3 – TMS: JTAG Test Mode Select – ICP4: Timer/Counter4 Input Capture Trigger – PCINT19: Pin Change Interrupt source 19. The PC3 pin can serve as an external interrupt
source.
TCK/T4/PCINT18 – Port C, Bit 2 – TCK: JTAG Test Clock – T4: Timer/Counter 4 External Counter Input – PCINT18: Pin Change Interrupt source 18. The PC2 pin can serve as an external interrupt
source.
SDA0/PCINT17 – Port C, Bit 1 – SDA0: two-wire Serial Bus0 Data Input/Output Line – PCINT17: Pin Change Interrupt source 17. The PC1 pin can serve as an external interrupt
source.
SCL0/PCINT16 – Port C, Bit 0 – SCL0: two-wire Serial Bus0 Clock Line – PCINT16: Pin Change Interrupt source 16. The PC0 pin can serve as an external interrupt
source.
The tables below relate the alternate functions of Port C to the overriding signals shown in Figure 16-5.
Table 16-10. Overriding Signals for Alternate Functions in PC7...PC4
Signal Name
PUOE AS2 • EXCLK AS2 JTAGEN JTAGEN
PUOV 0 0 1 1
DDOE AS2 • EXCLK AS2 JTAGEN
DDOV 0 0 0
PC7/TOSC2/PCINT23 PC6/TOSC1/PCINT22 PC5/TDI/PCINT21 PC4/OC4A/TDO/PCINT20
JTAGEN OC4A ENABLE
SHIFT_IR + SHIFT_DR + OC4A
PVOE 0 0 0 JTAGEN
PVOV 0 0 0 TDO
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Datasheet Complete
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ATmega324PB
Signal Name
DIEOE AS2 • EXCLK + PCINT23
DIEOV AS2 EXCLK + AS2 JTAGEN JTAGEN
DI PCINT23 INPUT PCINT22 INPUT PCINT21 INPUT PCINT20 INPUT
AIO T/C2 OSC OUTPUT T/C1 OSC INPUT TDI INPUT -
Table 16-11. Overriding Signals for Alternate Functions in PC3...PC0
Signal Name
PUOE JTAGEN JTAGEN TWEN TWEN
PUOV 1 1 PORTC1 • PUD PORTC0 • PUD
DDOE JTAGEN JTAGEN TWEN TWEN
DDOV 0 0 0 0
PVOE 0 0 TWEN TWEN
PVOV 0 0 SDA OUT SCL OUT
PC7/TOSC2/PCINT23 PC6/TOSC1/PCINT22 PC5/TDI/PCINT21 PC4/OC4A/TDO/PCINT20
AS2 + PCINT22 •
• PCIE2
PC3/TMS/ICP4/PCINT19 PC2/T4/PCINT18 PC1/SDA0/PCINT17 PC0/SCL0/PCINT16
PCIE2
JTAGEN + PCINT21 • PCIE2
JTAGEN + PCINT20 • PCIE2
DIEOE JTAGEN + PCINT19 • PCIE2 JTAGEN + PCINT18 • PCIE2 PCINT17 • PCIE2 PCINT16 • PCIE2
DIEOV JTAGEN JTAGEN 1 1
DI
AIO TMS INPUT TCK INPUT SDA0 INPUT SCL0 INPUT

16.3.4 Alternate Functions of Port D

Table 16-12. Port D Pins Alternate Functions
Port Pin Alternate Function
PD7 OC2A (Timer/Counter2 Output Compare Match A Output)
PD6 ICP1 (Timer/Counter1 Input Capture Trigger)
ICP4 INPUT PCINT19 INPUT
The Port D pins with alternate functions are shown in the table below:
XCK2 (USART2 External Clock Input/Output)
SCK1 (SPI1 Bus Master clock Input)
PCINT31 (Pin Change Interrupt 31)
OC2B (Timer/Counter2 Output Compare Match B Output)
T4 INPUT PCINT18 INPUT
PCINT17 INPUT PCINT16 INPUT
SS1 (SPI1 Slave Select input)
PCINT30 (Pin Change Interrupt 30)
PD5 OC1A (Timer/Counter1 Output Compare Match A Output)
© 2017 Microchip Technology Inc.
Datasheet Complete
DS40001908A-page 100
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