AVR Microcontroller with Core Independent Peripherals
and PicoPower technology
Introduction
The picoPower® ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves
throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed.
Feature
High Performance, Low Power AVR® 8-Bit Microcontroller Family
•Advanced RISC Architecture
–131 Powerful Instructions
–Most Single Clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 20 MIPS Throughput at 20MHz
–On-Chip 2-cycle Multiplier
•High Endurance Non-Volatile Memory Segments
–32KBytes of In-System Self-Programmable Flash Program Memory
–1KBytes EEPROM
–2KBytes Internal SRAM
–Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
–Data Retention: 20 Years at 85°C
–Optional Boot Code Section with Independent Lock Bits
•In-System Programming by On-chip Boot Program
•True Read-While-Write Operation
–Programming Lock for Software Security
•JTAG (IEEE std. 1149.1 Compliant) Interface
–Boundary-Scan Capabilities According to the JTAG Standard
–Extensive On-chip Debug Support
–Programming of Flash, EEPROM, Fuses, and Lock Bits Through the JTAG Interface
•Peripheral Features
–Peripheral Touch Controller (PTC)
•Capacitive Touch Buttons, Sliders and Wheels
•32 Self-Sap Channels and 256 Mutual Cap Channels
–Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
–Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode
–Real Time Counter with Separate Oscillator
–Ten PWM Channels
–8-Channel 10-Bit ADC
•Differential Mode with Selectable Gain at 1×, 10× or 200×
–Three Programmable Serial USARTs
–Two Master/Slave SPI Serial Interfaces
–Two Byte-oriented 2-wire Serial Interfaces (Philips I2C Compatible)
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
–Interrupt and Wake-up on Pin Change
•Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection
–Internal 8 MHz Calibrated Oscillator
–External and Internal Interrupt Sources
–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended
Standby
–Clock Failure Detection Mechanism and Switch to Internal 8 MHz RC Oscillator in case of Failure
–Individual Serial Number to Represent a Unique ID
•I/O and Packages
–39 Programmable I/O Lines
–44-Pin TQFP and 44-Pin QFN /MLF
The ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves
throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed.
The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega324PB provides the following features: 32K bytes of In-System Programmable Flash with
Read-While-Write capabilities, 1Kbytes EEPROM, 2Kbytes SRAM, 39 general purpose I/O lines, 32
general purpose working registers, five flexible Timer/Counters with compare modes, internal and
external interrupts, three serial programmable USART, two byte-oriented 2-wire Serial Interface (I2C), two
SPI serial port, a 8-channel 10-bit ADC with optional differential input stage with programmable gain, a
programmable Watchdog Timer with internal Oscillator, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the On-chip Debug system and programming, Clock failure detection mechanism
and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning.
PTC with enabling up to 32 self-cap and 256 mutual-cap sensors. The Power-down mode saves the
register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to
maintain a timer base while the rest of the device is sleeping. Also ability to run PTC in power-save mode/
wake-up on touch and Dynamic on/off of PTC analog and digital portion. The ADC Noise Reduction mode
stops the CPU and all I/O modules except asynchronous timer, PTC, and ADC to minimize switching
noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest
of the device is sleeping. This allows very fast start-up combined with low power consumption.
ATmega324PB
The device is manufactured using high density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the ATmega324PB is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega324PB is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
This port serves as analog inputs to the Analog-to-digital Converter.
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
5.1.4 Port B (PB[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
This port also serves the functions of various special features.
5.1.5 Port C (PC[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
ATmega324PB
This port also serves the functions of the JTAG interface, along with special features.
5.1.6 Port D (PD[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a reset condition, even if the clock is not running.
This port also serves the functions of various special features.
5.1.7 Port E (PE6:0) XTAL1/XTAL2/AREF
This is a 7-bit bi-directional GPIO port with internal pull-up resistors (selected for each pin). The Port E
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated. Port pins
are tri-stated during a reset condition, even if the clock is not running. PE0 and PE1 are multiplexed with
XTAL1 and XTAL2 input. PE4 is multiplexed with AREF for the A/D Converter.
5.1.8 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a reset.
5.1.9 AVCC
AVCC is the supply voltage pin for Port A, PE4 (AREF) and the Analog-to-digital Converter. It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to
VCC through a low-pass filter.
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
7.2 About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confer with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 8-1. Block Diagram of the AVR Architecture
ATmega324PB
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt
Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from
0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide
a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See InstructionSet Summary section for a detailed description.
Related Links
Instruction Set Summary
8.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set
Reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: SREG
Offset: 0x5F
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x3F
Bit 76543210
Access
Reset 00000000
ITHSVNZC
R/WR/WR/WR/WR/WR/WR/WR/W
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared,
none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T: Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in
BCD arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S: Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the Instruction Set Description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
8.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
•One 8-bit output operand and one 8-bit result input
•Two 8-bit output operands and one 8-bit result input
•Two 8-bit output operands and one 16-bit result input
•One 16-bit output operand and one 16-bit result input
Figure 8-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user Data Space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
ATmega324PB
8.4.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
Figure 8-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to
lower memory locations. The Stack Pointer Register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack
Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point
above start of the SRAM. See the table for Stack Pointer details.
Table 8-1. Stack Pointer Instructions
Instruction Stack pointerDescription
PUSHDecremented by 1 Data is pushed onto the stack
ATmega324PB
CALL
ICALL
RCALL
POPIncremented by 1Data is popped from the stack
RET
RETI
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
8.5.1 Stack Pointer Register Low and High byte
The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
Incremented by 2Return address is popped from the stack with return from subroutine or
return from interrupt
Name: SPL and SPH
Offset: 0x5D
Reset: 0x8FF
Property: When addressing I/O Registers as data space the offset address is 0x3D
The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These
registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the
8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte
is then written into the temporary register. When the high byte of the 16-bit register is written, the
temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
SP[11:8]
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low
byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register
in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the
temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when
reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit
register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when
writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
8.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clk
clock division is used. The Figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
, directly generated from the selected clock source for the chip. No internal
Figure 8-4. The Parallel Instruction Fetches and Instruction Executions
The following figure shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 8-5. Single Cycle ALU Operation
8.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector
each have a separate program vector in the program memory space. All interrupts are assigned
individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the
Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may
be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt
Vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors
can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programming
the BOOTRST Fuse.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program
Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and
hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic
one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled,
or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI
instruction. The following example shows how this can be used to avoid interrupts during the timed
EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before
any pending interrupts, as shown in this example.
Assembly Code Example
sei; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
(1)
(1)
1.Refer to About Code Examples.
Related Links
Memory Programming
Boot Loader Support – Read-While-Write Self-Programming
About Code Examples
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After
four clock cycles the program vector address for the actual interrupt handling routine is executed. During
this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump
to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs
when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles.
This increase comes in addition to the start-up time from the selected sleep mode. A return from an
interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter
(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in
SREG is set.
This section describes the different memory types in the device. The AVR architecture has two main
memory spaces, the Data Memory and the Program Memory space. In addition, the device features an
EEPROM Memory for data storage. All memory spaces are linear and regular.
9.2 In-System Reprogrammable Flash Program Memory
The ATmega324PB contains 32K bytes on-chip in-system reprogrammable Flash memory for program
storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32K x 16. For
software security, the Flash Program memory space is divided into two sections - Boot Loader Section
and Application Program Section in the device .
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega324PB Program
Counter (PC) is 15 bits wide, thus addressing the 32K program memory locations. The operation of the
Boot Program section and associated Boot Lock bits for software protection are described in detail in
Boot Loader Support – Read-While-Write Self-Programming. Refer to Memory Programming for the
description on Flash data serial downloading using the SPI pins or the JTAG interface.
ATmega324PB
Constant tables can be allocated within the entire program memory address space, using the Load
Program Memory (LPM) instruction.
Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.
The following figure shows how the device SRAM Memory is organized.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60
- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 4352 data memory locations address both the Register File, the I/O memory, Extended I/O
memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64
location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096
locations address the internal data SRAM.
The five different addressing modes for the data memory cover:
•Direct
–The direct addressing reaches the entire data space.
•Indirect with Displacement
–The Indirect with Displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.
•Indirect
–In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
•Indirect with Pre-decrement
–The address registers X, Y, and Z are decremented.
•Indirect with Post-increment
–The address registers X, Y, and Z are incremented.
ATmega324PB
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2K
bytes of internal data SRAM in the device are all accessible through all these addressing modes.
Figure 9-2. Data Memory Map with 2048 byte internal data SRAM
9.3.1 Data Memory Access Times
The internal data SRAM access is performed in two clk
The ATmega324PB contains 1K bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following,
specifying the EEPROM Address registers, the EEPROM Data register, and the EEPROM Control
register.
See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programming
mode.
Related Links
MEMPROG- Memory Programming
9.4.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 9-2. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall
slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. Please refer to Preventing EEPROM Corruption for
details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to
the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction
is executed.
During periods of low V
the CPU and the EEPROM to operate properly. These issues are the same as for board level systems
using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular
write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself
can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done
by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not
match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset
occurs while a write operation is in progress, the write operation will be completed provided that the
power supply voltage is sufficient.
the EEPROM data can be corrupted because the supply voltage is too low for
CC,
9.5 I/O Memory
The I/O space definition of the device is shown in the Register Summary.
All device I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the
LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working
registers and the I/O space. I/O Registers within the address range 0x00-0x1F are directly bit-accessible
using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using
the SBIS and SBIC instructions.
ATmega324PB
When using the I/O specific commands IN and OUT, the I/O addresses 0x00-0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60..0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O
memory addresses should never be written.
Some of the Status Flags are cleared by writing a '1' to them; this is described in the flag descriptions.
Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with
registers 0x00-0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
Related Links
MEMPROG- Memory Programming
Instruction Set Summary
9.5.1 General Purpose I/O Registers
The device contains three General Purpose I/O Registers, General Purpose I/O Register 0/1/2 (GPIOR
0/1/2). These registers can be used for storing any information, and they are particularly useful for storing
global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These
registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the
8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte
is then written into the temporary register. When the high byte of the 16-bit register is written, the
temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low
byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register
in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the
temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when
reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit
register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when
writing or reading 16-bit registers.
ATmega324PB
The temporary registers can also be read and written directly from user software.
9.6.2 EEPROM Address Register Low and High Byte
The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For
more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: EEARL and EEARH
Offset: 0x41 [ID-000004d0]
Reset: 0xXX
Property: When addressing as I/O Register: address offset is 0x21
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1K Bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023. The initial value
of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: EEDR
Offset: 0x40 [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x20
Bit 76543210
Access
Reset 00000000
R/WR/WR/WR/WR/WR/WR/WR/W
EEDR[7:0]
Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in
the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data
read out from the EEPROM at the address given by EEAR.
9.6.4 EEPROM Control Register
Name: EECR
Offset: 0x3F [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1F
The EEPROM Programming mode bit setting defines which programming action that will be triggered
when writing EEPE. It is possible to program data in one atomic operation (erase the old value and
program the new value) or to split the Erase and Write operations into two different operations. The
Programming times for the different modes are shown in the table below. While EEPE is set, any write to
EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy
programming.
Table 9-1. EEPROM Mode Bits
EEPM[1:0]Programming TimeOperation
003.4msErase and Write in one operation (Atomic Operation)
011.8msErase Only
101.8msWrite Only
11-Reserved for future use
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to
zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is
cleared. The interrupt will not be generated during EEPROM write or SPM.
Bit 2 – EEMPE: EEPROM Master Write Enable
The EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written.
When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selected
address.
If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software,
hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an
EEPROM write procedure.
Bit 1 – EEPE: EEPROM Write Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are
correctly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bit
must be written to '1' before EEPE is written to '1', otherwise no EEPROM write takes place. The following
procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1.Wait until EEPE becomes zero.
2.Wait until SPMEN in SPMCSR becomes zero.
3.Write new EEPROM address to EEAR (optional).
4.Write new EEPROM data to EEDR (optional).
5.Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR.
6.Within four clock cycles after setting EEMPE, write a '1' to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must
check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only
relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is
never being updated by the CPU, step 2 can be omitted.
Caution:
An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master
Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another
EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted
EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all
the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user
software can poll this bit and wait for a zero before writing the next byte. When EEPE has been
set, the CPU is halted for two cycles before the next instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address
is set up in the EEAR Register, the EERE bit must be written to a '1' to trigger the EEPROM read. The
EEPROM read access takes one instruction, and the requested data is available immediately. When the
EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it
is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. See the following table for typical
programming times for EEPROM access from the CPU.
Table 9-2. EEPROM Programming Time
SymbolNumber of Calibrated RC Oscillator CyclesTyp. Programming Time
EEPROM write (from CPU)26,3683.3ms
The following code examples show one assembly and one C function for writing to the EEPROM. The
examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts
will occur during execution of these functions. The examples also assume that no Flash Boot Loader is
present in the software. If such code is present, the EEPROM write function must also wait for any
ongoing SPM command to finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous writesbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address registerout EEARH, r18
out EEARL, r17
; Write data (r16) to Data Registerout EEDR,r16
; Write logical one to EEMPEsbi EECR,EEMPE
; Start eeprom write by setting EEPEsbi EECR,EEPE
ret
/* Wait for completion of previous write */while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
Note: (1) Please refer to About Code Examples
The following code examples show assembly and C functions for reading the EEPROM. The examples
assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address registerout EEARH, r18
out EEARL, r17
; Start eeprom read by writing EEREsbi EECR,EERE
; Read data from Data Registerin r16,EEDR
ret
(1)
C Code Example
unsignedchar EEPROM_read(unsignedint uiAddress)
{
/* Wait for completion of previous write */while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */return EEDR;
}
(1)
1.Refer to About Code Examples.
9.6.5 GPIOR2 – General Purpose I/O Register 2
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: GPIOR2
Offset: 0x4B [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x2B
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: GPIOR1
Offset: 0x4A [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x2A
Bit 76543210
Access
Reset 00000000
R/WR/WR/WR/WR/WR/WR/WR/W
GPIOR2[7:0]
GPIOR1[7:0]
Bits 7:0 – GPIOR1[7:0]: General Purpose I/O
9.6.7 GPIOR0 – General Purpose I/O Register 0
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: GPIOR0
Offset: 0x3E [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1E
The following figure illustrates the principal clock systems in the device and their distribution. All the
clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes. The clock systems are described in the
following sections.
The system clock frequency refers to the frequency generated from the System Clock Prescaler. All clock
outputs from the AVR Clock Control Unit runs in the same frequency.
Figure 10-1. Clock Distribution
ATmega324PB
10.1.1 CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of
such modules are the General Purpose Register File, the Status Register and the data memory holding
the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and
calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O
clock is also used by the External Interrupt module, but the start condition detection in the USI module is
carried out asynchronously when clk
Note: If a level triggered interrupt is used for wake-up from Power-down, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears
before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The
start-up time is defined by the SUT and CKSEL Fuses.
10.1.3 PTC Clock - clk
PTC
The PTC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order
to reduce noise and power due to digital circuitry.
10.1.4 Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously
with the CPU clock.
10.1.5 Asynchronous Timer Clock – clk
The Asynchronous Timer clock allows Asynchronous Timer/Counters to be clocked directly from an
external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/
Counter as a real-time counter even when the device is in sleep mode.
is halted, TWI address recognition in all sleep modes.
I/O
ASY
10.1.6 ADC Clock – clk
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order
to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
10.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The
clock from the selected source is input to the AVR clock generator, and routed to the appropriate
modules.
Table 10-1. Device Clocking Options Select
Device Clocking OptionCKSEL[3:0]
Low Power Crystal Oscillator1111 - 1000
Low Frequency Crystal Oscillator0101 - 0100
Internal 128kHz RC Oscillator0011
Calibrated Internal RC Oscillator0010
External Clock0000
Reserved0001
ADC
Note: For all fuses, '1' means unprogrammed while '0' means programmed.
10.2.1 Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed,
resulting in 1.0MHz system clock. The start-up time is set to maximum, and the time-out period is
enabled: CKSEL=0010, SUT=10, CKDIV8=0. This default setting ensures that all users can make their
desired clock source setting using any available programming interface.
10.2.2 Clock Start-up Sequence
Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles
before it can be considered stable.
ATmega324PB
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (t
) after the device
TOUT
reset is released by all other reset sources. See the Related Links for a description of the start conditions
for the internal reset. The delay (t
) is timed from the Watchdog Oscillator and the number of cycles in
TOUT
the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in the Table below.
The frequency of the Watchdog Oscillator is voltage dependent.
Main purpose of the delay is to keep the device in reset until it is supplied with minimum VCC. The delay
will not monitor the actual voltage, so it is required to select a delay longer than the VCC rise time. If this is
not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure
sufficient VCC before it releases the reset, and the time-out delay can be disabled. Disabling the time-out
delay without utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is considered
stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active
for a given number of clock cycles. The reset is then released and the device will start to execute. The
recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an
externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when the
device starts up from reset. When starting up from Power-save or Power-down mode, VCC is assumed to
be at a sufficient level and only the start-up time is included.
10.2.3 Clock Source Connections
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip Oscillator, as shown in the Figure below. Either a quartz crystal or a
ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors
depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic
noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in
the next Table. For ceramic resonators, the capacitor values given by the manufacturer should be used.
The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting
crystals, load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into
consideration. Both values are specified by the crystal vendor. The oscillator is optimized for very low
power consumption, and thus when selecting crystals, consider the Maximum ESR Recommendations:
Table 10-3. Maximum ESR Recommendation for 32.768kHz Crystal
Crystal CL [pF]Max. ESR [kΩ]
ATmega324PB
9.065
12.530
The Low-frequency Crystal Oscillator provides an internal load capacitance at each TOSC pin:
Table 10-4. Internal capacitance of Low-Frequency Oscillator
32kHz Osc. TypeInternal Pad Capacitance
(XTAL1/TOSC1)
Ci of system oscillator (XTAL pins) 6pF6pF
Ci of timer oscillator (TOSC pins)4pF4pF
The capacitance (Ce+Ci) needed at each XTAL/TOSC pin can be calculated by using:
+ = 2
where:
•Ce - is optional external capacitors. (=C1, C2 as shown in Figure 10-2)
•Ci - is the pin capacitance in Table 10-4.
•CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor.
•CS - is the total stray capacitance for one TOSC pin.
Crystals specifying a load capacitance (CL) higher than 6pF require external capacitors applied according
to above formula.
Internal Pad Capacitance
(XTAL2/TOSC2)
When this oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown
in the following table.
Table 10-5. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
Power Conditions Start-up Time from
Power-down and Power-
Additional Delay from Reset
(VCC = 5.0V)
CKSEL[0] SUT[1:0]
save
BOD enabled1K CK14CK
Fast rising power1K CK14CK + 4ms
Slowly rising power 1K CK14CK + 65ms
(1)
(1)
(1)
000
001
010
Reserved011
BOD enabled32K CK14CK100
Fast rising power32K CK14CK + 4ms101
Slowly rising power 32K CK14CK + 65ms110
Reserved111
Note:
1.This option should only be used if frequency stability at start-up is not important for the application.
Related Links
Clock Source Connections
10.4 Low Power Crystal Oscillator
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives
the lowest power consumption, but is not capable of driving other clock inputs, and may be more
susceptible to noise in noisy environments.
The crystal should be connected as described in Clock Source Connections. When selecting crystals,
load capacitance must be taken into consideration. The capacitance (Ce+Ci) needed at each TOSC pin
can be calculated by using:
+ = 2
where:
•Ce - is optional external capacitors. (= C1, C2 as shown in Figure 10-2)
•Ci - is the pin capacitance in Table 10-6.
•CL - is the load capacitance specified by the crystal vendor.
•CS - is the total stray capacitance for one XTAL pin.
Table 10-6. Internal capacitance of Low-Power Oscillator
32kHz Osc. TypeInternal Pad Capacitance
Ci of system oscillator (XTAL pins) 6pF6pF
The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL[3:1], as shown in the following table:
Table 10-7. Low Power Crystal Oscillator Operating Modes
Frequency Range
CKSEL[3:1]
(2)
Range for total capacitance of C1 and C2 [pF]
[MHz]
0.4 - 0.9100
(3)
–
0.9 - 3.010112 - 22
3.0 - 8.011012 - 22
8.0 - 16.011112 - 22
Note:
1.If the crystal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse
can be programmed in order to divide the internal frequency by 8. It must be ensured that the
resulting divided clock meets the frequency specification of the device.
2.This is the recommended CKSEL settings for the difference frequency ranges.
3.This option should not be used with crystals, only with ceramic resonators.
4.The range of the
capacitance should not be larger than the value given in this table.
The CKSEL0 Fuse together with the SUT[1:0] Fuses select the start-up times, as shown in the following
table:
(1)
(4)
Table 10-8. Start-up Times for the Low Power Crystal Oscillator Clock Selection
Oscillator Source / Power
Conditions
Ceramic resonator, fast rising power258 CK14CK + 4ms
Ceramic resonator, slowly rising
Start-up Time from
Power-down and
Power-save
Additional Delay from
Reset
(VCC = 5.0V)
258 CK14CK + 65ms
(1)
(1)
CKSEL0 SUT[1:0]
000
001
power
Ceramic resonator, BOD enabled1K CK14CK
Ceramic resonator, fast rising power1K CK14CK + 4ms
Ceramic resonator, slowly rising
1K CK14CK + 65ms
(2)
(2)
(2)
010
011
100
power
Crystal Oscillator, BOD enabled16K CK14CK101
Crystal Oscillator, fast rising power16K CK14CK + 4ms110
Crystal Oscillator, slowly rising power 16K CK14CK + 65ms111
Note:
1.These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These options
are not suitable for crystals.
2.These options are intended for use with ceramic resonators and will ensure frequency stability at
start-up. They can also be used with crystals when not operating close to the maximum frequency
of the device, and if frequency stability at start-up is not important for the application.
By default, the internal RC oscillator provides an 8.0MHz clock. Though voltage and temperature
dependent, this clock can be very accurately calibrated by the user. The device is shipped with the
CKDIV8 fuse programmed.
This clock may be selected as the system clock by programming the CKSEL fuses as shown in the
following table. If selected, it will operate with no external components. During reset, hardware loads the
pre-programmed calibration value into the OSCCAL register and thereby automatically calibrates the RC
Oscillator.
By changing the OSCCAL register from SW, it is possible to get a higher calibration accuracy than by
using the factory calibration.
When this oscillator is used as the chip clock, the Watchdog oscillator will still be used for the Watchdog
Timer and for the reset time-out.
The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. This clock may be
select as the system clock by programming the CKSEL Fuses to '0011':
1.The 128kHz oscillator is a very low power clock source, and is not designed for high accuracy.
When this clock source is selected, start-up times are determined by the SUT Fuses:
Table 10-12. Start-Up Times for the 128kHz Internal Oscillator
Power Conditions Start-Up Time from Power-down and Power-
save
BOD enabled6 CK14CK00
Fast rising power6 CK14CK + 4ms01
Slowly rising power 6 CK14CK + 65ms10
Reserved11
(1)
CKSEL[3:0]
Additional Delay from Reset SUT[1:0]
10.7 External Clock
To drive the device from an external clock source, EXTCLK should be driven as shown in the Figure
below. To run the device on an external clock, the CKSEL Fuses must be programmed to '0000':
Table 10-13. External Clock Frequency
Frequency
0 - 20MHz0000
Note:
1.If the cryatal frequency exceeds the specification of the device (depends on VCC), the CKDIV8
(1)
Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the
resulting divided clock meets the frequency specification of the device.
When this clock source is selected, start-up times are determined by the SUT Fuses:
Table 10-14. Start-Up Times for the External Clock Selection - SUT
ATmega324PB
Power Conditions Start-Up Time from Power-down
and Power-save
BOD enabled6 CK14CK00
Fast rising power6 CK14CK + 4ms01
Slowly rising power 6 CK14CK + 65ms10
Reserved11
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to
ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the
next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is
kept in Reset during the changes.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency
while still ensuring stable operation.
Related Links
System Clock Prescaler
Additional Delay from Reset (VCC =
5.0V)
10.8 Timer/Counter Oscillator
The device uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator.
See Low Frequency Crystal Oscillator for details on the oscillator and crystal requirements.
SUT[1:0]
On this device, the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with XTAL1 and
XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator
frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the
Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if the Enable External Clock Input bit in the
Asynchronous Status Register (ASSR.EXCLK) is written to '1'. See the description of the Asynchronous
Operation of Timer/Counter2 for further description on selecting external clock as input instead of a
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to
be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the
fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the
clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is
output.
10.10 System Clock Prescaler
The device has a system clock prescaler, and the system clock can be divided by configuring the Clock
Prescale Register (CLKPR). This feature can be used to decrease the system clock frequency and the
power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
, clk
ADC
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs
in the clock system. It also ensures that no intermediate frequency is higher than neither the clock
frequency corresponding to the previous setting, nor the clock frequency corresponding to the new
setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of
the prescaler - even if it were readable, the exact time it takes to switch from one clock division to the
other cannot be exactly predicted. From the time the Clock Prescaler Selection bits (CLKPS[3:0]) values
are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this
interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period
corresponding to the new prescaler setting.
CPU
, and clk
are divided by a factor as shown in the CLKPR description.
FLASH
ATmega324PB
,
I/O
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change
the CLKPS bits:
1.Write the Clock Prescaler Change Enable (CLKPCE) bit to '1' and all other bits in CLKPR to zero:
CLKPR=0x80.
2.Within four cycles, write the desired value to CLKPS[3:0] while writing a zero to CLKPCE:
CLKPR=0x0N
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not
interrupted.
Name: OSCCAL
Offset: 0x66
Reset: Device Specific Calibration Value
Property: -
Bit 76543210
Access
Reset xxxxxxxx
R/WR/WR/WR/WR/WR/WR/WR/W
Bits 7:0 – CAL [7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process
variations from the oscillator frequency. A pre-programmed calibration value is automatically written to
this register during chip reset, giving the Factory calibrated frequency as specified in the ClockCharacteristics section of Electrical Characteristics chapter.. The application software can write this
register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
the Clock Characteristics section of Electrical Characteristics chapter.. Calibration outside that range is
not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be
affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz.
Otherwise, the EEPROM or Flash write may fail.
CAL [7:0]
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest
frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are
overlapping, in other words a setting of OSCCAL=0x7F gives a higher frequency than OSCCAL=0x80.
The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the
lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range.
10.11.2 Clock Prescaler Register
Name: CLKPR
Offset: 0x61
Reset: Refer to the bit description
Property: -
Bit 76543210
CLKPCECLKPS [3:0]
Access
Reset 0xxxx
R/WR/WR/WR/WR/W
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is
only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by
hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within
this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.
These bits define the division factor between the selected clock source and the internal system clock.
These bits can be written run-time to vary the clock frequency to suit the application requirements. As the
divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced
when a division factor is used. The division factors are given in the table below.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the
CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a
division factor of 8 at start up. This feature should be used if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating conditions. Note that any
value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software
must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency
than the maximum frequency of the device at the present operating conditions. The device is shipped
with the CKDIV8 Fuse programmed.
The Clock Failure Detection mechanism for the device is enabled by CFD fuse in the Extended Fuse
Byte. CFD operates with 128kHz internal oscillator which will be enabled automatically when CFD is
enabled.
11.2 Features
•Detection for the failure of the low power crystal oscillator and external clocks
•Operate with 128kHz internal oscillator
•Switch the clock to internal RC oscillator clock when clock failure happens
•Failure Detection Interrupt Flag (XFDIF) available for the status of CFD
11.3 Operations
The Clock Failure Detector (CFD) allows the user to monitor the low power crystal oscillator or external
clock signal. CFD monitors XOSC clock and if it fails it will automatically switch to a safe clock. When
operating on safe clock the device will switch back to XOSC clock after Power-On or External Reset, and
continue monitoring XOSC clock for failures. The safe clock is derived from the 8MHz internal RC system
clock. This allows to configure the safe clock in order to fulfill the operative conditions of the
microcontroller.
ATmega324PB
Because the XOSC failure is monitored by the CFD circuit operating with the internal 128kHz oscillator,
the current consumption of the 128kHz oscillator will be added into the total power consumption of the
chip when CFD is enabled. CFD should be enabled only if the system clock (XOSC) frequency is above
256kHz.
Figure 11-1. System Clock Generation with CFD Mechanism
Clock Failure Detection
circuit
Low Power Crystal Oscillator
128kHz Internal Oscillator
Calibrated Internal RC Oscillator
External Clock
System
clock
XOSC CKSEL
Calibrated RC Oscillator
(CKSEL: 4'b 0010)
XOSC Failed
CKSEL
WDT 128kHz CLK
XOSC
(External CLK/
ATmega324PB
Clock Failure Detection
To start the CFD operation, the user must write a one to the CFD fuse bit in the Extended Fuse Byte
(EFB.CFD). After the start or restart of the XOSC, the CFD does not detect failure until the start-up time is
elapsed. Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored.
If the external clock is not provided, the device will automatically switch to calibrated RC oscillator output.
When the failure is detected, the failure status is asserted, i.e Failure Detection Interrupt Flag bit in the
XOSC Failure Detection Control And Status Register (XFDCSR.XFDIF) is set. The Failure Detection
interrupt flag is generated, when the Interrupt Enable bit in the XOSC Failure Detection Control And
Status Register (XFDCSR.XFDIE) is set. The XFDCSR.XFDIF reflects the current XOSC clock activity.
The detection will be automatically disabled when chip goes to power save/down sleep mode and
enabled by itself when chip enters back to active mode.
Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an
active clock. The safe clock source is the calibrated RC oscillator clock (CKSEL: 4’b0010). The clock
source can be downscaled with a configurable prescaler to ensure that the clock frequency does not
exceed the operating conditions selected by the application after switching. To use to original clock
source, user must provide a reset. When using CFD and clock failure has occurred the system operates
using 1MHz internal fallback clock. The system will try to resume to original clock source either via
Power-On-Reset (POR) or via external RESET.
The RC clock is enabled only after failure detection.
Figure 11-2. CFD mechanism timing diagram
ATmega324PB
11.5 Register Description
11.5.1 XOSC Failure Detection Control And Status Register
Name: XFDCSR
Offset: 0x62
Reset: 0x00
Property: -
Bit 76543210
Access
Reset 00
XFDIFXFDIE
RR/W
Bit 1 – XFDIF: Failure Detection Interrupt Flag
This bit is set when a failure is detected, and it can be cleared only by reset.
It serves as status bit for CFD.
Note: This bit is read only.
Bit 0 – XFDIE: Failure Detection Interrupt Enable
Setting this bit will enable the interrupt which will be issued when XFDIF is set. This bit is enable only.
Once enabled, it is not possible for the user to disable.
The following Table shows the different sleep modes, BOD disable ability and their wake-up sources.
Table 12-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock DomainsOscillatorsWake-up SourcesSoftware
clk
CPU
IdleYesYesYesYesYesYes
ADC Noise
Reduction
Power-downYes
Power-saveYesYesYes
(1)
Standby
Extended
Standby
Note:
1.Only recommended with external crystal or resonator selected as clock source.
2.If Timer/Counter2 is running in asynchronous mode.
3.For INT2, INT1 and INT0, only level interrupt.
4.Start frame detection, only.
5.Main clock is kept running if PTC is enabled.
FLASH
clkIOclk
clk
ADC
YesYesYesYesYes
clk
ASY
PTC
(2)
Yes
YesYesYes
Main Clock
Source
Enabled
YesYes
Timer
Oscillator
Enabled
(5)
Yes
INT and
PCINT
(2)
YesYesYesYesYes Yes YesYes
(2)
Yes
(2)
Yes
(2)
Yes
TWI
Address
Match
(3)
YesYes
(3)
YesYes YesYes
(3)
YesYesYes YesYes
(3)
YesYes YesYes
(3)
YesYesYes YesYes
Timer2 SPM/
EEPROM
Ready
(2)
YesYes Yes Yes
ADC WDT USART
Other
I/O
BOD
DisableSleep Modeclk
(4)
To enter any of the six sleep modes, the Sleep Enable bit in the Sleep Mode Control Register (SMCR.SE)
must be written to '1' and a SLEEP instruction must be executed. Sleep Mode Select bits
(SMCR.SM[2:0]) select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save,
Standby, or Extended Standby) will be activated by the SLEEP instruction.
Note: The block diagram in the section System Clock and Clock Options provides an overview over the
different clock systems in the device, and their distribution. This figure is helpful in selecting an
appropriate sleep mode.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then
halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes
execution from the instruction following SLEEP. The contents of the Register File and SRAM are
unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up
and executes from the Reset Vector.
Related Links
Clock Systems and Their Distribution
12.2 BOD Disable
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see also section Fuse Bits), the
BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible
to disable the BOD by software for some of the sleep modes. The sleep mode power consumption will
then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the
BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is
automatically enabled again. This ensures safe operation in case the VCC level has dropped during the
sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60μs to
ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by the BOD Sleep bit in the MCU Control Register (MCUCR.BODS). Writing
this bit to '1' turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD active. The
default setting, BODS=0, keeps BOD active.
Note: Writing to the BODS bit is controlled by a timed sequence and an enable bit.
Related Links
MCUCR
Fuse Bits
12.3 Idle Mode
When the SM[2:0] bits are written to '000', the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, USART, Analog Comparator, 2-wire Serial Interface, ADC, Timer/
Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts
clk
and clk
CPU
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator
interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the
Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle
mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
, while allowing the other clocks to run.
FLASH
ATmega324PB
Related Links
ACSR
12.4 ADC Noise Reduction Mode
When the SM[2:0] bits are written to '001', the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire Serial
Interface address watch, Timer/Counter
sleep mode basically halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC
is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion
Complete interrupt, only these events can wake up the MCU from ADC Noise Reduction mode:
•External Reset
•Watchdog System Reset
•Watchdog Interrupt
•Brown-out Reset
•2-wire Serial Interface address match
•Timer/Counter interrupt
•SPM/EEPROM ready interrupt
•External level interrupt on INT
•Pin change interrupt
I/O
, clk
(1)
, and the Watchdog to continue operating (if enabled). This
CPU
, and clk
, while allowing the other clocks to run.
FLASH
Note: 1. Timer/Counter will only keep running in asynchronous mode.
8-bit Timer/Counter2 with PWM and Asynchronous Operation
12.5 Power-Down Mode
When the SM[2:0] bits are written to '010', the SLEEP instruction makes the MCU enter Power-Down
mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial
Interface address watch, and the Watchdog continue operating (if enabled).
Only one of these events can wake up the MCU:
•External Reset
•Watchdog System Reset
•Watchdog Interrupt
•Brown-out Reset
•2-wire Serial Interface address match
•External level interrupt on INT
•Pin change interrupt
This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note: If a level triggered interrupt is used for wake-up from Power-Down, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears
before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The
start-up time is defined by the SUT and CKSEL Fuses.
ATmega324PB
When waking up from Power-Down mode, there is a delay from the wake-up condition occurs until the
wake-up becomes effective. This allows the clock to restart and become stable after having been
stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out
period.
Related Links
Clock Sources
EXINT - External Interrupts
12.6 Power-Save Mode
When the SM[2:0] bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode.
This mode is identical to Power-down, except:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer
Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt
enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.
If the PTC is enabled, the main clock is kept running.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If
Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during
sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep.
Even if the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2.
When the SM[2:0] bits are written to '110' and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-Down with the
exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock
cycles.
12.8 Extended Standby Mode
When the SM[2:0] bits are written to '111' and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-Save
mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device
wakes up in six clock cycles.
12.9 Power Reduction Registers
The Power Reduction Registers (PRR2, PRR1 and PRR0) provides a method to stop the clock to
individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the
I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will
remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
Waking up a module, which is done by clearing the corresponding bit in the PRR, puts the module in the
same state as before shutdown.
ATmega324PB
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power
consumption. In all other sleep modes, the clock is already stopped.
12.10 Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep mode
should be selected so that as few as possible of the device’s functions are operating. All functions not
needed should be disabled. In particular, the following modules may need special consideration when
trying to achieve the lowest possible power consumption.
12.10.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled
before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an
extended conversion.
Related Links
Analog-to-Digital Converter
12.10.2 Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC
Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog
Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal
Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise,
the Internal Voltage Reference will be enabled, independent of sleep mode.
If the Brown-Out Detector (BOD) is not needed by the application, this module should be turned off. If the
BOD is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always
consume power. In the deeper sleep modes, this will contribute significantly to the total current
consumption.
Related Links
System Control and Reset
12.10.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-Out Detection, the Analog
Comparator or the Analog-to-Digital Converter. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When turned on
again, the user must allow the reference to start up before the output is used. If the reference is kept on in
sleep mode, the output can be used immediately.
Related Links
System Control and Reset
12.10.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog
Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
ATmega324PB
Related Links
System Control and Reset
12.10.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most
important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock
(clk
) and the ADC clock (clk
I/O
ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is
needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Digital InputEnable and Sleep Modes for details on which pins are enabled. If the input buffer is enabled and the input
signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close
to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be
disabled by writing to the Digital Input Disable Registers (DIDR0 for ADC, DIDR1 for AC).
Related Links
Digital Input Enable and Sleep Modes
12.10.7 On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main
clock source is enabled and hence always consumes power. In the deeper sleep modes, this will
contribute significantly to the total current consumption.
) are stopped, the input buffers of the device will be disabled. This
ADC
There are three alternative ways to disable the OCD system:
The Sleep Mode Control Register contains control bits for power management.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: SMCR
Offset: 0x53
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x33
Bit 76543210
Access
Reset 0000
SM[2:0]SE
R/WR/WR/WR/W
Bits 3:1 – SM[2:0]: Sleep Mode Select
The SM[2:0] bits select between the five available sleep modes.
Table 12-2. Sleep Mode Select
SM[2:0]Sleep Mode
000Idle
001ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
111Extended Standby
(1)
(1)
Note:
1.Standby mode is only recommended for use with external crystals or resonators.
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,
it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP
instruction and to clear it immediately after waking up.
The MCU Control Register controls the placement of the Interrupt Vector table in order to move interrupts
between application and boot space.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: MCUCR
Offset: 0x55
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x35
Bit 76543210
JTDBODSBODSEPUDIVSELIVCE
Access
Reset 000000
R/WR/WR/WR/WR/WR/W
Bit 7 – JTD
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one,
the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface,
a timed sequence must be followed when changing this bit: The application software must write this bit to
the desired value twice within four cycles to change its value. Note that this bit must not be altered when
using the On-chip Debug system.
Bit 6 – BODS: BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is
controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both
BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be
written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS
is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared
after three clock cycles.
Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is
controlled by a timed sequence.
Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn
Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of
the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses.
To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to
change the IVSEL bit:
1.Write the Interrupt Vector Change Enable (IVCE) bit to one.
2.Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If
IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is
unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is
programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are
placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section.
Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware
four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as
explained in the IVSEL description above. See Code Example below.
Writing a logic one to this bit shuts down the TWI 0 by stopping the clock to the module. When waking up
the TWI again, the TWI should be re initialized to ensure proper operation.
Bit 6 – PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0).
When the Timer/Counter2 is enabled, operation will continue like before the shutdown.
Bit 5 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is
enabled, operation will continue like before the shutdown.
Bit 4 – PRUSART1: Power Reduction USART1
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking
up the USART again, the USART should be re initialized to ensure proper operation.
Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is
enabled, operation will continue like before the shutdown.
Bit 2 – PRSPI0: Power Reduction Serial Peripheral Interface 0
If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to
this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up
the SPI again, the SPI should be re initialized to ensure proper operation.
Bit 1 – PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking
up the USART again, the USART should be re initialized to ensure proper operation.
Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The
analog comparator cannot use the ADC input MUX when the ADC is shut down.
Writing a logic one to this bit shuts down the Timer/Counter4 module. When the Timer/Counter4 is
enabled, operation will continue like before the shutdown.
Bit 0 – PRTIM3: Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is
enabled, operation will continue like before the shutdown.
Name: PRR2
Offset: 0x63
Reset: 0x00
Property: -
Bit 76543210
Access
Reset 0000
PRPTCPRUSART2PRSPI1PRTWI1
R/WR/WR/WR/W
Bit 3 – PRPTC: Power Reduction PTC
Writing a logic one to this bit shuts down the PTC module. When the PTC is enabled, operation will
continue like before the shutdown.
Bit 2 – PRUSART2: Power Reduction USART2
Writing a logic one to this bit shuts down the USART2 by stopping the clock to the module. When waking
up the USART2 again, the USART2 should be re initialized to ensure proper operation.
Bit 1 – PRSPI1: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the
module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.
Bit 0 – PRTWI1: Power Reduction TWI1
Writing a logic one to this bit shuts down the TWI1 by stopping the clock to the module. When waking up
the TWI1 again, the TWI1 should be re initialized to ensure proper operation.
During reset, all I/O Registers are set to their initial values, and the program starts execution from the
Reset Vector. The instruction placed at the Reset Vector must be an Absolute Jump instruction (JMP) to
the reset handling routine for . If the program never enables an interrupt source, the Interrupt Vectors are
not used, and regular program code can be placed at these locations. This is also the case if the Reset
Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The
circuit diagram in the next section shows the reset logic.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This
does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This
allows the power to reach a stable level before normal operation starts. The time-out period of the delay
counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay
period are presented in the System Clock and Clock Options chapter.
Related Links
System Clock and Clock Options
ATmega324PB
13.2 Reset Sources
The device has the following sources of reset:
•Power-on Reset. The MCU is reset when the supply voltage is less than the Power-on Reset
threshold (V
•External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the
minimum pulse length.
•Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog System Reset mode is enabled.
•Brown-out Reset. The MCU is reset when the supply voltage VCC is less than the Brown-out Reset
threshold (V
•JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the
scan chains of the JTAG system. Refer to the section IEEE 1149.1 (JTAG) Boundary-scan for
details.
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The POR is activated
whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on
Reset threshold voltage invokes the delay counter, which determines how long the device is kept in Reset
after VCC rise. The Reset signal is activated again, without any delay, when VCC decreases below the
detection level.
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum
pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset. When the applied signal reaches the Reset Threshold Voltage (V
edge, the delay counter starts the MCU after the Time-out period (t
can be disabled by the RSTDISBL fuse.
ATmega324PB
) on its positive
RST
) has expired. The External Reset
TOUT
Figure 13-4. External Reset During Operation
13.5 Brown-out Detection
The device has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during
operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the
BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The
hysteresis on the detection level should be interpreted as V
V
/2. When the BOD is enabled, and VCC decreases to a value below the trigger level (V
HYST
following figure), the Brown-out Reset is immediately activated. When VCC increases above the trigger
level (V
expired.
in the following figure), the delay counter starts the MCU after the Time-out period t
BOT+
BOT+
= V
BOT
+ V
HYST
/2 and V
BOT-
= V
BOT-
BOT
in the
TOUT
-
has
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than
t
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling
edge of this pulse, the delay timer starts counting the Time-out period t
Figure 13-6. Watchdog System Reset During Operation
TOUT
ATmega324PB
.
13.7 Internal Voltage Reference
13.7.1 Voltage Reference Enable Signals and Start-up Time
The device features an internal bandgap reference. This reference is used for Brown-out Detection, and it
can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. To save power,
the reference is not always turned on. The reference is on during the following situations:
1.When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2.When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in
ACSR (ACSR.ACBG)).
3.When the ADC is enabled.
Thus, when the BOD is not enabled, after setting ACSR.ACBG or enabling the ADC, the user must
always allow the reference to start up before the output from the Analog Comparator or ADC is used. To
reduce power consumption in Power-Down mode, the user can avoid the three conditions above to
ensure that the reference is turned off before entering Power-Down mode.
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog
timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
Refer to Watchdog System Reset for details on how to configure the watchdog timer.
13.8.1 Features
•Clocked from separate On-chip Oscillator
•Three operating modes:
–Interrupt
–System Reset
–Interrupt and System Reset
•Selectable Time-out period from 16ms to 8s
•Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
13.8.2 Overview
The device has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate
on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a
given time-out value. In normal operation mode, it is required that the system uses the Watchdog Timer
Reset (WDR) instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
ATmega324PB
Figure 13-7. Watchdog Timer
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake
the device from sleep-modes, and also as a general system timer. One example is to limit the maximum
time allowed for certain operations, giving an interrupt when the operation has run longer than expected.
In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent
system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines
the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for
instance allow a safe shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset
mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are
locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up
must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as
follows:
1.In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and Watchdog
System Reset Enable (WDE) in Watchdog Timer Control Register (WDTCSR.WDCE and
WDTCSR.WDE). A logic one must be written to WDTCSR.WDE regardless of the previous value of
the WDTCSR.WDE.
2.Within the next four clock cycles, write the WDTCSR.WDE and Watchdog prescaler bits group
(WDTCSR.WDP) as desired, but with the WDTCSR.WDCE cleared. This must be done in one
operation.
The following examples show a function for turning off the Watchdog Timer. The
examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so
that no interrupts will occur during the execution of these functions.
Assembly Code Example
WDT_off:
; Turn off global interruptcli; Reset Watchdog Timerwdr; Clear WDRF in MCUSRin r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
; Write '1' to WDCE and WDE; Keep old prescaler setting to prevent unintentional time-outlds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDTldi r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interruptseiret
C Code Example
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE *//* Keep old prescaler setting to prevent unintentional time-out */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or
brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If
the code is not set up to handle the Watchdog, this might lead to an eternal loop of timeout resets. To avoid this situation, the application software should always clear the
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization
routine, even if the Watchdog is not in use.
The following code examples shows how to change the time-out value of the Watchdog
Timer.
Assembly Code Example
WDT_Prescaler_Change:
; Turn off global interruptcli; Reset Watchdog Timerwdr; Start timed sequencelds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; -- Got four cycles to set the new values from here -; Set new prescaler(time-out) value = 64K cycles (~0.5 s)ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCSR, r16
; -- Finished setting new values, used 2 cycles -; Turn on global interruptseiret
Note: The Watchdog Timer should be reset before any change of the WDTCSR.WDP
bits, since a change in the WDTCSR.WDP bits can result in a time-out when switching to
a shorter time-out period.
13.9 Register Description
13.9.1 MCU Status Register
To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the
MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the
source of the reset can be found by examining the Reset Flags.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: MCUSR
Offset: 0x54 [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x34
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG
instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0'
to it.
Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to it.
Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to it.
Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a '0' to it.
This bit is set when a timeout occurs in the Watchdog Timer and the Watchdog Timer is configured for
interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, WDIF is cleared by writing a '1' to it. When the I-bit in SREG and WDIE are set, the
Watchdog Timeout Interrupt is executed.
Bit 6 – WDIE: Watchdog Interrupt Enable
When this bit is written to '1' and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled.
If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the
corresponding interrupt is executed if timeout in the Watchdog Timer occurs. If WDE is set, the Watchdog
Timer is in Interrupt and System Reset Mode. The first timeout in the Watchdog Timer will set WDIF.
Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the
Watchdog goes to System Reset Mode).
This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the
interrupt service routine itself, as this might compromise the safety function of the Watchdog System
Reset mode. If the interrupt is not executed before the next timeout, a System Reset will be applied.
111Interrupt and System Reset Mode Interrupt, then go to System Reset Mode
0xxSystem Reset ModeReset
Note: 1. WDTON Fuse set to '0' means programmed and '1' means unprogrammed.
Bit 5 – WDP[3]: Watchdog Timer Prescaler 3
Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or
change the prescaler bits, WDCE must be set. Once written to '1', hardware will clear WDCE after four
clock cycles. Refer to Overview for how to use WDCE.
Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To
clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing
failure, and a safe start-up after the failure.
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The
different prescaling values and their corresponding timeout periods are shown in the following table.
Table 13-2. Watchdog Timer Prescale Select
WDP[3]WDP[2]WDP[1]WDP[0]Number of WDT Oscillator (Cycles)Oscillator
This section describes the specifics of the interrupt handling of the device. For a general explanation of
the AVR interrupt handling, refer to the description of Reset and Interrupt Handling.
In general:
•Each Interrupt Vector occupies .
•The Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is
affected by the IVSEL bit in MCUCR.
Related Links
Reset and Interrupt Handling
14.1 Interrupt Vectors in ATmega324PB
Table 14-1. Reset and Interrupt Vectors in ATmega324PB
Vector No
10x0000
Program Address
(1)
(2)
SourceInterrupts definition
RESETExternal Pin, Power-on Reset, Brown-out Reset and Watchdog System
Reset
ATmega324PB
20x0002INT0External Interrupt Request 0
30x0004INT1External Interrupt Request 1
40x0006INT2External Interrupt Request 2
50x0008PCINT0Pin Change Interrupt Request 0
60x000APCINT1Pin Change Interrupt Request 1
70x000CPCINT2Pin Change Interrupt Request 2
80x000EPCINT3Pin Change Interrupt Request 3
90x0010WDTWatchdog Time-out Interrupt
100x0012TIMER2_COMPA Timer/Counter2 Compare Match A
110x0014TIMER2_COMPB Timer/Coutner2 Compare Match B
120x0016TIMER2_OVFTimer/Counter2 Overflow
130x0018TIMER1_CAPTTimer/Counter1 Capture Event
140x001ATIMER1_COMPA Timer/Counter1 Compare Match A
150x001CTIMER1_COMPB Timer/Coutner1 Compare Match B
160x001ETIMER1_OVFTimer/Counter1 Overflow
170x0020TIMER0_COMPA Timer/Counter0 Compare Match A
180x0022TIMER0_COMPB Timer/Coutner0 Compare Match B
The table below shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used,
and regular program code can be placed at these locations. This is also the case if the Reset Vector is in
the Application section while the Interrupt Vectors are in the Boot section or vice versa.
Note: The Boot Reset Address is shown in Table Boot size configuration in Boot Loader Parameters.
For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in
the MCUCR Register is set before any interrupts are enabled, the most typical and general program
setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
0x00000 RESET: ldi r16,high(RAMEND) ; Main program start
0x00001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x00002 ldi r16,low(RAMEND)
0x00003 out SPL,r16
0x00004 sei; Enable interrupts
0x00005 <instr> xxx
When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and
general program setup for the Reset and Interrupt Vector Addresses is:
.org 0x1F000
0x1F000 RESET: ldi r16,high(RAMEND) ; Main program start
0x1F001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1F002 ldi r16,low(RAMEND)
0x1F003 out SPL,r16
0x1F004 sei; Enable interrupts
0x1F005 <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for
the Reset and Interrupt Vector Addresses is:
0x1F03E RESET: ldi r16,high(RAMEND) ; Main program start
0x1F03F out SPH,r16 ; Set Stack Pointer to top of RAM
0x1F040 ldi r16,low(RAMEND)
0x1F041 out SPL,r16
0x1F042 sei; Enable interrupts
0x1FO43 <instr> xxx
14.2 Register Description
14.2.1 Moving Interrupts Between Application and Boot Space
The MCU Control Register controls the placement of the Interrupt Vector table.
14.2.2 MCU Control Register
The MCU Control Register controls the placement of the Interrupt Vector table in order to move interrupts
between application and boot space.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
ATmega324PB
Name: MCUCR
Offset: 0x55
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x35
Bit 76543210
JTDBODSBODSEPUDIVSELIVCE
Access
Reset 000000
R/WR/WR/WR/WR/WR/W
Bit 7 – JTD
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one,
the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface,
a timed sequence must be followed when changing this bit: The application software must write this bit to
the desired value twice within four cycles to change its value. Note that this bit must not be altered when
using the On-chip Debug system.
Bit 6 – BODS: BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is
controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both
BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be
written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS
is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared
after three clock cycles.
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is
controlled by a timed sequence.
Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn
Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of
the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses.
To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to
change the IVSEL bit:
1.Write the Interrupt Vector Change Enable (IVCE) bit to one.
2.Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If
IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is
unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is
programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are
placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section.
Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware
four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as
explained in the IVSEL description above. See Code Example below.
The External Interrupts are triggered by the INT pin or any of the PCINT pins. Observe that, if enabled,
the interrupts will trigger even if the INT or PCINT pins are configured as outputs. This feature provides a
way of generating a software interrupt.
The Pin Change Interrupt Request 4 (PCI4) will trigger if any enabled PCINT[38:32] pin toggles. The Pin
Change Interrupt Request 3 (PCI3) will trigger if any enabled PCINT[31:24] pin toggles. The Pin Change
Interrupt Request 2 (PCI2) will trigger if any enabled PCINT[23:16] pin toggles. The Pin Change Interrupt
Request 1 (PCI1) will trigger if any enabled PCINT[15:8] pin toggles. The Pin Change Interrupt Request 0
(PCI0) will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK4, PCMSK3, PCMSK2, PCMSK1
and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts
on PCINT are detected asynchronously. This implies that these interrupts can be used for waking the part
also from sleep modes other than Idle mode.
The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the External Interrupt Control Register A (EICRA). When the external
interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is
held low. Note that recognition of falling or rising edge interrupts on INT requires the presence of an I/O
clock. Low level interrupt on INT is detected asynchronously. This implies that this interrupt can be used
for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep
modes except Idle mode.
ATmega324PB
Note: Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level
disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be
generated. The start-up time is defined by the SUT and CKSEL Fuses.
Related Links
System Clock and Clock Options
15.1.1 Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in the following figure.
The External Interrupt Control Register A contains control bits for interrupt sense control.
Name: EICRA
Offset: 0x69
Reset: 0x00
Property: -
Bit 76543210
Access
Reset 000000
Bits 5:4 – ISC2 [1:0]: Interrupt Sense Control 2
ISC2 [1:0]ISC1 [1:0]ISC0 [1:0]
The External Interrupt 2 is activated by the external pin INT2 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT2 pin that activate the interrupt are
defined in table below. The value on the INT2 pin is sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter
pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be
held until the completion of the currently executing instruction to generate an interrupt.
00The low level of INT2 generates an interrupt request.
01Any logical change on INT2 generates an interrupt request.
10The falling edge of INT2 generates an interrupt request.
11The rising edge of INT2 generates an interrupt request.
Bits 3:2 – ISC1 [1:0]: Interrupt Sense Control 1
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are
defined in the table below. The value on the INT1 pin is sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter
pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be
held until the completion of the currently executing instruction to generate an interrupt.
ValueDescription
00The low level of INT1 generates an interrupt request.
01Any logical change on INT1 generates an interrupt request.
10The falling edge of INT1 generates an interrupt request.
11The rising edge of INT1 generates an interrupt request.
Bits 1:0 – ISC0 [1:0]: Interrupt Sense Control 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are
defined in table below. The value on the INT0 pin is sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter
pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be
held until the completion of the currently executing instruction to generate an interrupt.
ValueDescription
00The low level of INT0 generates an interrupt request.
01Any logical change on INT0 generates an interrupt request.
10The falling edge of INT0 generates an interrupt request.
11The rising edge of INT0 generates an interrupt request.
15.1.2.2 External Interrupt Mask Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: EIMSK
Offset: 0x3D
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1D
When the INT2 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is
enabled. The Interrupt Sense Control2 bits 1/0 (ISC21 and ISC20) in the External Interrupt Control
Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the
INT2 pin or level sensed. Activity on the pin will cause an interrupt request even if INT2 is configured as
an output. The corresponding interrupt of External Interrupt Request 2 is executed from the INT2 Interrupt
Vector.
Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is
enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control
Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the
INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as
an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt
Vector.
Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is
enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control
Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the
INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as
an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt
Vector.
15.1.2.3 External Interrupt Flag Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: EIFR
Offset: 0x3C
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1C
Bit 76543210
Access
Reset 000
INTF2INTF1INTF0
R/WR/WR/W
Bit 2 – INTF2: External Interrupt Flag 2
When an edge or logic change on the INT2 pin triggers an interrupt request, INTF2 will be set. If the I-bit
in SREG and the INT2 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it. This flag is always cleared when INT2 is configured as a level interrupt.
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 will be set. If the I-bit
in SREG and the INT1 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it. This flag is always cleared when INT1 is configured as a level interrupt.
Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 will be set. If the I-bit
in SREG and the INT0 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it. This flag is always cleared when INT0 is configured as a level interrupt.
15.1.2.4 Pin Change Interrupt Control Register
Name: PCICR
Offset: 0x68
Reset: 0x00
Property: -
Bit 76543210
Access
Reset 00000
PCIE4PCIE3PCIE2PCIE1PCIE0
R/WR/WR/WR/WR/W
Bit 4 – PCIE4: Pin Change Interrupt Enable 4
When the PCIE4 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 4 is
enabled. Any change on any enabled PCINT[39:32] pin will cause an interrupt. The corresponding
interrupt of Pin Change Interrupt Request is executed from the PCI4 Interrupt Vector. PCINT[39:32] pins
are enabled individually by the PCMSK4 Register.
Bit 3 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is
enabled. Any change on any enabled PCINT[31:24] pin will cause an interrupt. The corresponding
interrupt of Pin Change Interrupt Request is executed from the PCI3 Interrupt Vector. PCINT[31:24] pins
are enabled individually by the PCMSK3 Register.
Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is
enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding
interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins
are enabled individually by the PCMSK2 Register.
Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 1 is
enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt
of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are
enabled individually by the PCMSK1 Register.
When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt
of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled
individually by the PCMSK0 Register.
15.1.2.5 Pin Change Interrupt Flag Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: PCIFR
Offset: 0x3B
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x1B
Bit 76543210
Access
Reset 00000
PCIF4PCIF3PCIF2PCIF1PCIF0
R/WR/WR/WR/WR/W
Bit 4 – PCIF4: Pin Change Interrupt Flag 4
When a logic change on any PCINT[39:32] pin triggers an interrupt request, PCIF4 will be set. If the I-bit
in SREG and the PCIE4 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
'1' to it.
Bit 3 – PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT[31:24] pin triggers an interrupt request, PCIF3 will be set. If the I-bit
in SREG and the PCIE3 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
'1' to it.
Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 will be set. If the I-bit
in SREG and the PCIE2 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
'1' to it.
Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[15:8] pin triggers an interrupt request, PCIF1 will be set. If the I-bit in
SREG and the PCIE1 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it.
Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 will be set. If the I-bit in
SREG and the PCIE0 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it.
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding
I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[15:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[15:8] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[23:16] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Each PCINT[31:24]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[31:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[31:24] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Each PCINT[38:32]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[38:32] is set and the PCIE4 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[38:32] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This
means that the direction of one port pin can be changed without unintentionally changing the direction of
any other pin with the SBI and CBI instructions. The same applies when changing drive value (if
configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer
has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong
enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a
supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as
indicated in the following figure.
Figure 16-1. I/O Pin Equivalent Schematic
ATmega324PB
All registers and bit references in this section are written in general form. A lower case “x” represents the
numbering letter for the port, and a lower case “n” represents the bit number. However, when using the
register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in
Port B, here documented generally as PORTxn.
Four I/O memory address locations are allocated for each port, one each for the Data Register – PORTx,
Data Direction Register – DDRx, Pull-up Enable Register – PUEx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/
write. However, writing '1' to a bit in the PINx Register will result in a toggle in the corresponding bit in the
Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all
pins in all ports when set.
Using the I/O port as General Digital I/O is described in next section. Most port pins are multiplexed with
alternate functions for the peripheral features on the device. How each alternate function interferes with
the port pin is described in Alternate Port Functions section in this chapter. Refer to the individual module
sections for a full description of the alternate functions.
Enabling the alternate function of some of the port pins does not affect the use of the other pins in the
port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows the
functional description of one I/O-port pin, here generically called Pxn.
Figure 16-2. General Digital I/O
ATmega324PB
(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
16.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in the Register
Description, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O
address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written to '1', Pxn is
configured as an output pin. If DDxn is written to '0', Pxn is configured as an input pin.
If PORTxn is written to '1' when the pin is configured as an input pin, the pull-up resistor is activated. To
switch the pull-up resistor off, PORTxn has to be written to '0' or the pin has to be configured as an output
pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written to '1' when the pin is configured as an output pin, the port pin is driven high. If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low.
Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI
instruction can be used to toggle one single bit in a port.
16.2.3 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11),
an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn,
PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a highimpedance environment will not notice the difference between a strong high driver and a pull-up. If this is
not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use
either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an
intermediate step.
The following table summarizes the control signals for the pin value.
Table 16-1. Port Pin Configurations
ATmega324PB
DDxnPORTxnPUD
I/OPull-upComment
(in MCUCR)
00XInputNoTri-state (Hi-Z)
010InputYesPxn will source current if ext. pulled low
011InputNoTri-state (Hi-Z)
10XOutputNoOutput Low (Sink)
11XOutputNoOutput High (Source)
16.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn
Register bit. As shown in Ports as General Digital I/O, the PINxn Register bit and the preceding latch
constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the
edge of the internal clock, but it also introduces a delay. The following figure shows a timing diagram of
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted t
pd,max
and t
respectively.
pd,min
Figure 16-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is
closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded
region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is
clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows
tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the
following figure. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In
this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 16-4. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port
pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read
back again, but as previously discussed, a nop instruction is included to be able to read back the value
recently assigned to some of the pins.
Assembly Code Example
...
; Define pull-ups and set outputs high; Define directions for port pinsldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronizationnop; Read port pinsin r16,PINB
...
(1)
Note: 1. For the assembly program, two temporary registers are used to minimize the
time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,
defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
As shown in the figure of General Digital I/O, the digital input signal can be clamped to ground at the input
of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode and Standby mode to avoid high power consumption if some input signals are left
floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not
enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate
functions as described in Alternate Port Functions section in this chapter.
If a logic high level is present on an asynchronous external interrupt pin configured as “Interrupt on Rising
Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the
corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode,
as the clamping in these sleep mode produces the requested logic change.
16.2.6 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though
most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should
be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset,
Active mode and Idle mode).
ATmega324PB
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this
case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is
recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is
not recommended, since this may cause excessive currents if the pin is accidentally configured as an
output.
16.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. The following figure
shows how the port pin control signals from the simplified Figure 16-2 can be overridden by alternate
functions. The overriding signals may not be present in all port pins, but the figure serves as a generic
description applicable to all port pins in the AVR microcontroller family.
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn:DIGITAL INPUT PIN n ON PORTx
AIOxn:ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
Q D
CLR
Q
Q D
CLR
Q
QD
CLR
PINxn
PORTxn
DDxn
DATA BUS
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:SLEEP CONTROL
Pxn
I/O
0
1
WPx:WRITE PINx
WPx
ATmega324PB
Figure 16-5. Alternate Port Functions
(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
The following table summarizes the function of the overriding signals. The pin and port indexes from
previous figure are not shown in the succeeding tables. The overriding signals are generated internally in
Table 16-2. Generic Description of Overriding Signals for Alternate Functions
ATmega324PB
Signal
Name
PUOEPull-up Override
PUOVPull-up Override
DDOEData Direction
DDOVData Direction
PVOEPort Value
PVOVPort Value
DIEOEDigital Input
DIEOVDigital Input
Full NameDescription
Enable
Value
Override Enable
Override Value
Override Enable
Override Value
Enable Override
Enable
Enable Override
Value
If this signal is set, the pull-up enable is controlled by the PUOV signal. If this
signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared,
regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If
this signal is cleared, the Output driver is enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared,
regardless of the setting of the DDxn Register bit.
If this signal is set and the Output Driver is enabled, the port value is controlled
by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the
port Value is controlled by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the setting of the
PORTxn Register bit.
If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this
signal is cleared, the Digital Input Enable is determined by MCU state (Normal
mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared,
regardless of the MCU state (Normal mode, sleep mode).
DIDigital InputThis is the Digital Input to alternate functions. In the figure, the signal is
connected to the output of the Schmitt Trigger but before the synchronizer.
Unless the Digital Input is used as a clock source, the module with the alternate
function will use its own synchronizer.
AIOAnalog Input/
Output
The following subsections shortly describe the alternate functions for each port, and relate the overriding
signals to the alternate function. Refer to the alternate function description for further details.
16.3.1 Alternate Functions of Port A
The Port A pins with alternate functions are shown in the table below:
Table 16-3. Port A Pins Alternate Functions
Port PinAlternate Functions
PA7
PA6
This is the Analog Input/output to/from alternate functions. The signal is
connected directly to the pad, and can be used bi-directionally.
•ADC[7:0]/PCINT[7:0] – Port A, Bit [7:0]
–ADC[7:0]: Analog to Digital Converter Channels [7:0].
–PCINT[7:0]: Pin Change Interrupt source [7:0]. The PA[7:0] pins can serve as external
interrupt sources.
Table 16-4. Overriding Signals for Alternate Functions in PA7...PA4
•SCK0/OC3B/OC4B/PCINT15 – Port B, Bit 7
–SCK0: Master Clock output, Slave Clock input pin for SPI0 channel. When the SPI0 is
enabled as a slave, this pin is configured as an input regardless of the setting of DDRB7.
When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDRB7.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit.
–OC3B: Output Compare Match B output. The PB7 pin can serve as an external output for the
Timer/Counter3 Output Compare. The pin has to be configured as an output (DDRB7 set “1”)
to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.
–OC4B: Output Compare Match B output. The PB7 pin can serve as an external output for the
Timer/Counter4 Output Compare. The pin has to be configured as an output (DDRB7 set “1”)
to serve this function. The OC4B pin is also the output pin for the PWM mode timer function.
–PCINT15: Pin Change Interrupt source 15. The PB7 pin can serve as an external interrupt
source.
•MISO0/OC3A/PCINT14 – Port B, Bit 6
–MISO0: Master Data input, Slave Data output pin for SPI0 channel. When the SPI0 is enabled
as a master, this pin is configured as an input regardless of the setting of DDRB6. When the
SPI0 is enabled as a slave, the data direction of this pin is controlled by DDRB6. When the
pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit.
–OC3A: Output Compare Match A output. The PB6 pin can serve as an external output for the
Timer/Counter3 Output Compare. The pin has to be configured as an output (DDRB6 set “1”)
to serve this function. The OC3A pin is also the output pin for the PWM mode timer function.
–PCINT14: Pin Change Interrupt source 14. The PB6 pin can serve as an external interrupt
source.
ATmega324PB
•MOSI0/ICP3/PCINT13 – Port B, Bit 5
–MOSI0: SPI0 Master Data output, Slave Data input for SPI0 channel. When the SPI0 is
enabled as a slave, this pin is configured as an input regardless of the setting of DDRB5.
When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDRB5.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit.
–ICP3: Input Capture Pin 3. The PB5 pin can act as an input capture pin for Timer/Counter3.
–PCINT13: Pin Change Interrupt source 13. The PB5 pin can serve as an external interrupt
•SS0/OC0B/PCINT12 – Port B, Bit 4
–SS0: Slave Port Select input. When the SPI0 is enabled as a slave, this pin is configured as
an input regardless of the setting of DDRB4. As a slave, the SPI0 is activated when this pin is
driven low. When the SPI0 is enabled as a master, the data direction of this pin is controlled
by DDRB4. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB4 bit.
–OC0B: Output Compare Match B output. The PB4 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDRB4 set “1”)
to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
–PCINT12: Pin Change Interrupt source 12. The PB4 pin can serve as an external interrupt
source.
•AIN1/OC0A/PCINT11– Port B, Bit 3
–AIN1: Analog Comparator Negative input. This pin is directly connected to the negative input
of the Analog Comparator.
–OC0A: Output Compare Match A output. The PB3 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDRB3 set “1”)
to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.
–PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt
source.
•AIN0/INT2/PCINT10 – Port B, Bit 2
–AIN0: Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
–INT2: External Interrupt source 2. The PB2 pin can serve as an External Interrupt source to
the MCU.
–PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt
source.
•T1/CLKO/PCINT9 – Port B, Bit 1
–T1: Timer/Counter1 counter source.
–CLKO: Divided System Clock: The divided system clock can be output on the PB1 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB1 and DDRB1 settings. It will also be output during reset.
–PCINT9: Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt
source.
•T0/XCK0/PCINT8 – Port B, Bit 0
–T0: Timer/Counter0 counter source.
–XCK0: USART0 External clock. The Data Direction Register (DDRB0) controls whether the
clock is output (DDRB0 set “1”) or input (DDRB0 cleared). The XCK0 pin is active only when
the USART0 operates in Synchronous mode.
–PCINT8: Pin Change Interrupt source 8. The PB0 pin can serve as an external interrupt
source.
Table 16-7 and Table 16-8 relate the alternate functions of Port B to the overriding signals shown in
Figure 16-5. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is
•TDI/PCINT21 – Port C, Bit 5
–TDI: JTAG Test Data Input
–PCINT21: Pin Change Interrupt source 21. The PC5 pin can serve as an external interrupt
source.
•OC4A/TDO/PCINT20 – Port C, Bit 4
–OC4A: Timer/Counter 4 Output Compare Match A Output
–TDO: JTAG Test Data Output
–PCINT20: Pin Change Interrupt source 20. The PC4 pin can serve as an external interrupt
source.
•TMS/ICP4/PCINT19 – Port C, Bit 3
–TMS: JTAG Test Mode Select
–ICP4: Timer/Counter4 Input Capture Trigger
–PCINT19: Pin Change Interrupt source 19. The PC3 pin can serve as an external interrupt
source.
•TCK/T4/PCINT18 – Port C, Bit 2
–TCK: JTAG Test Clock
–T4: Timer/Counter 4 External Counter Input
–PCINT18: Pin Change Interrupt source 18. The PC2 pin can serve as an external interrupt
source.
•SDA0/PCINT17 – Port C, Bit 1
–SDA0: two-wire Serial Bus0 Data Input/Output Line
–PCINT17: Pin Change Interrupt source 17. The PC1 pin can serve as an external interrupt
source.
•SCL0/PCINT16 – Port C, Bit 0
–SCL0: two-wire Serial Bus0 Clock Line
–PCINT16: Pin Change Interrupt source 16. The PC0 pin can serve as an external interrupt
source.
The tables below relate the alternate functions of Port C to the overriding signals shown in Figure 16-5.
Table 16-10. Overriding Signals for Alternate Functions in PC7...PC4