Datasheet ATF22V10CZ-15XI, ATF22V10CZ-15XC, ATF22V10CZ-15SI, ATF22V10CZ-15SC, ATF22V10CZ-15PI Datasheet (ATMEL)
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Features
Industry Standard Architecture
•
12 ns Maximum Pin-to-Pin Del ay
•
Zero Power - 25 µA Maximum Standby Pow e r
•
CMOS and TTL Compatible Inputs and Outputs
•
Advanced Electrically Erasable Technology
•
Reprogrammable
100% Tested
Latch Feature Holds Inputs to Previous Logic State
•
High Reliability CMOS Process
•
20 Year Data Retention
100 Erase/Write Cyc le s
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
•
Dual-in-Line and Surface Mount Packages in Standard Pinouts
•
Block Diagram
High
Performance
2
E
PLD
ATF22V10CZ
Preliminary
Description
The ATF22V10CZ is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 12 ns with zero standby power dissipation are offered. All speed ranges are specified over the full 5V ±10% range for industrial temperature ranges; 5V ± 5% for commercial range 5-volt devices.
Pin Configurations
Pin Name Function
CLK Clock
IN Logic Inputs
I/O Bidirectional Buffers
VCC +5V Supply
DIP/SOIC
PLCC Top View
(1)
TSSOP Top View
1
CLK/IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
IN
9
IN
10
IN
11
IN
12
GND
24
VCC
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
IN
ATF22V10CZ
Note: 1. For PLCC, P1, P8, P15 and P22 can be left un con-
nected. Connect V
to pin 1 and GND to 8, 15, and
CC
22.
Rev. 0778B/V10CZ-B–04/98
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The ATF22V10CZ provides a “zero” power CMOS PLD
solution with 5V operating voltages. The ATF22V10CZ
powers down automatically to th e zero power mode
through Atmel’s patented Input Transition Detection (ITD)
circuitry when the device is idle. The ATF22V10CZ has
an edge-sensing power down feature, offering “zero” (25
µA worst case) standby power. This feature allows the
user to manage total system power to meet specific application requirements and enhance reliability. Pin “ keeper”
Absolute Maximum Ratings*
circuits on input and output pins eliminate static power
consumed by pull-up resistors.
The ATF22V10CZ incorporates a superset of the generic
architectu res, which allows direc t replacement of the
22V10 family and most 24-pin combinatorial PLDs. Ten
outputs are each allocated 8 to 16 product terms. Three
different modes of operation, configured automatically
with software, allow highly complex logic functions to be
realized.
Temperature Under Bias...................-40°C to +85°C
Storage Temperature......................-65°C to +150°C
Voltage on Any Pin with
Respect to Ground.........................-2.0V to +7.0V
(1)
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or an y ot he r con ditions beyond those indicated in the oper ational secti ons of this specification is not
implied. Exposure to absolute maxi mum rating conditions
for extended periods may affect device reliability.
Voltage on Input Pins
with Respect to Ground
During Programming....................-2.0V to +14.0V
Programming Voltage with
Respect to Ground.......................-2.0V to +14.0V
(1)
(1)
Note: 1. Minimum voltage is -0.6V dc, which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Case) 0°C - 70°C -40°C - 85°C
V
Power Supply 5V ± 5% 5V ± 10%
CC
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ATF22V10CZ
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Functional Logic Diagram Description
The Functional Logic Diagram describes the
ATF22V10CZ architecture.
The ATF22V10CZ has 12 inputs and 10 I/O macrocells.
Each macrocell can be configured into one of four output
configurations: active high/low, registered/combinatorial
output. The universal architecture of the ATF22V10CZ
can be programmed to emulate most 24-pin PAL devices.
DC Characteristics
ATF22V10CZ
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security
Fuse, when programmed, protects the contents of the
ATF22V10CZ. Eight bytes (64 fuses) of User Signature
are accessible to the user for purposes such as storing
project nam e, part number, revision or date. The User
Signature is accessible regardless of the state of the Security Fuse.
Symbol Parameter Condition Min Typ Max Units
I
IL
I
IH
I
CC
I
SB
I
OS
V
IL
V
IH
V
OL
V
OH
Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input or I/O Low
Leakage Current
Input or I/O High
Leakage Current
Clocked Power
Supply Current
Power Supply Current,
Standby
Output Short Circuit
(1)
Current
0 ≤ V
3.5 ≤ V
V
Outputs Open,
f = 15 MHz
V
V
Outputs Open
V
≤ VIL(max) -10 µA
IN
≤ V
IN
CC
= MAX,
CC
= MAX,
CC
= MAX,
IN
= 0.5V -150 mA
OUT
Com.
Ind.
Com.
Ind.
90
90
5
5
150
180
Input Low Voltage -0.5 0.8 V
Input High Voltage 2.0 VCC + 0.75 V
= VIH or V
V
Output Low Voltage
Output High Voltage
IN
VCC = MIN,
I
= 16 mA
OL
= VIH or VIL,
V
IN
V
= MIN,
CC
I
= -4.0 mA
OH
IL
Com.
Ind.
2.4 V
10 µA
25
50
0.5 V
mA
mA
µA
µA
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AC Waveforms
AC Characteristics
(1)
-12 -15
Symbol Parameter
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
Input to Feedback to Non-Registered Output 3 12 3 15 ns
Clock to Feedback 6 4.5 ns
Clock to Output 2 8 2 8 ns
Input or Feedback Setup Time 10 10 ns
Input Hold Time 0 0 ns
Clock Period 12 12 ns
Clock Width 6 6 ns
External Feedback 1/(tS + tCO)
F
MAX
Internal Feedback 1/(t
No Feedback 1/(t
t
EA
t
ER
t
PZX
t
PXZ
t
AP
t
SP
t
AW
t
AR
t
SPR
Input to Output Enable - Product Term 3 12 3 15 ns
Input to Output Disable - Product Term 2 15 3 15 ns
OE Pin to Output Enable 2 12 2 15 ns
OE Pin to Output Disable 2 15 2 15 ns
Input or I/O to Asynchronous Reset of Register 3 10 3 15 ns
Setup Time, Synchronous Preset 10 10 ns
Asynchronous Reset Width 7 8 ns
Asynchronous Reset Recovery Time 5 6 ns
Synchronous Preset to Clock Recovery Time 10 10 ns
+ tCF)
S
)
P
Min Max Min Max
55.5
62
83.3
55.5
69
83.3
Units
MHz
MHz
MHz
Note: 1. See ordering in fo rma ti on for valid part numb ers .
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ATF22V10CZ
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ATF22V10CZ
Input Test Waveforms and
Measurement Levels
Pin Capacitance (f = 1 MHz, T = 25°C)
Output Test Loads
Note: Similar competitors’ devices are specified
with slightly different loads. These load differences may affect output signals’ delay and slew
rate. Atmel devices are tested with sufficient
margins to meet compatible device specification
conditions.
(1)
Typ Max Units Conditions
C
IN
C
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
58pFV
68pFV
= 0V
IN
OUT
= 0V
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Power Up Reset
The registers in the ATF22V10CZ are designed to reset
during power up. At a point delayed slight ly from V
crossing V
, all registers will be reset to the low state.
RST
The output state will depend on the polarity of the buffer.
This feat ure is critical for s tate machine initialization.
However, due to the asynchronous nature of reset and the
uncertainty of how V
actually rises in the system, the
CC
following conditions are required:
1. The V
2. The clock must remain stable during T
rise must be monotonic and start below 0.7V.
CC
PR.
3. After TPR occurs, all input and feedback setup times
must be met before driving the clock pin high.
CC
file preload sequence will be done automatically by most
of the approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF22V10CZ fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit
User Signature remains accessible. The security fuse
should be programmed last, as its effect is immediate.
Preload of Register Outputs
The ATF22V10CZ’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any st ate can be
forced into the registers to control test sequencing. A
Programming/Erasing
Programmin g/erasing is performed using standard PLD
programmers. See CMOS PLD Programming Hardware
& Software Support for information on software/programming.
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC
V
R
ST
POWER
t
PR
REGISTERED
OUTP UTS
C
LOCK
t
S
t
W
Parameter Description Typ Max Units
T
V
PR
RST
Power-Up
Reset Time
Power-Up
Reset Voltage
600 1,000 ns
3.8 4.5 V
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ATF22V10CZ
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Input and I/O Pull-Ups
All ATF22V10CZ family members have internal input and
I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their
last driven state. This ensures that all logic array inputs
Input Diagram
ATF22V10CZ
and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by
TTL-compatible drivers (see input and I/O diagrams below).
I/O Diagram
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Functional Logic Diagram ATF22V10CZ
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ATF22V10CZ
Page 9
ATF22V10CZ
t
PD
(ns)
12 10 8 ATF22V10CZ-12JC 28J Commercial
15 4.5 8 ATF22V10CZ-15JC 28J Commercial
t
S
(ns)
4.5 8 ATF22V10CZ-15JI 28J Industrial
t
CO
(ns)
Ordering Code Package Operation Range
ATF22V10CZ-12PC 24P3 (0°C to 70°C)
ATF22V10CZ-12SC 24S
ATF22V10CZ-12XC 24X
ATF22V10CZ-15PC 24P3 (0°C to 70°C)
ATF22V10CZ-15SC 24S
ATF22V10CZ-15XC 24X
ATF22V10CZ-15PI 24P3 (-40°C to +85°C)
ATF22V10CZ-15SI 24S
ATF22V10CZ-15XI 24X
28J
24P3
24S
24X
Package Type
28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP)
24-Lead, 0.300" Wid e, Plastic Gull WIng Smal l O ut li ne (SOI C)
24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
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