Datasheet ATF22LV10CZ-25XI, ATF22LV10CZ-25XC, ATF22LV10CZ-25SI, ATF22LV10CZ-25SC, ATF22LV10CZ-25PI Datasheet (ATMEL)
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Features
3.0V to 5.5V Operating Ra ng e
•
Advanced Low Voltage, Zero Power,
•
Electrically Erasable Programmable Logic Device
Edge-Sensing “Zero” Power
•
Low Voltage Equivalent of ATF22V10CZ
•
“Zero” Standby Power (25 µA Maximum)
•
Ideal for Battery Powered Systems
•
25 ns Maximum Propag ation Delay
•
CMOS and TTL Compatible Inputs and Outputs
•
Latch Feature Hold Inputs to Previous Logic States
•
Advanced E2 Technology
•
Reprogrammable
100% Tested
High Reliability CMOS Process
•
20 Year Data Retention
100 Erase/Write Cyc le s
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
•
Dual-in-Line and Surface Mount Standard Pinouts
•
Block Diagram
High
Performance
2
E
PLD
ATF22LV10CZ
Pin Configurations
Pin Name Function
CLK Clock
IN Logic Inputs
I/O Bidirectional Buffers
V
CC
(3 to 5.5V) Supply
DIP/SOIC
CLK/IN
GND
PLCC
TSSOP Top View
1
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
IN
9
IN
10
IN
11
IN
12
Top view
Note: For PLCC, pi ns 1 , 8, 15, and 22 ca n be l ef t unconnected. Fo r s up erior performance, connect V
to pin 1 and GND to pins 8, 15 , an d 22 .
CC
ATF22LV10CZ
24
VCC
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
IN
Rev. 0779E/LV10CZ-E–05/98
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Description
The ATF22LV10CZ is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which
utilizes Atmel’s proven electrically erasable Flash memory technology and provides 25 ns speed with stand-by
current of 25 µA maximum. All speed ranges are specified
over the 3.0V to 5.5V range for industrial and commercial
temperature ranges.
The ATF22LV10CZ provides a low voltage and edgesensing “zero” power CMOS PLD solution with “zero”
standby power (5 µA typical). The ATF22LV10CZ powers
down automatically to the zero power mode through Atmel’s patented Input Transition Detection (ITD) circuitry
when the device is idle. The ATF22LV10CZ is capable of
Absolute Maximum Ratings*
operating at supply voltages down to 3.0V. Pin “keeper”
circuits on input and output pins hold pins to their previous
logic levels when idle, which eliminate static power consumed by pull-up resistors.
The ATF22LV10CZ mac rocell incorporates a variable
product term architecture. Each output is allocated from 8
to 16 product terms whic h allows highly complex logic
functions to be realized. Two additional product terms are
included to provide synchronous reset and asynchronous
reset. These additional product terms are common to all
10 registers and are automatically cleared upon power up.
Register Preload simplifies testing. A Security Fuse prevents unauthorized copying of programmed fuse patterns.
Temperature Under Bias...................-40°C to +85°C
Storage Temperature......................-65°C to +150°C
Voltage on Any Pin with
Respect to Ground.........................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming....................-2.0V to +14.0V
Programming Voltage with
Respect to Ground.......................-2.0V to +14.0V
(1)
(1)
(1)
*NOTICE: Stresses beyond those listed under “ Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or an y ot he r con ditions beyond tho se ind icated in the oper ational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note: 1. Minimum voltage is -0.6V dc, which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Case) 0°C - 70°C -40°C - 85°C
V
Power Supply 3.0V - 5.5V 3.0V - 5.5V
CC
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ATF22LV10CZ
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ATF22LV10CZ
Functional Logic Diagram Description
The Functional Logic Diagram describes the
ATF22LV10CZ architecture.
The ATF22LV10CZ has 12 inputs and 10 I/O macrocells.
Each macrocell can be configured into one of four output
configurations: active-high/low or registered/combinatorial. The universal architecture of the ATF22LV10CZ can
be programmed to emulate most 24-pin PAL devices.
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
I
I
I
I
V
V
V
V
IL
IH
CC
SB
OS
IL
IH
OL
OH
Input or I/O Low
Leakage Current
Input or I/O High
Leakage Current
Clocked Power
Supply Current
Power Supply Current,
Standby
Output Short Circuit
(1)
Current
0 ≤ V
V
≤ VIL(MAX) -10 µA
IN
- 0.7V ≤ VIN ≤ V
CC
VCC = MAX,
Outputs Open, f = 15 MHz
VCC = MAX,
V
= MAX, Outputs Open
IN
V
= 0.5V -130 mA
OUT
Input Low Voltage -0.5 0.8 V
Input High Voltage 2.0 VCC + 0.75 V
= VIH or V
V
Output Low Voltage
Output High Voltage
IN
VCC = MIN,
I
= 8 mA
OL
= VIH or VIL,
V
IN
V
= MIN,
CC
I
= -4.0 mA
OH
IL
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security
Fuse, when programmed, protects the contents of the
ATF22LV10CZ. Eight bytes (64 fuses) of User S ignature
are accessible to the user for purposes such as storing
project nam e, part number, revision or date. The User
Signature is accessible regardless of the state of the Security Fuse.
CC
10 µA
Com. 55 85 mA
Ind. 60 90 mA
Com. 5 25 µA
Ind. 5 50 µA
Com.
0.5 V
Ind.
2.4 V
Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
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AC Waveforms
INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET
ASYNCH. RESET
CP
tS
tH
tW tW
tP
tAW
tAR
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
AC Characteristics
tAPtCO
VALID
tPD
VALID VALID
(1)
tER tEA
VALID VALID
OUTPUT
DISABLED
tEAtER
OUTPUT
DISABLED
-25
Symbol Parameter
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
Input to Feedback to Non-Registered Output 3 25 ns
Clock to Feedback 13 ns
Clock to Output 2 15 ns
Input or Feedback Setup Time 15 ns
Input Hold Time 0 ns
Clock Period 25 ns
Clock Width 12.5 ns
External Feedback 1/(tS + tCO)
F
MAX
Internal Feedback 1/(t
No Feedback 1/(t
t
EA
t
Input to Output Disable 3 25 ns
ER
t
AP
t
SP
t
AW
t
AR
t
SPR
Input to Output Enable 3 25 ns
Input or I/O to Asynchronous Reset of Register 3 25 ns
Setup Time, Synchronous Preset 15 ns
Asynchronous Reset Width 25 ns
Asynchronous Reset Recovery Time 25 ns
Synchronous Preset to Clock Recovery Time 15 ns
+ tCF)
S
)
P
Min Max
33.3
35.7
40.0
VALID
Units
MHz
MHz
MHz
Note: 1. See ordering informa tion for valid part numb ers .
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ATF22LV10CZ
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ATF22LV10CZ
Input Test Waveforms and
Measurement Levels
Pin Capacitance
C
IN
(f = 1 MHz, T = 25°C)
Output Test Loads
Note: Similar competitors’ devices are specified
with slightly different loads. These load differences may affect output signals’ delay and slew
rate. Atmel devices are tested with sufficient
margins to meet compatible device specification
conditions.
(1)
Typ Max Units Conditions
58pFV
IN
= 0V
C
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
68pFV
OUT
= 0V
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Power Up Reset
The registers in the ATF22LV10CZ are designed to reset
during power up. At a point delayed slightly from V
crossing V
The output state will depend on the polarity of the buffer.
This feat ure is critical for s tate machine initialization.
However, due to the asynchronous nature of reset and the
uncertainty of how V
following conditions are required:
1. The V
3. The clock must remain stable during T
2. After T
met before driving the clock pin high.
, all registers will be reset to the low state.
RST
actually rises in the system, the
CC
rise must be monotonic and start below 0.7V
CC
.
PR
, all input and feedback setup times must be
PR
CC
Preload of Register Outputs
The ATF22LV10CZ’s registers are provided with circuitry
to allow loading of each register with either a high or a low.
This feature will simplify testing since any st ate can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most
of the approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF22LV10CZ fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit
User Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programmin g/erasing is performed using standard PLD
programmers. See CMOS PLD Programming Hardware
& Software Support for information on software/programming.
Parameter Description Typ Max Units
T
V
PR
RST
Power-Up
Reset Time
Power-Up
Reset Voltage
600 1,000 ns
2.3 2.7 V
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ATF22LV10CZ
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Input and I/O Pin Keepers
All ATF22LV10CZ family members have internal input and
I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their
last driven state. This ensures that all logic array inputs
Input Diagram
ATF22LV10CZ
and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by
TTL-compatible drivers (see input and I/O diagrams below).
I/O Diagram
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Functional Logic Diagram ATF22LV10CZ
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ATF22LV10CZ
Page 9
ATF22LV10CZ
t
PD
(ns)
25 15 15 ATF22LV10CZ-25JC 28J Commercial
t
S
(ns)
15 15 ATF22LV10CZ-25JI 28J Industrial
t
CO
(ns)
Ordering Code Package Operation Range
ATF22LV10CZ-25PC 24P3 (0°C to 70°C)
ATF22LV10CZ-25SC 24S
ATF22LV10CZ-25XC 24X
ATF22LV10CZ-25PI 24P3 (-40°C to +85°C)
ATF22LV10CZ-25SI 24S
ATF22LV10CZ-25XI 24X
28J
24P3
24S
24X
Package Type
28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP)
24-Lead, 0.300" Wid e, Plastic Gull WIng Smal l Out li ne (SOI C )
24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
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