NDA. For more information, please
contact your local Microchip sales
office.
ATECC608B
CryptoAuthentication™ Device Summary Data Sheet
Features
• Cryptographic Co-Processor with Secure Hardware-Based Key Storage:
– Protected storage for up to 16 keys, certificates or data
• Hardware Support for Asymmetric Sign, Verify, Key Agreement:
– ECDSA: FIPS186-3 Elliptic Curve Digital Signature
– ECDH: FIPS SP800-56A Elliptic Curve Diffie-Hellman
– NIST Standard P256 Elliptic Curve Support
• Hardware Support for Symmetric Algorithms:
– SHA-256 & HMAC Hash including off-chip context save/restore
– AES-128: Encrypt/Decrypt, Galois Field Multiply for GCM
• Networking Key Management Support:
– Turnkey PRF/HKDF calculation for TLS 1.2 & 1.3
– Ephemeral key generation and key agreement in SRAM
– Small message encryption with keys entirely protected
• Secure Boot Support:
– Full ECDSA code signature validation, optional stored digest/signature
– Optional communication key disablement prior to secure boot
– Encryption/Authentication for messages to prevent on-board attacks
• Internal High-Quality NIST SP 800-90A/B/C Random Number Generator (RNG)
• Two High-Endurance Monotonic Counters
• Unique 72-Bit Serial Number
• Two Interface Options Available:
– High-Speed Single Wire Interface with One GPIO Pin
– 1 MHz Standard I2C Interface
• 1.8V to 5.5V IO Levels, 2.0V to 5.5V Supply Voltage
• Two Temperature Ranges Available:
– Standard Industrial Temperature Range: -40℃ to +85℃
– Extended Industrial Temperature Range: -40℃ to +100℃
• <150 nA Sleep Current
• Packaging Options
– 8-pad UDFN, 8-lead SOIC and 3-Lead Contact Package Options
– Die-on-Tape and Reel and WLCSP for Qualified Customers (Contact Microchip Sales)
The Microchip Website.................................................................................................................................24
The ATECC608B is a member of the Microchip CryptoAuthentication™ family of high-security cryptographic devices,
which combine world-class, hardware-based key storage with hardware cryptographic accelerators to implement
various authentication and encryption protocols.
The ATECC608B provides security enhancements over that of the ATECC608A, while providing complete backwards
compatibility. All configuration settings, commands, packages and functionality of the ATECC608A are still available
in the ATECC608B, making migration from the ATECC608A a simple process. For new designs, it is recommended
that customers start directly with the ATECC608B device. For designs that are being upgraded and currently use the
ATECC508A or the ATECC608A, it is recommended that they move to the ATECC608B. For designs not planned to
be upgraded, it is recommended that customers review their designs to see if they would benefit from the enhanced
security of the ATECC608B. For assistance with migrating a design to the ATECC608B, see the Migrations
References section.
For more information on compatibility with other Microchip CryptoAuthentication products, please see Section 3.
Compatibility.
Migration References:
1.AN3539: Provides guidance on migrating from the ATECC508A to the ATECC608B
2.AN2237: Provides guidance on migrating from the ATECC608A to the ATECC608B
ATECC608B
Introduction
1.1 Applications
The ATECC608B has a flexible command set that allows use in many applications, including the following:
• Network/IoT Node Endpoint Security
Manages node identity authentication and session key creation and management. Supports the entire
ephemeral session key-generation flow for multiple protocols, including TLS 1.2 (and earlier) and TLS 1.3.
• Secure Boot
Supports the MCU host by validating code digests and optionally enabling communication keys on success.
Various configurations to offer enhanced performance are available.
• Small Message Encryption
Contains a hardware AES engine to encrypt and/or decrypt small messages or data such as PII information.
Supports the AES-ECB mode directly. Other modes can be implemented with the help of the host
microcontroller. There is an additional GFM calculation function to support AES-GCM.
• Key Generation for Software Download
Supports local protected key generation for downloaded images. Both broadcast of one image to many systems,
each with the same decryption key, or point-to-point download of unique images per system are supported.
• Ecosystem Control and Anti-Counterfeiting
Validates that a system or component is authentic and came from the OEM shown on the nameplate.
1.2 Device Features
The ATECC608B includes an EEPROM array which can be used for storage of up to 16 keys, certificates,
miscellaneous read/write, read-only or secret data, consumption logging and security configurations. Access to the
various sections of memory can be restricted in a variety of ways and then the configuration can be locked to prevent
changes.
Access to the device is made through a standard I2C Interface at speeds of up to 1 Mbps. The interface is compatible
with standard Serial EEPROM I2C interface specifications. The device also supports a Single-Wire Interface (SWI),
which can reduce the number of GPIOs required on the system processor, and/or reduce the number of pins on
connectors. If the Single-Wire Interface is enabled, the remaining pin is available for use as a GPIO, an authenticated
output or tamper input.
Each ATECC608B ships with an ensured unique 72-bit serial number. Using the cryptographic protocols supported
by the device, a host system or remote server can verify a signature of the serial number to prove that the serial
number is authentic and not a copy. Serial numbers are often stored in a standard Serial EEPROM; however, these
can be easily copied with no way for the host to know if the serial number is authentic or if it is a clone.
The ATECC608B features a wide array of defense mechanisms specifically designed to prevent physical attacks on
the device itself, or logical attacks on the data transmitted between the device and the system. Hardware restrictions
on the ways in which keys are used or generated provide further defense against certain styles of attack.
1.3 Cryptographic Operation
The ATECC608B implements a complete asymmetric (public/private) key cryptographic signature solution based
upon Elliptic Curve Cryptography and the ECDSA signature protocol. The device features hardware acceleration for
the NIST standard P256 prime curve and supports the complete key life cycle from high quality private key
generation, to ECDSA signature generation, ECDH key agreement and ECDSA public key signature verification.
The hardware accelerator can implement such asymmetric cryptographic operations from ten to one-thousand times
faster than software running on standard microprocessors, without the usual high risk of key exposure that is
endemic to standard microprocessors.
The ATECC608B also implements AES-128, SHA256 and multiple SHA derivatives such as HMAC(SHA), PRF (the
key derivation function in TLS) and HKDF in hardware. Support is included for the Galois Field Multiply (aka Ghash)
to facilitate GCM encryption/decryption/authentication.
The device is designed to securely store multiple private keys along with their associated public keys and certificates.
The signature verification command can use any stored or an external ECC public key. Public keys stored within the
device can be configured to require validation via a certificate chain to speed up subsequent device authentications.
Random private key generation is supported internally within the device to ensure that the private key can never be
known outside of the device. The public key corresponding to a stored private key is always returned when the key is
generated and it may optionally be computed at a later time.
The ATECC608B can generate high-quality random numbers using its internal random number generator. This
sophisticated function includes runtime health testing designed to ensure that the values generated from the internal
noise source contain sufficient entropy at the time of use. The random number generator is designed to meet the
requirements documented in the NIST 800-90A, 800-90B and 800-90C documents.
These random numbers can be employed for any purpose, including as part of the device’s cryptographic protocols.
Because each random number is ensured to be essentially unique from all numbers ever generated on this or any
other device, their inclusion in the protocol calculation ensures that replay attacks (i.e., re-transmitting a previously
successful transaction) will always fail.
The ATECC608B also supports a standard hash-based challenge-response protocol to allow its use across a wide
variety of additional applications. In its most basic instantiation, the system sends a challenge to the device, which
combines that challenge with a secret key via the MAC command and then sends the response back to the system.
The device uses a SHA-256 cryptographic hash algorithm to make that combination so that an observer on the bus
cannot derive the value of the secret key. At the same time, the recipient can verify that the response is correct by
performing the same calculation with a stored copy of the secret on the recipient’s system. There are a wide variety
of variations possible on this symmetric challenge/response theme.
Voltage on any pin -0.5V to (VCC + 0.5V)-0.5V to (VCC + 0.5V)
ESD Ratings:
Human Body Model(HBM) ESD>4kV
Charge Device Model(CDM) ESD>1kV
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ATECC608B
Electrical Characteristics
2.2 Reliability
The ATECC608B is fabricated with Microchip’s high reliability CMOS EEPROM manufacturing technology.
Table 2-1. EEPROM Reliability
ParameterMin.Typ.Max.Units
Write Endurance at +85°C (Each Byte)400,000——Write Cycles
To Crypto Device93——µs After ATECC608B transmits the last bit
4.6068.60µs—
4.6068.60µs—
4.6068.60µs—
TIMEOUT
ATECC608B may enter Sleep mode.
415478µs —
6496131µsATECC608B will initiate the first low
going transition after this time interval
following the initial falling edge of the
start pulse of the last bit of the transmit
flag.
of a group, the system must wait this
interval before sending the first bit of a
flag. It is measured from the falling
edge of the start pulse of the last bit
transmitted by ATECC608B.
,
IO Timeout
t
TIMEOUT
To Crypto Device456585ms ATECC608B may transition to the
Sleep mode if the bus is inactive
longer than this duration.
Note:
1.t
START
, t
, t
ZLO
ZHI
and t
are designed to be compatible with a standard UART running at 230.4 kBaud for both
BIT
transmit and receive. The UART must be set to seven data bits, no parity and one Stop bit.
——6mA During ECC command execution. Clock divider = 0x5
——3mA During ECC command execution. Clock divider = 0xD
—800—µAWhen device is in Idle mode,
V
and V
SDA
—30150nAWhen device is in Sleep mode, VCC ≤ 3.6V,
V
and V
SDA
——2µAWhen device is in Sleep mode.
Over full VCC and temperature range.
——0.4VWhen device is in Active mode,
VCC = 2.5 to 5.5V
——4mA When device is in Active mode,
VCC = 2.5 to 5.5V, VOL = 0.4V
< 0.4V or > VCC – 0.4
SCL
< 0.4V or > VCC – 0.4, TA ≤ +55°C
SCL
Theta JAƟ
2.4.1 VIH and VIL Specifications
The input levels of the device will vary dependent on the mode and voltage of the device. The input voltage
thresholds when in Sleep or Idle mode are dependent on the VCC level as shown in Figure 2-4. When in Sleep or Idle
mode the TTLenable bit has no effect.
Table 2-6. VIL, VIH on All I/O Interfaces (TTLenable = 0)
ParameterSym.Min.Typ.Max.UnitsConditions
Input Low VoltageV
Input High VoltageV
IL
IH
—166—°C/W SOIC (SSH)
JA
—173—°C/W UDFN (MAH)
—146—°C/W RBH
-0.5—0.5VWhen device is active and TTLenable bit in Configuration
memory is zero; otherwise, see above.
1.5—VCC + 0.5VWhen device is active and TTLenable bit in Configuration
memory is zero; otherwise, see above.
The ATECC608B is designed to provide an enhanced security profile over that of the ATECC608A while maintaining
backwards compatibility. The following details the changes and enhancements to the device. No configuration bit
fields have changed. Configurations defined for the ATECC608A will be functionally identical with the ATECC608B
device.
Corrections, Enhancements
The following items have been corrected or enhanced in the ATECC608B device:
• Two temperature ranges are now available:
– Standard Industrial Temperature Range: -40℃ to +85℃
– Standard Industrial Temperature Range: -40℃ to +100℃
• Operating at a low I2C Frequency with multiple devices on the bus will no longer create a bus contention issue.
• Modifications to Command Timings for Verify, SecureBoot, Lock and Read commands.
• New Packaging Options: 3-Lead Contact Package and WLCSP for qualified customers. (Contact Microchip
Sales for the WLCSP Option.)
ATECC608B
Compatibility
3.2 Microchip ATECC508A
The ATECC608B is designed to be fully compatible with the ATECC508A devices with the limited exception of the
functions listed below. If the ATECC608B is properly configured, software written for the ATECC508A will work with
the ATECC608B without any required changes, again with the exception of the functions listed below.
Note: Most elements of the configuration zone in the ATECC608B are identical in both location and value with the
ATECC508A. However, the initial values that had been stored in the LastKeyUse field may need to be changed to
conform to the new definition of those bytes which can be found in this document. That field contained the initial
count for the Slot 15 limited use function which is supported in the ATECC608B via the monotonic counters.
The execution times of commands have changed between the ATECC608B and the ATECC508A. These
changes will not cause an issue if polling has been implemented. If fixed timing has been used, this must
be evaluated and updated as required.
New Features in ATECC608B vs. ATECC508A
• Secure boot function with IO encryption and authentication
• KDF command, supporting PRF, HKDF, AES
• AES command, including encrypt/decrypt
• GFM calculation function for GCM AEAD mode of AES
• Updated NIST SP800-90 A/B/C Random Number Generator
• Flexible SHA/HMAC command with context save/restore
• SHA command execution time significantly reduced
• Volatile Key Permitting to prevent device transfer
• Transport Key Locking to protect programmed devices during delivery
• Counter Limit Match function
• Ephemeral key generation in SRAM, also supported with ECDH and KDF
• Verify command output can be validated with a MAC
• Added self test command, optional automatic power-on self test
• Unaligned public key for built-in X.509 cert key validation
• Optional power reduction at increased execution time
• Programmable I2C address after data (secret) zone lock
Features Eliminated in ATECC608B vs. ATECC508A
• HMAC command removed, replaced via new more powerful SHA command
• OTP consumption mode eliminated, now read only
• Pause command eliminated along with related Selector function in UpdateExtra
• Slot 15 special limited use eliminated, replaced with standard monotonic counter limited use
• SHA command no longer uses TempKey during the digest calculation and the result in TempKey is unchanged
throughout the SHA operation. TempKey can however still be used to initialize the SHA for the HMAC_Start or to
store the final digest.
3.3 Microchip ATSHA204A, ATECC108A
The ATECC608B is generally compatible with all ATSHA204/A and ATECC108/A devices. If properly configured, it
can be used in most situations where these devices are currently employed. For ATSHA204A and ATECC108A
compatibility restrictions, see the ATECC508A data sheet.
As part of Microchip’s overall security features, the part marking for all crypto devices is intentionally vague. The
marking on the top of the package does not provide any information as to the actual device type or the manufacturer
of the device. The alphanumeric code on the package provides manufacturing information and will vary with
assembly lot. The packaging mark should not be used as part of any incoming inspection procedure.
Microchip provides online support via our website at www.microchip.com/. This website is used to make files and
information easily available to customers. Some of the content available includes:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Embedded Solutions Engineer (ESE)
• Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
1.Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering
purposes and is not printed on the device package. Check with your Microchip Sales Office for package
availability with the Tape and Reel option.
2.Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-
form factor package availability, or contact your local Sales Office.
3.Die-on-Tape and Reel and WLCSP packages are available for qualified customers. Ordering codes for these
packages are not shown in this table. Please contact Microchip sales for more information on these package
options.
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
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