Page 1
AT93C86A
3-wire Serial EEPROM
16K (2,048 x 8 or 1,024 x 16)
DATASHEET
Features
Low-voltage Operation
VCC = 1.8V to 5.5V
= 2.7V to 5.5V
V
CC
User-selectable Internal Organization
16K: 2,048 x 8 or 1,024 x 16
3-wire Serial Interface
Sequential Read Operation
Schmitt Trigger, Filtered Inputs for Noise Suppression
2MHz Clock Rate (5V)
Self-timed Write Cycle (10ms Max)
High Reliability
Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-lead PDIP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT93C86A provides 16,384 bits of Serial Electrically Erasable
Programmable Read-Only Memory (EEPROM) organized as 1,024 words of 16
bits each (when the ORG pin is connected to VCC) and 2,048 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage
operations are essential. The AT93C86A is available in space-saving 8-lead
JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-lead PDIP packages.
The AT93C86A is enabled through the Chip Select pin (CS) and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and
the data is clocked out serially on the DO pin. The write cycle is completely
self-timed, and no separate erase cycle is required before Write. The write cycle is
only enabled when the part is in the Erase/Write Enable state. When CS is
brought high following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part.
The AT93C86A operates from 1.8V to 5.5V or from 2.7V to 5.5V.
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Page 2
1. Pin Configurations and Pinouts
Table 1-1. Pin Configurations
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
V
CC
Power Supply
ORG Internal Organization
NC No Connect
2. Absolute Maximum Ratings*
8-lead SOIC
(Top View)
CS
SK
DO
1
2
3
DI
4
8
V
CC
7
NC
6
ORG
5
GND
8-pad UDFN
(Top View)
CS
SK
DO
1
2
DI
3
4
V
8
CC
NC
7
ORG
6
GND
5
Note: Drawings are not to scale.
CS
SK
DO
DI
CS
SK
DO
8-lead TSSOP
(Top View)
1
2
3
4
8-lead PDIP
(Top View)
1
2
3
DI
4
V
8
7
6
5
8
7
6
5
V
CC
NC
ORG
GND
CC
NC
ORG
GND
Operating Temperature . . . . . . . . . . .-55C to +125C
Storage Temperature . . . . . . . . . . . . .-65C to +150C
Voltage on any pin
with respect to ground . . . . . . . . . . . -1.00V to +7.00V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
2
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Page 3
3. Block Diagram
Figure 3-1. Block Diagram
ORG
DI
CS
SK
V
CC
Memory Array
2,048 x 8
1,024 x 16
Mode Decode
Generator
GND
or
Data
Register
Logic
Clock
Address
Decoder
Output
Buffer
DO
Note: When the ORG pin is connected to V
the x8 organization is selected. If the ORG pin is left unconnected, and the application does not load the input
beyond the capability of the internal 1M
, the x16 organization is selected. When it is connected to ground,
CC
pull-up resistor, then the x16 organization is selected.
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
3
Page 4
4. Memory Organization
4.1 Pin Capacitance
Table 4-1. Pin Capacitance
Applicable over recommended operating range from T
Symbol Test Conditions Max Units Conditions
C
OUT
C
IN
Output Capacitance (DO) 5 pF V
Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Note: 1. This parameter is characterized, and is not 100% tested.
4.2 DC Characteristics
Table 4-2. DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Unit
V
CC1
V
CC2
V
CC3
I
CC
Supply Voltage 1.8 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V
(1)
= 25C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted).
A
= 0V
OUT
Read at 1.0MHz 0.5 2.0 mA
Write at 1.0MHz 0.5 2.0 mA
I
SB1
I
SB2
I
SB3
I
IL
I
OL
(1)
V
IL1
(1)
V
IH1
(1)
V
IL2
(1)
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Note: 1. V
Standby Current VCC = 1.8V CS = 0V 0.4 1.0 μA
Standby Current VCC = 2.7V CS = 0V 6.0 10.0 μA
Standby Current VCC = 5.0V CS = 0V 10.0 15.0 μA
Input Leakage VIN = 0V to VCC 0.1 3.0 μA
Output Leakage VIN = 0V to VCC 0.1 3.0 μA
Input Low Voltage 2.7V VCC 5.5V 0.6 0.8 V
Input High Voltage 2.7V VCC 5.5V 2.0 VCC + 1 V
Input Low Voltage 1.8V VCC 2.7V 0.6 VCC x 0.3 V
Input High Voltage 1.8V VCC 2.7V VCC x 0.7 VCC + 1 V
Output Low Voltage 2.7V VCC 5.5V IOL = 2.1mA 0.4 V
Output High Voltage 2.7V VCC 5.5V IOH = 0.4mA 2.4 V
Output Low Voltage 1.8V VCC 2.5V IOL = 0.15mA 0.2 V
Output High Voltage 1.8V VCC 2.7V IOH = 100μA VCC 0.2 V
min and VIH max are reference only, and are not tested.
IL
4
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Page 5
4.3 AC Characteristics
Table 4-3. AC Characteristics
Applicable over recommended operating range from T
noted).
Symbol Parameter Test Condition Min Typ Max Units
= -40°C to + 85°C, CL = 1 TTL gate and 100pF (unless otherwise
AI
4.5V VCC 5.5V 0 2 MHz
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
SK Clock Frequency
2.7V VCC 5.5V 0 1 MHz
1.8V VCC 5.5V 0 250 kHz
2.7V VCC 5.5V 250 ns
SK High Time
1.8V VCC 5.5V 1000 ns
2.7V VCC 5.5V 250 ns
SK Low Time
1.8V VCC 5.5V 1000 ns
2.7V VCC 5.5V 250 ns
Minimum CS Low Time
1.8V VCC 5.5V 1000 ns
2.7V VCC 5.5V 50 ns
CS Setup Time Relative to SK
1.8V VCC 5.5V 200 ns
2.7V VCC 5.5V 100 ns
DI Setup Time Relative to SK
1.8V VCC 5.5V 400 ns
CS Hold Time Relative to SK 0 ns
2.7V VCC 5.5V 100 ns
DI Hold Time Relative to SK
1.8V VCC 5.5V 400 ns
2.7V VCC 5.5V 250 ns
Output Delay to 1 AC Test
1.8V VCC 5.5V 1000 ns
t
PD0
Output Delay to 0 AC Test
1.8V VCC 5.5V 1000 ns
2.7V VCC 5.5V 250 ns
2.7V VCC 5.5V 250 ns
t
SV
t
DF
t
WP
Endurance
CS to Status Valid AC Test
1.8V VCC 5.5V 1000 ns
CS to DO in
High-impedance
AC Test 2.7V VCC 5.5V 150 ns
CS = V
IL
1.8V VCC 5.5V 400 ns
Write Cycle Time 1.8V VCC 5.5V 0.1 3 10 ms
(1)
5.0V, 25°C 1,000,000
Note: 1. This parameter is characterized, and is not 100% tested.
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Write
Cycles
5
Page 6
5. Functional Description
The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface. Device operation
is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of
CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory address
location.
Table 5-1. AT93C86A Instruction Set
Instruction SB Opcode
Address Data
(1)
x16
(1)
x8 x16
Commentsx8
READ 1 10 A
10
– A
0
A9 – A
0
EWEN 1 00 11XXXXXXX 11XXXXXX
ERASE 1 11 A
WRITE 1 01 A
10
10
– A
– A
0
0
A9 – A
A9 – A
0
0
ERAL 1 00 10XXXXXXX 10XXXXXX
D7 – D
D
0
– D0Writes memory location AN – A0.
15
Reads data stored in memory at
specified address.
Write Enable must precede all
programming modes.
Erases memory location AN – A0.
Erases all memory locations.
Valid only at V
Writes all memory locations.
WRAL 1 00 01XXXXXXX 01XXXXXX D7 – D
D
15
– D
0
Valid only at V
0
Disable Register cleared.
EWDS 1 00 00XXXXXXX 00XXXXXX
Disables all programming
instructions.
Note: 1. The ‘X’ in the address field represent don’t care values, and must be clocked.
= 4.5V to 5.5V.
CC
= 4.5V to 5.5V and
CC
READ: The READ instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the Serial Output
pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be
noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string. The AT93C86A supports
sequential Read operations. The device will automatically increment the internal address pointer and clock out
the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (Logic 0) will not
be clocked out between memory locations, thus allowing for a continuous stream of data to be read.
Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first
before any programming instructions can be carried out.
Note: Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or VCC
power is removed from the part.
6
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Page 7
ERASE: The ERASE instruction programs all bits in the specified memory location to the Logic 1 state. The
self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A Logic 1 at the
DO pin indicates that the selected memory location has been erased, and the part is ready for another
instruction.
WRITE: The WRITE instruction contains the 8-bits or 16-bits of data to be written into the specified memory
location. The self-timed programming cycle, tWP, starts after the last bit of data is received at Serial Data Input
pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of tCS. A Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the
memory location at the specified address has been written with the data pattern contained in the instruction, and
the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the
end of the self-timed programming cycle, tWP.
Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state
and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought
high after being kept low for a minimum of tCS. The ERAL instruction is valid only at V
= 5.0V ± 10%.
CC
Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns
specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of tCS. The WRAL instruction is valid only at V
= 5.0V ± 10%.
CC
Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be executed after all programming operations. The
operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be
executed at any time.
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
7
Page 8
6. Timing Diagrams
Figure 6-1. Synchronous Data Timing
V
DI
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
t
t
DIS
CSS
t
SV
t
PD0
t
DIH
t
SKH
CS
SK
DO (Read)
DO (Program)
Note: 1. This is the minimum SK period.
Table 6-1. Organization Key for Timing Diagrams
AT93C86A (16K)
1µs
(1)
t
SKL
Status Valid
t
PD1
t
CSH
t
DF
t
DF
I/O
A
N
D
N
Figure 6-2. ERASE Timing
CS
SK
DI
DO
1 1 ...1AN
High-impedance High-impedance
x8 x16
A
10
D
7
AN-1 AN-2
A
D
9
15
t
CS
Check
Standby
Status
A0
t
SV
t
DF
Busy
Ready
t
WP
8
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Page 9
Figure 6-3. READ Timing
CS
SK
t
CS
DI
1 1 0 AN A0
High-impedance
DO
Figure 6-4. EWEN Timing
CS
SK
DI
10
011
0DN D0
t
CS
...
Figure 6-5. WRITE Timing
CS
SK
11
DI
DO
High-impedance
0A0D0
... ...
AN DN
t
CS
t
Busy
WP
Ready
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
9
Page 10
Figure 6-6. ERAL Timing
(1)
t
CS
CS
CS
SK
SK
DI
DI
DO
DO
11000
High-impedance High-impedance
Note: 1. VCC = 4.5V to 5.5V.
Figure 6-7. WRAL Timing
CS
CS
(1)
Standby
t
DF
t
WP
Check
Status
t
SV
Busy
Ready
t
CS
SK
SK
DI
DI
DO
DO
Note: 1. Valid only at V
1 0 0 1 ... D
High-impedance
CC
Figure 6-8. EWDS Timing
CS
SK
DI
10
= 4.5V to 5.5V.
000
...
... D00
N
Busy Ready
t
WP
t
CS
10
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Page 11
7. Ordering Code Detail
AT93C86AN-10SU-1.8-E
Atmel Designator
Product Family
93C = Microwire-Compatible
3-Wire Serial EEPROM
Device Density
86 = 8-Kilobit
Device Revision
Package Variation
(Package Type Dependent)
N = 0.150” width SOIC
Y6 = 2.0x3.0mm body UDFN
Shipping Carrier Option
Blank = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Expanded Quantity Option
Operating Voltage
1.8 or 18 = 1.8V to 5.5V
2.7 = 2.7V to 5.5V
Package Device Grade
U = Green, Matte Tin Lead Finish
or SnAgCu Ball
Industrial Temperature Range
(-40°C to +85°C)
H = Green, NiPdAu Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Type
S = JEDEC SOIC
T = TSSOP
Y = UDFN
P = PDIP
Speed Type
10 = Default value
Note: This field is not used for
Serial EEPROM products.
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
11
Page 12
8. Part Markings
AT93C86A: Package Marking Information
8-lead SOIC
ATMELYWW
93C86A
SU%%
Note: Lot Number and location of assembly
on the bottom side of the package.
8-pad UDFN
2.0 x 3.0 mm Body
###
H%
8-lead TSSOP
U%
AT###
Note: Lot Number, location of assembly and
YWW date code on the bottom side of
the package.
8-lead PDIP
ATMLUYWW
93C86A
PU%%
YXX
Note: Lot Number and location of assembly
on the bottom side of the package.
Note 1: designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT93C86A Truncation Code ###: 86A
Date Codes Voltages
Y = Year M = Month WW = Work Week of Assembly % = Minimum Voltage
4: 2014 8: 2018 A: January 02: Week 2 3 or 27: 2.7V min
5: 2015 9: 2019 B: February 04: Week 4 1 or 18: 1.8V min
6: 2016 0: 2020 ... ...
7: 2017 1: 2021 L: December 52: Week 52
Country of Assembly Lot Number Grade/Lead Finish Material
@ = Country of Assembly AAA...A = Atmel Wafer Lot Number H: Industrial/NiPdAu
U: Industrial/Matte Tin/SnAgCu
Trace Code Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel
Example: AA, AB.... YZ, ZZ ATM: Atmel
ATML: Atmel
12
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
93C86ASM, AT93C86A Package Marking Information
DRAWING NO. REV. TITLE
93C86ASM
6/11/14
A
Page 13
9. Ordering Information
Lead
Finish
Package Voltage
1.8V to 5.5V Tape and Reel 4,000 per Reel
Form Quantity
Atmel Ordering Code
AT93C86A-10SU-1.8
(1)
8S1
Delivery Information
AT93C86A-10SU-2.7 2.7V to 5.5V
AT93C86A-10TU-1.8
NiPdAu
Lead-free
Halogen-free
1.8V to 5.5V Tape and Reel 5,000 per Reel
(1)
Tape and Reel 4,000 per Reel
8X
AT93C86A-10TU-2.7 2.7V to 5.5V
AT93C86A-10PU-1.8
AT93C86A-10PU-2.7 2.7V to 5.5V
AT93C86AY6-10YH-1.8
AT93C86AY6-10YH-18-E Tape and Reel 15,000 per Reel
Matte Tin
Lead-free
Halogen-free
NiPdAu
Lead-free
Halogen-free
8P3
8MA2 1.8V to 5.5V
1.8V to 5.5V Tape and Reel 4,000 per Reel
(1)
Tape and Reel 5,000 per Reel
(1)
Tape and Reel 4,000 per Reel
Tape and Reel 5,000 per Reel
Operation
Range
Industrial
Temperature
(-40C to 85C)
AT93C86A-W1.8-11
(2)
N/A Wafer Sale 1.8V to 5.5V Note 2
Notes: 1. For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in Section 4.2, “DC Characteristics”
and 4.3, “AC Characteristics” on page 5.
2. For Waffle pack and Wafer form; order as SL788 for inkless Wafer form. Bumped die available upon request. Please
contact Atmel sales.
Package Type
8S1 8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC)
8X 8-lead, 0.170” wide, Thin Shrink Small Outline (TSSOP)
8P3 8-lead, 0.300” wide body, Plastic Dual In-line Package (PDIP)
8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN)
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
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Page 14
10. Packaging Information
10.1 8S1 — 8-lead JEDEC SOIC
C
1
N
TOP VIEW
e
D
b
A
A1
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
E
E1
L
Ø
END VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
ØØ 0° – 8°
MIN
NOM
MAX
NOTE
14
Package Drawing Contact:
packagedrawings@atmel.com
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
SWB
6/22/11
DRAWING NO. REV. TITLE GPC
8S1 G
Page 15
10.2 8X — 8-lead TSSOP
1
Pin 1 indicator
this corner
E1
E
N
Top View
b
A
A1
e
A2
D
Side View
Notes: 1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
C
L1
L
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX
A - - 1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
b 0.19 0.25 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
C 0.09 - 0.20
NOTE
Package Drawing Contact:
packagedrawings@atmel.com
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
DRAWING NO. REV. TITLE GPC
TNR
8X E
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
2/27/14
15
Page 16
10.3 8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
D
3
4
TOP VIEW
A2
A1
E2
b (8x)
8
7
6
5
Pin#1 ID
e (6x)
L (8x)
BOTTOM VIEW
Notes: 1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
6
5
A
1
2
D2
3
4
K
C
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 0.50 0.55 0.60
A1 0.0 0.02 0.05
A2 - - 0.55
D 1.90 2.00 2.10
D2 1.40 1.50 1.60
E 2.90 3.00 3.10
E2 1.20 1.30 1.40
b 0.18 0.25 0.30 3
C 1.52 REF
L 0.30 0.35 0.40
e 0.50 BSC
K 0.20 - -
MIN
NOM
MAX
NOTE
16
Package Drawing Contact:
packagedrawings@atmel.com
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
GPC
YNZ
11/26/14
DRAWING NO. REV. TITLE
8MA2 G
Page 17
10.4 8P3 — 8-lead PDIP
D1
A1
b3
4 PLCS
Top View
D
e
Side View
1
E
E1
.381
Gage Plane
N
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
b
b2
v
A2 A
0.254
MIN
SYMBOL
A - - 5.334 2
A1 0.381 - -
A2 2.921 3.302 4.953
b 0.356 0.457 0.559 5
b2 1.143 1.524 1.778 6
b3 0.762 0.991 1.143 6
c 0.203 0.254 0.356
L
m
C
D 9.017 9.271 10.160 3
D1 0.127 0.000 0.000 3
E 7.620 7.874 8.255 4
E1 6.096 6.350 7.112 3
e 2.540 BSC
eA 7.620 BSC 4
L 2.921 3.302 3.810 2
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
DRAWING NO. REV. TITLE GPC
Package Drawing Contact:
packagedrawings@atmel.com
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
PTC
8P3 E
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
07/31/14
17
Page 18
11. Revision History
Revision No. Date Comments
3408J 01/2015
3408I 08/2014
3408H 01/2007
3408G 07/2006
Add the UDFN extended quantity option and update the ordering information section.
Update the 8MA2 and 8P3 package drawings.
Update pinouts, 8MA2 package drawing, grammatical changes, document template,
logos, and disclaimer page. No changes to functional specification.
Add “Bottom View” to pg 1 Ultra Thin MiniMap package drawing pg 4 revise Note 1
added “ensured by characterization”.
Revision history implemented.
Delete ‘Preliminary’ status from datasheet; Add ‘Ultra Thin’ description to MLP 2x3
package; Delete ‘1.8V not available’ on Figure 1 Note; Add 1.8V range on Table 4 under
Write Cycle Time.
18
AT93C86A [DATASHEET]
Atmel-3408J-SEEPROM-AT93C86A-Datasheet_012015
Page 19
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