Page 1
BDTIC www.bdtic.com/ATMEL
1. Features
• Medium-voltage and Standard-voltage Operation
– 2.7 (V
• Automotive Temperature Range –40°C to +125°C
• User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
• 3-wire Serial Interface
• Sequential Read Operation
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• 2 MHz Clock Rate (5V) Compatibility
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Lead-Free/Halogen-Free Devices Available
• 8-lead JEDEC SOIC and 8-lead TSSOP Packages
2. Description
The AT93C86A provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin
is connected to V
device is optimized for use in many automotive applications where low-power and
low-voltage operations are essential. The AT93C86A is available in space saving 8lead JEDEC SOIC and 8-lead TSSOP packages.
Table 2-1. Pin Configuration
Pin Name Function
= 2.7V to 5.5V)
CC
and 2048 words of 8 bits each when it is tied to ground. The
CC
8-lead SOIC
Three-wire
Automotive
Temperature
Serial
EEPROM
16K (2048 x 8 or 1024 x 16)
AT93C86A
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
ORG Internal Organization
DC Don’t Connect
The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before Write. The write cycle is only
enabled when the part is in the Erase/Write Enable state. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part. The AT93C86A is available in a 2.7V to 5.5V version.
CS
SK
DI
DO
CS
SK
DI
DO
1
2
3
4
8-lead TSSOP
1
2
3
4
VCC
8
DC
7
ORG
6
GND
5
8
VCC
7
DC
6
ORG
5
GND
Rev. 5096E–SEEPR–1/08
Page 2
Absolute Maximum Ratings*
O
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on any Pin
with Respect to Ground ....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 2-1. Block Diagram
Vcc GND
MEMORY ARRAY
RG
2048 x 8
1024 x 16
OR
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
ADDRESS
DECODER
DATA
REGISTER
DI
CS
SK
MODE
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
Note: When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
Table 2-2. Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
C
OUT
C
IN
Note: 1. This parameter is characterized and is not 100% tested.
Output Capacitance (DO) 5 pF V
OUT
= 0V
Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
2
AT93C86A
5096E–SEEPR–1/08
Page 3
AT93C86A
Table 2-3. DC Characteristics
Applicable over recommended operating range from: T
noted)
Symbol Parameter Test Condition Min Typ Max Unit
= –40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise
A
V
CC1
V
CC2
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
READ at 1.0 MHz 0.5 2.0 mA
I
I
I
I
I
V
V
V
V
CC
SB1
SB2
IL
OL
IL1
IH1
OL1
OH1
(1)
(1)
Supply Current VCC = 5.0V
WRITE at 1.0 MHz 0.5 2.0 mA
Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
Standby Current VCC = 5.0V CS = 0V 10.0 15.0 µA
Input Leakage VIN = 0V to VCC 0.1 3.0 µA
Output Leakage VIN = 0V to VCC 0.1 3.0 µA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ V
≤ 5.5V
CC
I
= 2.1 mA 0.4 V
OL
I
= –0.4 mA 2.4 V
OH
−−−−0.6 0.8 V
2.0 V
+ 1 V
CC
Note: 1. VIL min and VIH max are reference only and are not tested.
Table 2-4. AC Characteristics
Applicable over recommended operating range from T
= –40°C to +125°C, VCC = As Specified,
A
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
f
t
t
t
t
t
t
t
t
t
SK
SKH
SKL
CS
CSS
DIS
CSH
DIH
PD1
PD0
SK Clock
Frequency
SK High Time
SK Low Time
Minimum CS
Low Time
CS Setup Time Relative to SK
DI Setup Time Relative to SK
CS Hold Time Relative to SK 0 ns
DI Hold Time Relative to SK
Output Delay to ‘1’ AC Test
Output Delay to ‘0’ AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
4.5V ≤ V
2.7V ≤ V
4.5V ≤ V
2.7V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
≤ 5.5V
CC
4.5V ≤ V
2.7V ≤ V
4.5V ≤ V
2.7V ≤ V
4.5V ≤ V
2.7V ≤ V
4.5V ≤ V
2.7V ≤ V
4.5V ≤ V
2.7V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
0
0
250
250
250
250
250
250
50
50
100
100
100
100
2
1
250
500
250
500
MHz
ns
ns
ns
ns
ns
ns
ns
ns
5096E–SEEPR–1/08
3
Page 4
Table 2-4. AC Characteristics (Continued)
Applicable over recommended operating range from T
= –40°C to +125°C, VCC = As Specified,
A
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
t
SV
t
DF
t
WP
Endurance
(1)
CS to Status Valid AC Test
CS to DO in High
Impedance
Write Cycle Time
5.0V, 25°C 1M Write Cycles
AC Test
CS = V
IL
4.5V ≤ V
2.7V ≤ V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.7V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V 0.1 4 10 ms
CC
250
250
100
150
Note: 1. This parameter is characterized and is not 100% tested.
Table 2-5. Instruction Set for the AT93C86A
Address Data
Instruction SB Op Code
Commentsx 8 x 16 x 8 x 16
ns
ns
READ 1 10 A
10
– A
0
A9 – A
0
Reads data stored in memory,
at specified address.
EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write enable must precede all
programming modes.
ERASE 1 11 A
WRITE 1 01 A
10
10
– A
– A
0
0
A9 – A
A9 – A
0
0
D7 – D0D
15
Erases memory location An – A0.
– D0Writes memory location An – A0.
ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Erases all memory locations.
WRAL 1 00 01XXXXXXXXX 01XXXXXXXX D
– D0D
7
Valid only at V
– D0Writes all memory locations.
15
Val id w h e n V
= 4.5V to 5.5V.
CC
= 4.5V to 5.5V and
CC
Disable Register cleared.
EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Disables all programming
instructions.
4
AT93C86A
5096E–SEEPR–1/08
Page 5
3. Functional Description
The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface.
Device operation is controlled by seven instructions issued by the host processor. A valid
instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the
appropriate Op Code and the desired memory address location.
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or
16-bit data output string. The AT93C86A supports sequential read operations. The device will
automatically increment the internal address pointer and clock out the next memory location as
long as CS is held high. In this case, the dummy bit (logic “0”) will not be clocked out between
memory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or V
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and
address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought
high after being kept low for a minimum of 250 ns (t
selected memory location has been erased, and the part is ready for another instruction.
power is removed from the part.
CC
AT93C86A
). A logic “1” at pin DO indicates that the
CS
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written
into the specified memory location. The self-timed programming cycle t
starts after the last bit
WP
of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the
part if CS is brought high after being kept low for a minimum of 250 ns (t
). A logic “0” at DO
CS
indicates that programming is still in progress. A logic “1” indicates that the memory location at
the specified address has been written with the data pattern contained in the instruction and the
part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is
brought high after the end of the self-timed programming cycle t
WP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(t
). The Eral instruction is valid only at VCC = 5.0V ± 10%.
CS
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (t
valid only at V
= 5.0V ± 10%.
CC
). The Wral instruction is
CS
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of
both the Ewen and Ewds instructions and can be executed at any time.
5096E–SEEPR–1/08
5
Page 6
4. Timing Diagrams
Figure 4-1. Synchronous Data Timing
Note: 1. This is the minimum SK period.
Table 4-1. Organization Key for Timing Diagrams
I/O
A
N
D
N
Figure 4-2. READ Timing
AT93C86A (16K)
x 8 x 16
A
10
D
7
A
9
D
15
6
AT93C86A
5096E–SEEPR–1/08
Page 7
Figure 4-3. EWEN Timing
C
S
C
S
C
D
S
K
AT93C86A
t
CS
DI
Figure 4-4. EWDS Timing
S
K
DI 1 0
Figure 4-5. WRITE Timing
S
SK
001
11
000
...
t
CS
...
t
CS
DI
HIGH IMPEDANCE
O
11
0A0D0
... ...
A
N
D
N
BUSY
t
WP
READY
7
5096E–SEEPR–1/08
Page 8
Figure 4-6. WRAL Timing
C
D
C
D
E
S
SK
(1)
t
CS
DI
HIGH IMPEDANCE
1 0 0 1 ... D
O
Note: 1. Valid only at VCC = 4.5V to 5.5V.
Figure 4-7. ERASE Timing
S
SK
DI A
1 1 ...1
N
A
N-1AN-2
A0
... D00
N
BUSY
READY
t
WP
t
CS
CHECK
STATUS
t
SV
STANDBY
t
DF
HIGH IMPEDANCE
O
BUSY
READY
t
WP
HIGH IMPEDANC
8
AT93C86A
5096E–SEEPR–1/08
Page 9
AT93C86A
Figure 4-8. ERAL Timing
Note: 1. Valid only at VCC = 4.5V to 5.5V.
(1)
D
5096E–SEEPR–1/08
9
Page 10
5. AT93C86A Ordering Information
Ordering Code Package Operation Range
AT93C86A-10SQ-2.7
AT93C86A-10TQ-2.7
8S1
8A2
Lead-free/Halogen-free
Automotive Temperature
(−40°C to 125°C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
−2.7 Low Voltage (2.7V to 5.5V)
10
AT93C86A
5096E–SEEPR–1/08
Page 11
6. Packaging Information
Ø
E
1
N
C
E1
A
b
L
A1
e
D
6.1 8S1 – JEDEC SOIC
AT93C86A
C
1
E
N
Ø
E1
L
TOP VIEW
END VIEW
e
D
SIDE VIEW
b
COMMON DIMENSIONS
A
A1
SYMBOL
A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
θ 0° – 8°
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
R
5096E–SEEPR–1/08
3/17/05
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1 C
REV.
11
Page 12
6.2 8A2 – TSSOP
Pin 1 indicator
this corner
123
N
Top View
b
e
D
Side View
A2
E1
E
L1
L
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
12
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
2325 Orchard Parkway
R
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
AT93C86A
5096E–SEEPR–1/08
5/30/02
REV.
B
Page 13
7. Revision History
Doc. Rev. Date Comments
5096E 1/2008
AT93C86A
Moved to new template
Replaced Table 5 with correct version
5096D 2/2007
5096C 9/2006
Removed PDIP package offering
Removed Pb’d part numbers
Revision history implemented; Removed ‘Preliminary’ status
from datasheet.
5096E–SEEPR–1/08
13
Loading...