Datasheet AT93C46C-10SI-2.7, AT93C46C-10SI-2.5, AT93C46C-10SI, AT93C46C-10SC-2.7, AT93C46C-10SC-2.5 Datasheet (ATMEL)

Features

•

Low-Voltage and Standard-Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)

•

3-Wire Serial Interface

•

Schmitt Trigger, Filtered Inputs for Noise Suppression

•

2 MHz Clock Rate (5V) Compatibility

•

Self-Timed Write Cycle (10 ms max)

•

High Reliability

– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: > 4000V

•

Automotive Grade and Extended Temperature Devices Available

•

8-Pin PDIP and JEDEC SOIC Packages

Description

The AT93C46C provides 1024 bits of serial electrically-erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each. The devi ce is opti­mized for use in many industrial and commercial appl ications where lo w-power and
low-voltage operation are essential. The AT93C46C is available in space saving 8-pin
PDIP and 8-pin JEDEC packages.

The AT93C46C is enabled through the Chip Select pin (CS) , and accessed vi a a 3­wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycl e is completely self­timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is
brought “high” followin g the initiation of a WRITE cy cle, the DO pin outputs the
READY/BUSY status of the part.

The AT93C46C is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V versions.

3-Wire
Serial EEPROM

1K (64 x 16)

AT93C46C

Pin Configurations

Pin Name Function

CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
NC No Connect
DC Don’t Connect

CS
SK

DI

DO

CS
SK

DI

DO

8-Pin PDIP

1
2
3
4

8-Pin SOIC

1
2
3
4

8

VCC

7

DC

6

NC

5

GND

VCC

8

DC

7

NC

6

GND

5

3-Wire, 1K
Serial E

2

PROM

Rev. 1122A–07/98

1

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage........................................... 6.25V

DC Output Current........................................................5.0 mA

Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the de vic e. T his is a stres s r ating o nly an d
functional opera tion of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reli abi li ty.

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Test Conditions Max Units Conditions

C

OUT

C

IN

Note: 1. This parameter is characterized and is not 100% tested.

2

Output Capacitance (DO) 5 pF V
Input Capacitance (CS, SK, DI) 5 pF VIN = 0V

OUT

= 0V

AT93C46C

AT93C46C

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V,

= 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted).

T

AC

Symbol Parameter Test Condition Min Typ Max Units

V
V
V
I

I
I
I
I
I
V

V
V

V
V

V

CC1

CC2

CC3

CC

SB1

SB2

SB3

IL

OL

IL1
IH1

OL1
OH1

OL2
OH2

(1)

(1)

Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current

V

= 5.0V

CC

READ at 1.0 MHz 0.5 2.0 mA

WRITE at 1.0 MHz 0.5 2.0 mA
Standby Current VCC = 2.5V CS = 0V 14.0 20.0 µA
Standby Current VCC = 2.7V CS = 0V 14.0 20.0 µA
Standby Current VCC = 5.0V CS = 0V 35.0 50.0 µA
Input Leakage VIN = 0V to VCC 0.1 1.0 µA
Output Leakage VIN = 0V to VCC 0.1 1.0 µA
Input Low Voltage

Input High Voltage
Output Low Voltage

Output High Voltage
Output Low Voltage

Output High Voltage

2.5V ≤ VCC ≤ 5.5V

4.5V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 2.7V

CC

I

= 2.1 mA 0.4 V

OL

I

= -0.4 mA 2.4 V

OH

= 0.15 mA 0.2 V

I

OL

IOH = -100 µAV

Note: 1. VIL min and VIH max are reference only and are not tested.

-0.6

V

x 0.7

CC

- 0.2 V

CC

x 0.3

V

CC

V

+ 1

CC

V

AC Characteristics

Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

f

t

t

t

t

SK

SKH

SKL

CS

CSS

SK Clock Frequency 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

SK High Time 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

SK Low Time 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

0
0
0

250
250
500

250
250
500

250
250
500

50
50

100

2
1

0.5

MHz

ns

ns

ns

ns

3

AC Characteristics (Continued)

Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

t

DIS

t

CSH

t

DIH

t

PD1

t

PD0

t

SV

t

DF

t

WP

Endurance

Note: 1. This parameter is characterized and is not 100% tested.

DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

100
100

200
CS Hold Time Relative to SK 0 ns
DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

Output Delay to ‘1’ AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

Output Delay to ‘0’ AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ V

2.5V ≤ V

≤ 5.5V

CC

≤ 5.5V

CC

CS to Status Valid AC Test 4.5V ≤ VCC ≤ 5.5V

≤ 5.5V

CC

≤ 5.5V

CC

≤ 5.5V

CC

≤ 5.5V

CC

CS to DO in High Impedance AC Test

CS = V

2.7V ≤ V

2.5V ≤ V

4.5V ≤ VCC ≤ 5.5V

IL

2.7V ≤ V

2.5V ≤ V

100

100

200

250
250
500

250
250
500

250
250
500

100
100
200

Write Cycle Time 0.1 10 ms

4.5V ≤ V

(1)

5.0V, 25°C, Page Mode 1 M Write Cycle

≤ 5.5V 1 ms

CC

ns

ns

ns

ns

ns

ns

Instruction Set for the AT93C46C

Address

Instruction SB Op Code

READ 1 10 A

5

- A

0

EWEN 1 00 11XXXX Write enable must precede all programming modes.
ERASE 1 11 A
WRITE 1 01 A

5

5

- A

- A

0

0

ERAL 1 00 10XXXX Erases all memory locations. Valid only at V
WRAL 1 00 01XXXX Writes all memory locations. Valid only at VCC = 4.5V to 5.5V.
EWDS 1 00 00XXXX Disables all programming instructions.

4

AT93C46C

Commentsx 16

Reads data stored in memory, at specified address.

Erase memory location An - A0.
Writes memory location An - A0.

= 4.5V to 5.5V.

CC

Functional Description

The AT93C46C is accessed via a simple and vers atile
three-wire serial communication interface. Device opera­tion is controlle d by se ven ins tructio ns issued by the host
processor.

of CS

appropriate Op Code and the desired memory Address
location.

READ (READ):

the Address code fo r the me mor y l oc ati on to be re ad. A fter
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the ris­ing edges of serial clock SK. It should be noted that a
dummy bit (logic ‘0’) precedes the 16-bit data output string.

ERASE/WRITE (EWEN):

part automatically go es into the Erase/Write Dis able
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, program­ming remains e nabled until an Erase/Write Disable
(EWDS) instruction is executed or V
from the part.

ERASE (ERASE):

grams all bits in the specified memory location to the logical
‘1’ state. The self-timed erase cycle starts once the ERASE
instruction and address are decoded. The DO pin outputs
the READY/BUSY status of the part if CS is brought high
after being kept low for a minimum of 250 ns (t
‘1’ at pin DO indicates that the selected memory location
has been erase d, and the part is ready for an other inst ruc­tion.

A valid instruction starts with a rising edge

and consists of a Start Bit (logic ‘1’) followed by the

The Read (READ) instructio n contains

To assure data integrity, the

power is removed

CC

The Erase (ERASE) instruction pr o-

). A logic

CS

AT93C46C

WRITE (WRITE):

the 16 bits of data to be written into the specified memory
location. The self-timed programming cycle t
the last bit of data is received at serial data input pin DI.
The DO pin outputs the READY/BUSY status of the part if
CS is brought high after being kept low for a minimum of
250 ns (t

). A logic ‘0’ at DO indicates that programming is

CS

still in progress. A logic ‘1’ indicates that the memory loca­tion at the specified ad dr ess h as been wr itte n wi th th e da ta
pattern contained in the instruction and the part is ready for
further instructions.

obtained if the CS is brought high after the end of the
self-timed programming cycle, t

ERASE ALL (E RAL):

programs every bit in the memory array to the logic ‘1’ state
and is primarily u sed for testi ng purpos es. The DO pin out­puts the READY/BU SY status of the pa rt if CS is brough t
high after being kept low for a minimum of 250 ns (t
ERAL instruction is vali d only at V

WRITE ALL (WRAL):

programs all memory locations with the data patterns spec­ified in the instruction. The DO pin outputs the
READY/BUSY sta tus of the pa rt if CS i s brought h igh after
being kept low for a minimum of 250 ns (t
instruction is valid only at V

ERASE/WRITE DI SABLE (EWDS):

accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.

The Write (WRITE) instruction contains

starts after

WP

A Ready/Busy Status cannot be

.

WP

The Erase All (ERAL) instruction

). The

= 5.0V ± 10%.

CC

CS

The Write All (WRAL) instruction

). The WRAL

= 5.0V ± 10%.

CC

CS

To protect against

5

Timing Diagrams

Synchronous Data Timing

Note: 1. This is the minimum SK period.

6

AT93C46C

Organization Key for Timing Diagrams

AT93C46C

I/O

A

N

D

N

READ Timing

CS

SK

DI

x 16

A

D

15

11

5

...

A

0

N

A0

AT93C46C

t

CS

DO

EWEN Timing

Note: 1. Requires a minimum of nine clock cycles.

EWDS Timing

(1)

(1)

0

...

D

N

D0

Note: 1. Requires a minimum of nine clock cycles.

7

WRITE Timing

WRAL Timing

Notes: 1. Valid only at VCC = 4.5V to 5.5V.

2. Require s a minimum of nine clock cycles.

(1)(2)

8

AT93C46C

ERASE Timin g

AT93C46C

TERAL Timing

Note: 1. Valid only at VCC = 4.5V to 5.5V.

(1)

9

Ordering Information

tWP (max)

(ms)

10 2000 50.0 2000 AT93C46C-10PC

10 2000 50.0 2000 AT93C46C-10PI

10 800 20.0 1000 AT93C46C-10PC-2.7

10 800 20.0 1000 AT93C46C-10PI-2.7

10 600 20.0 500 AT93C46C-10PC-2.5

10 600 20.0 500 AT93C46C-10PI-2.5

ICC (max)

(µA)

ISB (max)

(µA)

f

MAX

(kHz) Ordering Code Packag e Operation Range

AT93C46C-10SC

AT93C46C-10SI

AT93C46C-10SC-2.7

AT93C46C-10SI-2.7

AT93C46C-10SC-2.5

AT93C46C-10SI-2.5

8P3
8S1

8P3
8S1

8P3
8S1

8P3
8S1

8P3
8S1

8P3
8S1

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

Blank Standard Device (4.5V to 5.5V)

-2.7 Low Voltage (2.7V to 5.5 V)

-2.5 Low Voltage (2.5V to 5.5 V)

10

AT93C46C

Packaging Information

AT93C46C

8P3

, 8-Lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 BA

.400 (10.16)
.355 (9.02)

PIN

1

.280 (7.11)
.240 (6.10)

.037 (.940)

.300 (7.62) REF

.210 (5.33) MAX

SEATING

PLANE

.150 (3.81)
.115 (2.92)

.012 (.305)
.008 (.203)

.070 (1.78)
.045 (1.14)

.027 (.690)

.100 (2.54) BSC

.015 (.380) MIN

.022 (.559)
.014 (.356)

.325 (8.26)
.300 (7.62)

0

REF

15

.430 (10.9) MAX

8S1

, 8-Lead, 0.150" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)

.020 (.508)
.013 (.330)

.244 (6.20)
.228 (5.79)

.068 (1.73)
.053 (1.35)

.010 (.254)
.007 (.203)

PIN 1

0
8

.157 (3.99)
.150 (3.81)

.050 (1.27) BSC

.196 (4.98)
.189 (4.80)

.010 (.254)
.004 (.102)

REF

.050 (1.27)
.016 (.406)

11