Page 1
AT91EB42 Evaluation Board
..............................................................................................
User Guide
Page 2
Page 3
Table of Contents
Section 1
Overview...............................................................................................1-1
1.1 Scope........................................................................................................1-1
1.2 Deliverables ..............................................................................................1-1
1.3 The AT91EB42 Evaluation Board .............................................................1-1
Section 2
Setting Up the
AT91EB42 Evaluation Board ................................................................2-1
2.1 Electrostatic Warning ................................................................................2-1
2.2 Requirements............................................................................................2-1
2.3 Layout .......................................................................................................2-1
2.4 Jumper Settings ........................................................................................2-2
2.5 Powering Up the Board .............................................................................2-2
2.6 Measuring Current Consumption on the AT91M42800A ..........................2-2
2.7 Testing the AT91EB42 Evaluation Board..................................................2-3
Section 3
The On-board Software ........................................................................3-1
3.1 AT91EB42 Evaluation Board ....................................................................3-1
3.2 Boot Software Program.............................................................................3-1
3.3 Programmed Default Memory Mapping....................................................3-2
3.4 Flash Uploader..........................................................................................3-2
3.5 Power-down Demonstration......................................................................3-3
3.6 Angel Debug Monitor ................................................................................3-3
3.7 Programmed Default Speed......................................................................3-3
Section 4
Circuit Description................................................................................. 4-1
4.1 AT91M42800A Processor .........................................................................4-1
4.2 Expansion Connectors and JTAG Interface..............................................4-1
4.2.1 I/O Expansion Connector ...................................................................4-1
4.2.2 EBI Expansion Connector ..................................................................4-1
4.2.3 JTAG Interface ...................................................................................4-1
4.3 Memories ..................................................................................................4-2
4.4 Analog-to-digital Converter .......................................................................4-2
4.5 Power and Crystal Quartz .........................................................................4-2
4.6 Push-buttons, LEDs, Reset and Serial Interfaces.....................................4-3
4.7 Layout Drawing .........................................................................................4-3
AT91EB42 Evaluation Board User Guide i
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Table of Contents
Section 5
Appendix A – Configuration Straps....................................................... 5-1
5.1 Functional Pin Assignment .......................................................................5-1
5.2 Configuration Straps (CB1 - 23, JP1 - 8) ..................................................5-2
5.3 Power Consumption Measurement Strap (JP5) .......................................5-7
5.4 Ground Links (JP6) ...................................................................................5-7
5.5 Increasing Memory Size ...........................................................................5-7
Section 6
Appendix B – Schematics.....................................................................6-1
6.1 Schematics ...............................................................................................6-1
Section 7
Appendix C – Bill of Materials...............................................................7-1
Section 8
Appendix D – Flash
Memory Mapping .................................................................................. 8-1
ii AT91EB42 Evaluation Board User Guide
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Page 5
Section 1
Overview
1.1 Scope The AT91EB42 Evaluation Board enables real-time code development and evaluation.
It supports the AT91M42800A.
This user guide focuses on the AT91EB42 Evaluation Board as an evaluation and dem-
onstration platform.
! Section 1 provides an overview.
! Section 2 describes how to set up the evaluation board.
! Section 3 details the on-board software.
! Section 4 contains a description of the circuit board.
! Section 5 and Section 6 are two appendixes covering configuration straps and
schematics, including pin connectors.
1.2 Deliverables The evaluation board is delivered with a DB9 plug-to-DB9 socket straight-through serial
cable to connect the target evaluation board to a PC. A bare power lead with a 2.1 mm
jack on one end for connection to a bench power supply is also delivered.
The evaluation board is also delivered with a CD-ROM that contains an evaluation version of the software development toolkit, the documentation that outlines the AT91
microcontroller family and the AT91 C Library.
1.3 The AT91EB42 Evaluation Board
The evaluation board is capable of supporting different kinds of debugging systems,
using an ICE interface or the on-board Angel
The board consists of an AT91M42800A together with several peripherals:
! Two serial ports
! Reset push-button
! An indicator that memorizes a reset event
! Four user-defined push-buttons
! Eight LEDs
! A 256K bytes 16-bit SRAM (upgradeable to 1M byte)
™
Debug Monitor.
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Overview
! A 2M bytes 16-bit Flash (of which 1M byte is available for user software)
! A 4M bytes Serial DataFlash
! An analog-to-digital converter with SPI access
! 2 x 32-pin EBI expansion connectors
! 2 x 32-pin I/O expansion connectors
! 20-pin JTAG interface connector
If required, user-defined peripherals can also be added to the board. See Section 5 for
details.
Figure 1-1. AT91EB42 Evaluation Board Block Diagram
AT91M42800A
Reset
Controller
JTAG
ICE
Connector
ARM7TDMI
Processor
8K Bytes
RAM
ASB
EBI
SRAM
EBI
Expansion
Connector
Flash
2.1 mm DC
Power
Socket
Fast-charge
Controller
32.768 kHz
Crystal
Push-buttons
Reset
Controller
Power Supply
Battery
Connector
Clock
Generator
Interrupt
Controller
System
Timer
Watchdog
Reset
PIO
APB
AMBA
Bridge
PIO
Timer
Counters
SPI
Serial
Ports
LEDs
Serial
DataFlash
10-bit ADC
4 Channels
RS232
Transceivers
I/O
Expansion
Connector
DB9 Serial
Connectors
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Section 2
Setting Up the
AT91EB42 Evaluation Board
2.1 Electrostatic Warning
2.2 Requirements In order to set up the AT91EB42 Evaluation Board, the following requirements are
2.3 Layout Figure 2-1 shows the layout of the AT91EB42 Evaluation Board.
The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. The
board must not be subjected to high electrostatic potentials. A grounding strap or similar
protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
needed:
! The AT91EB42 Evaluation Board itself
! The DC power supply capable of supplying 7V to 12V at 1A (not supplied)
Figure 2-1. Layout of the AT91EB42 Evaluation Board
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Setting Up the AT91EB42 Evaluation Board
2.4 Jumper Settings JP1 is used to boot standard or user programs. For standard operations, set it in the
STD position.
JP8 is used to select the core power supply of the AT91M42800A. Operations at 2V are
not supported on the current silicon.
For more information about jumpers and other straps, see Section 5.
2.5 Powering Up the Board
DC power is supplied to the board via the 2.1 mm socket (J1) shown in Figure 2-2. The
polarity of the power supply is not critical. The minimum voltage required is 7V.
A battery is supplied on the AT91EB42. It supplies all on-board devices in the same way
that the external DC power operates. A battery fast-charge controller is provided onboard with a fast-charge indicator (D28), as shown in Figure 2-1.
Figure 2-2. 2.1 mm Socket
positive (+)
or
negative (-)
2.1 mm Connector
The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to range from 7V to 12V. When you switch the power on, the red LED marked
POWER lights up. If it does not, switch off and check the power supply connections.
2.6 Measuring
Current
Consumption
on the
The board is designed to generate the power for the AT91 product, and only the AT91
product, through the jumpers JP5 (V
surements of the consumption of the AT91 product to be made.
See Section 5 for further details.
) and JP8 (V
DDIO
DDCORE
). This feature enables mea-
AT91M42800A
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Setting Up the AT91EB42 Evaluation Board
2.7 Testing the AT91EB42 Evaluation Board
To test the AT91EB42 Evaluation Board, perform the following procedure:
1. Hold down the SW1 button and power-up the board, or generate a reset and wait
for the light sequence on each LED to complete. All the LEDs light.
2. Release the SW1 button. The LEDs D1 to D8 light up in sequential order. If all
the LEDs light up twice, this indicates an error.
The LEDs represent the following test functions:
! D1 for the internal SRAM
! D2 for the external SRAM
! D3 for the external Flash
! D4 reserved
! D5 for the SPI DataFlash
®
! D6 reserved
! D7 for the USART
! D8 for ADC with SPI access
During a complete test cycle, each LED flashes once to inform the user that the corresponding function has been successfully tested. If an error is detected, all the LEDs will
light up twice. After a complete test cycle, the embedded self-test software called Functional Test Software (FTS) restarts a new cycle.
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Setting Up the AT91EB42 Evaluation Board
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Section 3
The On-board Software
3.1 AT91EB42 Evaluation Board
3.2 Boot Software Program
The AT91EB42 Evaluation Board embeds an AT49BV162A Flash memory device programmed with default software. Only the lowest 8 x 8 KB sectors are used. The
remaining sectors are user definable, and can be programmed using one of the Flash
downloader “Flash_16x4” solutions offered in the AT91 Library.
When delivered, the Flash memory device contains:
! the Boot Software Program
! the Functional Test Software (FTS)
! the Flash Uploader
! the power-down function
! the Angel Debug Monitor
! a default user boot with a default application (LED Swing Application)
The Boot Software Program and Functional Test Software (FTS) are in sectors 0 and 1
of the Flash. These sectors are not locked in order to provide an easy on-board
upgrade. The user must avoid overwriting these sectors.
The Boot Software Program configures the AT91M42800A, and thus controls the memory and other board components.
The Boot Software Program is started at reset if JP1 is in the STD position. If JP1 is in
the USER position, the AT91M42800A boots from address 0x01100000 in the Flash,
which must have a user-defined boot.
The Boot Software Program first initializes the master clock frequency at 32.768 MHz.
The EBI then executes the REMAP procedure and checks the state of the buttons as
described below.
! When the SW1 button is pressed:
– All the LEDs light up together.
– The D1 LED remains lit when SW1 is released.
– The Functional Test Software (FTS) is started.
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The On-board Software
! When the SW2 button is pressed:
– Reserved
! When the SW3 button is pressed:
– All the LEDs light up together.
– The D3 LED remains lit when SW3 is released.
– The Flash uploader is activated.
! When the SW4 button is pressed:
– All the LEDs light up together.
– The D4 LED remains lit when SW4 is released.
– The power-down function is activated.
! When no buttons are pressed:
– Branch at address 0x01006000.
– The Angel Debug Monitor starts from this address by recopying itself in
external SRAM.
3.3 Programmed Default Memory Mapping
Table 3-1 defines the mapping defined by the boot program.
Table 3-1. Memory Map
Part Name Start Address End Address Size Device
U1 0x01000000 0x011FFFFF 2M Bytes Flash
AT49BV162A
U2 - U3 0x02000000 0x0203FFFF 256K Bytes SRAM
The Boot Software Program, Functional Test Software (FTS), Flash Uploader and the
power-down demonstration are in sectors 0 and 1 of the Flash device. Sectors 3 to 8
support the Angel Debug Monitor.
Sector 24 at address 0x0110 0000 can be programmed with a user application to be
debugged. This sector is mapped at address 0x0100 0000 (or 0x0 after a reset) when
the jumper JP1 is in the USER position.
3.4 Flash Uploader The Flash Uploader included in the EB42 Boot Software is the same Flash Uploader
factory-programmed in the Flash-based AT91 devices, the AT91FR4042 and the
AT91FR40162/S. The Flash Uploader allows programming to Sector 24 of Flash
through a serial port. Either of the on-chip USARTs can be used by the Flash Uploader.
To boot from the application downloaded in Sector 24, the downloading address must
be 0x01100000. The boot starts the Flash Uploader if the SW3 button is pressed at
reset.
The procedure is as follows:
1. Connect the Serial A or B port of the AT91EB42 Evaluation Board to a host PC
Serial port using the straight serial cable provided.
2. Start the AT91Loader.exe program available in the AT91 Library on the host computer. The AT91 Loader must be configured beforehand. See the “Readme.pdf”
file in folder <CDROM>\ToolBox\host_tools\Dev PC windev\AT91Loader\Doc.
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The On-board Software
3. Check JP1 is in STD position. Power-on or press RESET, holding down the SW3
button simultaneously. Wait for all LEDs to light up together and then release
SW3. LED3 remains lit. If the AT91Loader is configured in automatic mode, the
download starts. Wait for the download to end.
4. Put JP1 in USER position and press RESET button. The application downloaded
starts.
For further details, see the application note “Crystal Oscillator and PLL Considerations
for AT91M42800A and AT91M55800A”, literature number 1740A. A PLL Filter Calculator Tool is also available. See “Automatic_calculation_xls.zip”.
3.5 Power-down Demonstration
3.6 Angel Debug Monitor
The AT91EB42 Evaluation Board is delivered with a battery unit to supply the board
when the main power supply is removed. The aim of the power-down demonstration is
to save the battery unit. When the power-down function is started, the main clock of the
AT91M42800A is switched to the slow clock oscillator at 32.768 kHz. The processor is
put in IDLE mode and all peripheral clocks are turned off. The power-down mode is indicated by LED4 flashing every 10 seconds. The boot starts the power-down
demonstration if the SW4 button is pressed at reset.
The procedure is as follows:
1. Power-on or press RESET, holding down the SW4 button simultaneously.
2. Wait for all LEDs to light up and then release SW4. LED4 remains lit for
3 seconds and light off. Then LED4 flashes every 10 seconds.
3. Press SW4 or the reset button to re-start the board. When SW4 is pressed,
the power-down demonstration re-configures the AT91M42800A to run at
32.768 MHz and branches to Angel.
The Angel Debug Monitor is located in the Flash from 0x01006000 up to 0x01011FFF.
The boot program starts it if no button is pressed at reset.
When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by
Angel is from 0x02020000 to 0x0203FFFF, i.e., the highest half part of the SRAM.
The Angel on the AT91EB42 Evaluation Board can be upgraded regardless of the version programmed on it.
Note that if the debugger is started through ICE while the Angel monitor is on, the
Advanced Interrupt Controller (AIC) and the USART channel are enabled.
3.7 Programmed Default Speed
AT91EB42 Evaluation Board User Guide 3-3
As the speed of the AT91M42800A is programmable, the Boot Software Program initializes the device to run as fast as possible, i.e., at 32.768 MHz. The Boot Software
Program and the Functional Test Software are run at this speed. When Angel is started,
it also runs at 32.786 MHz and the user should not modify this frequency without reprogramming the speed of the USARTs.
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The On-board Software
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Section 4
Circuit Description
4.1 AT91M42800A Processor
4.2 Expansion Connectors and JTAG Interface
4.2.1 I/O Expansion Connector
Figure 6-1 on page 6-2 shows the AT91M42800A. The footprint is for a 144-pin TQFP
package.
Strap CB20 enables the user to choose between the standard ICE debug mode and the
JTAG boundary scan mode of operation.
The operating mode is defined by the state of the JTAGSEL input detected at reset.
Jumper JP5 (see Figure 6-8 on page 6-9 in Section 6, “Appendix B – Schematics”) can
be removed by the user to allow measurement of the consumption of the whole microcontroller (V
microcontroller consumption (V
The two expansion connectors, I/O expansion connector and EBI expansion connector,
and the JTAG interface are described below.
The I/O and EBI expansion connectors’ pinout and position are compatible with other
AT91 evaluation boards (except the I/O expansion connector pinout and position of the
EB40) so that users can connect their prototype daughter boards to any of these evaluation boards.
The I/O expansion connector makes the general-purpose I/O (GPIO) lines, VCC3V3
and Ground, available to the user. Configuration straps CB2, CB3, CB4, CB11, CB13,
CB14, CB15, CB17, CB18 and CB19 are used to select between the I/O lines being
used by the evaluation board or by the user via the I/O expansion connector.
DDIO
and V
DDCORE
). Jumper JP8 can be removed to measure the core
DDCORE
).
4.2.2 EBI Expansion Connector
4.2.3 JTAG Interface An ARM
AT91EB42 Evaluation Board User Guide 4-1
The schematic (see Figure 6-4 on page 6-5 in Section 6, “Appendix B – Schematics”)
also shows the bus expansion connector. The 32 x 2 connector allows the user to
access the data bus, all control bus signals and oscillator output. VCC3V3 and ground
are also available on this connector.
Configuration strap CB1, when open, allows the user to connect the EBI expansion connector to the MPI expansion connector of an AT91EB63 evaluation board without any
conflict.
®
-standard 20-pin box header (P5) is provided to enable connection of an ICE
interface to the JTAG inputs on the AT91. This allows code to be developed on the
board without using system resources such as memory and serial ports.
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Circuit Description
4.3 Memories The schematic (see Figure 6-3 on page 6-4 in Section 6, “Appendix B – Schematics”)
shows one AT49BV162A 2M bytes 16-bit Flash, one AT45DB321 4M bytes serial
DataFlash, one AT24C512 64K bytes EEPROM, one AT25256 32K Bytes EEPROM
and two 128K/512K x 8 SRAM devices.
Note: The AT24C512 64K byte EEPROM and the AT25256 32K byte EEPROM are
not mounted.
4.4 Analog-to-digital Converter
4.5 Power and Crystal Quartz
An on-board 4-channel, 10-bit ADC device (TLV1504 by Texas Instruments) is featured
on the AT91EB42. This device is interfaced to the AT91M42800A via the SPIA peripheral and embeds its voltage reference equal to 2V. Four channels are used on the
AT91EB42 for the following measurements:
! Channel 0 is used to measure the temperature near the 32.768 kHz crystal.
! Channel 1 is dedicated to supervise the External Power Supply.
! Channel 2 is dedicated to supervise the Battery Power Supply.
! Channel 3 is dedicated to supervise the V
Each ADC channel is fitted on the I/O extension connector and can be used in other
applications. For this reason, each ADC input can be taken away from its function by its
appropriate jumper.
The AT91M42800A master clock is derived from a 32.768 kHz crystal. The on-chip lowpower oscillator together with two PLL-based frequency multipliers and the prescaler
results in a programmable master clock between 500 Hz and 33 MHz. A temperature
sensor has been placed near the 32.768 kHz crystal and the analog signal output has
been fitted to Channel 0 of the on-board ADC.
Two sets of components for the PLL filters are fitted by default on the board (see Figure
6-6 on page 6-7 in Section 6, “Appendix B – Schematics”). They are calculated to provide a 16.77 MHz (PLLA: multiplier factor of 512 and settling time of 600 µs) or a 32.768
MHz (PLLB: multiplier factor of 1000 and settling time of 6 ms) master clock frequency.
DDCORE
.
For further details, see the application note “Crystal Oscillator and PLL Considerations
for AT91M42800A and AT91M55800A”, literature number 1740A. A PLL Filter Calculator Tool is also available. See “Automatic_calculation_xls.zip”.
The voltage regulator provides 3.3V to the board and will light the red POWER LED
(D11) when operating.
Power can be applied via the 2.1 mm connector to the regulator in either polarity
because of the diode-rectifying circuit. Another regulator allows the user to power the
AT91M42800A core with 3.3V or 1.8V by means of the JP8 jumper.
All functions can be supplied by the on-board battery. A connector permits the user to
disconnect the battery. The type of battery and connection to be used are shown in Section 6 of this user guide. This type of battery will ensure the power supply of the board
for approximately one hour. A battery fast-charge controller is provided on-board to
charge it and maintains the full charge. The user is warned while the fast-charge is
started via the on-board indicator (D28) or a logical signal on I/O port PB18.
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Circuit Description
4.6 Push-buttons, LEDs, Reset and Serial Interfaces
The IRQ0, TIOA0, PB6 and PB21 switches are debounced and buffered.
A supervisory circuit has been included in the design to detect and consequently reset
the board when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be
changed depending on the board production series. The supervisory circuit also provides a debounced reset signal. This device can also generate the reset signal in case
of watchdog timeout as the pin NWDOVF of the AT91M42800A is connected to its input
MR
.
The assertion of this reset signal will light up the red RESET LED (D10). By pressing the
CLEAR RESET push-button (S1), the LED can be turned off.
Another supervisory circuit initializes separately the microcontroller-embedded
JTAG/ICE interface when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed, depending on the board production series. These separated reset
lines allow the user to reset the board without resetting the JTAG/ICE interface while
debugging.
The schematic (see Figure 6-5 on page 6-6 in Section 6, “Appendix B – Schematics”)
also shows eight general-purpose LEDs connected to Port B PIO pins (PB8 to PB15).
Two 9-way D-type connectors (P3/4) are provided for serial port connection.
Serial Port A (P3) is used primarily for host PC communication and is a DB9 female con-
nector. TXD and RXD are swapped so that a straight-through cable can be used. CTS
and RTS are connected together, as are DCD, DSR and DTR.
Serial Port B (P4) is a DB9 male connector with TXD and RXD obeying the standard
RS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected.
LEDs are connected to the TX and RX signals of both serial ports and show activity on
these serial links.
A MAX3223 device (U10) and associated bulk storage capacitors provide RS-232 level
conversion.
4.7 Layout Drawing The layout diagram (see Figure 6-1 on page 6-2 in Section 6, “Appendix B – Schemat-
ics”) shows an approximate floor plan for the board. This has been designed to give the
lowest board area, while still providing access to all test points, jumpers and switches on
the board.
The board is provided with four mounting holes, one at each corner, into which feet are
attached. The board has two signal layers and two power planes.
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Circuit Description
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Section 5
Appendix A – Configuration Straps
5.1 Functional Pin Assignment
The following table provides a list of each peripheral used on the AT91EB42 Evaluation
Board.
Table 5-1. Functional Pin Assignment
Pin Designation Function Used on the AT91EB42
NCS0 Chip Select signal for the Flash Memory (AT49BV162A)
NCS1 Chip Select signal for the Static RAMs
PB7/TIOA0 General I/O input line for the User Interface Push-button (SW1)
PA0/IRQ0 General I/O input line for the User Interface Push-button (SW2)
PB6/TCLK0 General I/O input line for the User Interface Push-button (SW3)
PB21/TCLK5 General I/O input line for the User Interface Push-button (SW4)
PB8/TIOB0 General I/O output line for the User Interface Light Indicator (Led D1)
PB9/TCLK1 General I/O output line for the User Interface Light Indicator (Led D2)
PB10/TIOA1 General I/O output line for the User Interface Light Indicator (Led D3)
PB11/TIOB1 General I/O output line for the User Interface Light Indicator (Led D4)
PB12/TCLK2 General I/O output line for the User Interface Light Indicator (Led D5)
PB13/TIOA2 General I/O output line for the User Interface Light Indicator (Led D6)
PB14/TIOB2 General I/O output line for the User Interface Light Indicator (Led D7)
PB15/TCLK3 General I/O output line for the User Interface Light Indicator (Led D8)
PA6/TXD0 To the RS232 Transceiver device and dedicated for the Serial A
socket
PA7/RXD0 To the RS232 Transceiver device and dedicated for the Serial A
socket
PA9/TXD1/NTRI To the RS232 Transceiver device and dedicated for the Serial B
socket
PA10/RXD1 To the RS232 Transceiver device and dedicated for the Serial B
socket
PB18/TCLK4 General I/O input line to detect the fast-charge mode for the battery
PB16/TIOA3 General I/O output line to generate SCL signal dedicated for a two
wire bus access
AT91EB42 Evaluation Board User Guide 5-1
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Appendix A – Configuration Straps
Table 5-1. Functional Pin Assignment (Continued)
Pin Designation Function Used on the AT91EB42
PB17/TIOB3 General I/O input/output line to generate SDA signal dedicated for a
two wire bus access
PA13/MOSIA To generate SPI bus Access to the DataFlash, EEPROM and ADC
devices
PA12/MISOA To generate SPI bus Access to the DataFlash, EEPROM and ADC
devices
PA11/SPCKA To generate SPI bus Access to the DataFlash, EEPROM and ADC
devices
PA14/NPCSA0/NSSA Chip Select signal for the SPI device: DataFlash
PA15/NPCSA1 Chip Select signal for the SPI device: EEPROM
PA16/NPCSA2 Chip Select signal for the SPI device: ADC
PA3/IRQ3 Interrupt line from the ADC device
5.2 Configuration Straps (CB1 - 23, JP1 - 8)
By adding the I/O and EBI expansion connectors, users can connect their own peripherals to the evaluation board. These peripherals may require more I/O lines than available
while the board is in its default state. Extra I/O lines can be made available by disabling
some of the on-board peripherals or features. This is done using the configuration straps
detailed below. Some of these straps present a default wire (notified by the default mention) that must be cut before soldering the strap.
CB1 On-board PB5/A23/CS4 Signal
(1)
Closed
Open AT91 PB5/A23/CS4 signal is not connected to the EBI expansion connector
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
CB3 On-board IRQ3 Signal
(1)
Closed
Open AT91 IRQ3 signal is not connected to the external ADC (U20 pin 4). This
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
AT91 PB5/A23/CS4 signal is connected to the EBI expansion connector
(P1-B21).
(P1-B21).
This authorizes users to connect the EBI expansion connector of this board
to the MPI expansion connector of an AT91EB63 Evaluation Board without
conflicting problems.
the wire on the board.
AT91 IRQ3 signal is connected to the external ADC (U20 pin 4).
authorizes the user to use this signal for other applications via the I/O
Expansion connector (P2 - A8).
the wire on the board.
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Appendix A – Configuration Straps
CB4 ADC Chip Select Line
Closed
(1)
ADC (U20) control lines enabled.
Open ADC (U20) control lines disabled. This authorizes users to connect the
corresponding chip select line to their own resources via the I/O expansion
connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB5 Standard Power Supply Supervisory Enabling
Closed
(1)
Standard power supply is supervised by the ADC (U20) channel 1 via a
resistor bridge. The ratio is set to 0.1013 so that the standard power supply
can be supervised up to 15V.
Open Standard power supply is not connected to the ADC (U20) channel 1. This
allows the user to connect the corresponding ADC channel to their own
resources via the I/O expansion connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB6 VDDCORE Voltage Monitoring
Closed
(1)
The ADC channel 3 is connected at the V
power supply. This allows
DDCORE
the user to tune the frequency clock according to the core voltage.
Open The ADC channel 3 is not connected and it is available on the I/O expansion
connector for user application.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB7 Battery Power Supply Supervisory Enabling
Closed
(1)
Battery power supply is supervised by the ADC (U20) channel 2 via a
resistor bridge. The ratio is set to 0.24 so that the battery voltage range can
be supervised (5.5V to 6.2V).
Open Battery power supply is not connected to the ADC (U20) channel 2. This
authorizes the user to connect the corresponding ADC channel to their own
resources via the I/O expansion connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB8 Ambient Temperature Monitoring
Closed
(1)
The ADC channel 0 is connected to a temperature sensor near the
32.768 kHz crystal. This allows the user to evaluate the frequency drift
according to the ambient temperature.
Open The ADC channel 0 is not connected and it is available on the I/O expansion
connector for the user application.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
AT91EB42 Evaluation Board User Guide 5-3
1708C–ATARM–12-May-05
Page 22
Appendix A – Configuration Straps
CB9 On-board Boot Chip Select
Closed
(1)
AT91 NCS0 select signal is connected to the Flash memory.
Open AT91 NCS0 select signal is not connected to the Flash memory. This
authorizes the user to connect the corresponding select signal to their own
resources via the EBI expansion connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB10 Flash Reset
Closed
(1)
The on-board reset signal is connected to the Flash NRESET input.
Open The on-board reset signal is not connected to the Flash NRESET input.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB12 Boot Mode Strap Configuration
Open
(1)
BMS AT91 input pin is set for the microcontroller to boot on an external 16-bit
memory at reset.
Closed BMS AT91 input pin is set for the microcontroller to boot on an external 8-bit
memory at reset.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB13, CB14 Two-wire Interface EEPROM Enabling
Closed
(1)
EEPROM communication enabled.
Open EEPROM communication disabled. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB15 Serial DataFlash Enabling
Closed
(1)
AT91 NPCSA0 select signal is connected to the serial DataFlash memory.
Open AT91 NPCSA0 select signal is not connected to the serial DataFlash
memory. This authorizes users to connect the corresponding PIO to their
own resources via the I/O expansion connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB16 Control Line for the Internal Oscillator
Closed Disables the internal low frequency oscillator.
(1)
Open
Enables the internal oscillator.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
5-4 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 23
Appendix A – Configuration Straps
CB17 SPI EEPROM Enabling
Closed
(1)
EEPROM communication enabled.
Open EEPROM communication disabled. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB18 R(eturn) TCK ICE Signal Synchronization
(1)
1 - 2
The TCK and RTCK ICE signals are not synchronized with MCKO.
2 - 3 The TCK signal from the JTAG interface can be synchronized with the MCKO
signal and returns to the JTAG interface (RTCK).
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB19 PB18 End of Fast Charge Signal
Closed
(1)
AT91 PB18 signal is connected to the battery charger (U16), NFASTCHG
output pin.
Open AT91 PB18 signal is not connected to the battery charger (U16), NFASTCHG
output pin. This authorizes users to connect the corresponding signal to their
own resources via the I/O expansion connector.
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB20 JTAGSEL
1 - 2
(1)
AT91 standard ICE debug feature enabled
2 - 3 IEEE 1149.1 JTAG boundary scan feature enabled
Note: 1. Hardwired default position: To cancel this default configuration, the user should cut
the wire on the board.
CB21, CB22, CB23 Charger Device (U16): Programming the Battery Number of Cells
Number of Cells CB21 CB22 CB23
1 Open Closed Closed
2 Open Open Closed
4 Closed Open Closed
(1)
5
Open Closed Open
6 Open Open Open
8 Closed Open Open
AT91EB42 Evaluation Board User Guide 5-5
1708C–ATARM–12-May-05
Page 24
Appendix A – Configuration Straps
JP1 User or Standard Boot Selection
2 - 3 The first half part of the Flash memory is accessible at its base address.
1 - 2 The second half part of the Flash memory is accessible at its base address.
This authorizes users to download their own application software in this part
and to boot on it.
JP2 Push Button Enabling
Open SW1-4 inputs to the AT91 are valid.
Closed SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
JP3 User or Standard Boot Selection
Open The RS-232 transceivers are enabled.
Closed The RS-232 transceivers are disabled. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
JP4 PME Function (Protect Mode Enable)
Closed The AT91M42800A is in Protect Mode.
Open This is the default mode on the AT91EB42. The AT91M42800A internal
registers are accessible in all processor modes.
JP8 Core Power Supply Selection
2 - 3 The AT91 core is powered by 3.3V power supply.
1 - 2 Not supported on the current microcontroller revision.
5-6 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 25
Appendix A – Configuration Straps
5.3 Power Consumption Measurement Strap (JP5)
5.4 Ground Links (JP6)
5.5 Increasing Memory Size
The JP5 strap enables connection of an ammeter to measure the AT91M42800A global
consumption (V
DDCORE
and V
DDIO
) when V
DDCORE
power supply is derived from V
DDIO
(JP8 in 3V3 position). Core consumption can be measured by connecting another
ammeter between JP8 1 - 2 or 2 - 3, depending on the power supply used to power the
core.
The JP6 strap allows the user to connect the electrical and mechanical grounds.
The AT91EB42 Evaluation Board is supplied with two 128K x 8 SRAM memories. If,
however, the user needs more than 256K bytes of memory, the devices can be replaced
with two 512K x 8 3.3V 10/15 ns SRAMs, giving a total of 1024K bytes. The following
references for the 512K x 8 SRAM are available.
Manufacturer Reference
Samsung KM68V4002BJ-15 in 36-SOJ-400 package
IDT 71V424-15 in 36-pin 400-mil SOJ package (SO36-1)
AT91EB42 Evaluation Board User Guide 5-7
1708C–ATARM–12-May-05
Page 26
Appendix A – Configuration Straps
5-8 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 27
Appendix B – Schematics
6.1 Schematics The following schematics are appended:
! Figure 6-1 – PCB Layout
! Figure 6-2 – AT91EB42 Blocks Overview
! Figure 6-3 – EBI Memories
! Figure 6-4 – I/O and EBI Expansion Connectors
! Figure 6-5 – Push-buttons, LEDs and Serial Interface
! Figure 6-6 – AT91M42800A
! Figure 6-7 – Reset and JTAG Interface
! Figure 6-8 – Power Supply and Battery Charger
! Figure 6-9 – SPI Memories, Two-wire Interface Memories and SPI ADC
Section 6
The pin connectors are indicated on the schematics:
! P1 = EBI Expansion Connector (Figure 6-4)
! P2 = I/O Expansion Connector (Figure 6-4)
! P3 = Serial A (Figure 6-5)
! P4 = Serial B (Figure 6-5)
! P5 = JTAG Interface (Figure 6-7)
AT91EB42 Evaluation Board User Guide 6-1
Rev. 1708C–ATARM–12-May-05
Page 28
Appendix B – Schematics
Figure 6-1. PCB Layout
6-2 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 29
Figure 6-2. AT91EB42 Blocks Overview
INPUT / OUTPUT ON BOARD
Serial Connectors / P.B. / LED
PB[6..15]
PA[6..7]
PA0
PA[9..10]
SUPPLY and RTC SA VE
power supply / battery
PB18
SERIAL MEMORIES
SERIAL MEMORIES
PB17
MOSIA
MISOA
SPCKA
PB16
NRST
NPCSA0
NPCSA1
VIN[1..4]
NPCSA2
IRQ3
PB19
PB20
EXTENSIONS CONNECTORS
Extension Connectors
IOB_[0..57]
EBI_[0..42]
EBI MEMORIES
memories connected on EBI
EBI_[0..42]
A20
PB22
MICROCONTROLLER
micro / Rst / Wchdog / JTAG co.
EBI_[0..42]
IOB_[0..53]
IOB_13
IOB_12
IOB_11
IOB_47
IOB_46
EBI_[0..42]
EBI_[0..42]
IOB_[0..57]
IOB_[0..57] IOB_[0..57]
IOB_[36..45]
IOB_[0..57]
IOB_32
IOB_[0..57]
EBI_[0..42]
EBI_41
IOB_52
EBI_[0..42]
IOB_14
IOB_15
IOB_[0..53]
IOB_[54..57]
IOB_16
IOB_3
IOB_49
IOB_50
IOB_[6..7]
IOB_0
IOB_[9..10]
IOB_[0..57]
IOB_48
Appendix B – Schematics
AT91EB42 Evaluation Board User Guide 6-3
1708C–ATARM–12-May-05
Page 30
Appendix B – Schematics
Figure 6-3. EBI Memories
A13
24
D425D526D629D7
13
NWR1
A13
24
D425D526D629D7
13
NWR0
A12
A11
A514A615A716A817A9
WE
A6
A5
A11
A12
A514A615A716A817A9
WE
A5
A6
VCC3V3VCC3V3VCC3V3VCC3V3
A9
A10
19
NC
A1020A1121A1222A1323A14
IDT71V424S10Y
18
A8
A19
A10
A9
19
NC
A1020A1121A1222A1323A14
IDT71V424S10Y
18
A8
A7
A19
NRD
D15
D13
D12
A14
A16
A15
A17
36
30
33
35
31
28
27
OE
NC
A1532A16
A1734A18
GND
VCC
GND
A01A12A23A34A4
U3
A18
36
1Mbytes ( two 512kX8 ) SRAM with two footprints or
256kbytes ( two 128kX8 ) SRAM with two footprints.
NC
128k 128k
512k 512k
A01A12A23A34A4
U2
A18
VCC
CS
D18D211D3
D0
9
6
5
7
10
12
A1
A2
A3A7A4
layout for SOJ 400mil.
A15
A16
A17
33
35
A1734A18
A2
A3
A1
D11
D8
D10
D9 D14
NCS1
VCC3V3 VCC3V3
NRD
D6
D5
D4
D7
A14
30
31
27
28
OE
A1532A16
GND
VCC
GND
VCC
CS
D18D211D3
D0
9
5
7
6
10
12
A4
D0
D3
D1
D2
NCS1
VCC3V3 VCC3V3
C4
100nF
A17
44
42
41
NC43NC
NC
128k
512k512k
A03A14A25A36A4
NC1NC
U5
2
A1
A18
C3
100nF
C2
100nF
A17
44
42
41
NC43NC
NC
128k
A03A14A25A36A4
NC1NC
U4
2
A1
A18
C1
100nF
VCC3V3VCC3V3
NRD
D14
D15
D13
D12D4
A13
36
OE
CS
D0
9
D8
D7
36
OE
CS
D0
9
D0
34
33
GND
VCC
GND
VCC
D110D213D3
12
11
D9
GND
VCC3V3
D6
33
34
GND
VCC
GND
VCC
D110D213D3
12
11
D1
VCC3V3
A12
30
D431D532D635D7
A516A617A718A819A9
WE
15
14
A5
A6
D11
D10
NWR1
D5
A11
A13
A12
30
D431D532D635D7
A516A617A718A819A9
WE
14
15
A5
A6 A11
D3
D2
NWR0
A16
A15
39
37
A1538A16
A1740A18
8
7
A4
A3
A2
NCS1
NRD
layout for TSSOP 400mil.
A16
A14 A14
A15
39
37
A1538A16
A1740A18
7
8
A4
A3
A2
NCS1
NCS0CTL4
NCS1CTL6
A9
A10
CTL5 NRST
CTL2 NRD NOEA4CTL1 NWR1 NUB
25
NC23NC24NC
A1026A1127A1228A1329A14
NC21NC
20
22
A7
A8
A19
A10
A9
25
NC23NC24NC
A1026A1127A1228A1329A14
NC21NC
20
22
A8
A7
A19
CTL0 NWR0 NWE
IDT71424S10PH
D[0..15]
A[0..19]
CTL[0..6]
EBI_[0..15]
EBI_[16..35]
EBI_[36..42]
EBI_[0..42]
A20B
STD BOOT
2
3
JP1
jumper_3P
IOB_32
A20
USER BOOT
1
1
1
U6A
74LVC02
2
3
IDT71424S10PH
D[0..15]
D0
D1
I/O029I/O131I/O233I/O335I/O438I/O540I/O642I/O744I/O830I/O9
2Mbytes FLASH ME MORY
A025A124A223A322A421A520A619A718A88A97A106A124A133A142A151A1648A1717A1816A1915NC9NC10NC14NC / Vpp13CE26WE11OE28RESET
U1
A1
A2
A3
A[0..19]
D9
D2
D3
D4
A5
D12
D10
D11
D7
D6
D8
D5
D13
D14
32
43
45
I/O1034I/O1136I/O1239I/O1341I/O14
A11
5
A9A7A6
A8
A12
A15
A14
A13
A16
A17 D15
A10
A11
I/O15
VCC3V3
1 2
A18
A19
VCC3V3
CB24
1 2
A20B
10
C5
100nF
37
47
VCCQ
R1
100k
46
VCC
GND27GND
AT49BV162A
12
NCS0_1
1 2
NRST_1NRST
CB9
CB10
1 2
1 2
NWE
NCS0
NOE
VCC3V3
R2
100k
74LVC02AD
U6C
74LVC02AD
1
U6D
8
9
VCC3V3
13
14
1
100nF
7
11
C89
12
6-4 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 31
AT91EB42 Evaluation Board User Guide 6-5
Figure 6-4. I/O and EBI Expansion Connectors
EBI Extension Connector I/O Extension Connector
PB[0..23]
PA[0..29]
P1A
A1
GND
CTL0
CTL2
PA25
NCS2PB0
VCC3V3
A0
A2
A4
A6
A[0..19]
A10
A12
A14
VCC3V3
A16
A18
CS7PB2
CS5PB4
D0
D2
D4
D6 D7
VCC3V3
D8
D10
D12
D14
A2
NWR0 / NWE
A3
NRD / NOE
A4
PA25 / MCK0
A5
NCS0
A6
PB0 / NCS2
A7
VCC3V3
A8
A0 / NLB
A9
A2
A10
A4
A11
A6
A12
GND
A13
A8
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A8
A10
A12
A14
VCC3V3
A16
A18
PB2 / A20 / CS7
PB4 / A22 / CS5
GND
D0
D2
D4
D6
VCC3V3
D8
D10
D12
D14
GND
EBI Ext. Con.
P1B
NWR1 / NUB
PB1 / NCS3
PB3 / A21 / CS6
PB5 / A23 / CS4
EBI Ext. Con.
NWAIT
NCS1
NRST
VCC3V3
VCC3V3
GND
GND
GND
GND
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
D1
D3
D5
D7
D9
D11
D13
D15
CTL[0..6]
B1
B2
B3
B4
-
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
D[0..15]
A[0..19]
CTL[0..6]
CTL1
CTL3
NCS1 CTL6NCS0CTL4
VCC3V3
CS4_1
VCC3V3
NCS3
CB1
PB1
A[0..19]
CS6 PB3
CS4 PB5
PB[0..23]
CTL5
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
1 2
D1
D3 PA20
D5
D9
D11
D13
D15
EBI_[0..15]
EBI_[16..35]
EBI_[36..42]
P2B
PB6 / TCLK0
PB7 / TIOA0
PB8 / TIOB0
PB9 / TCLK1
PB10 / TIOA1
PB11 / TIOB1
PB12 / TCLK2
PB13 / TIOA2
PB14 / TIOB2
PB15 / TCLK3
PB16 / TIOA3
PB17 / TIOB3
PB18 / TCLK4
PB19 / TIOA4
PB20 / TIOB4
PB21 / TCLK5
PB22 / TIOA5
PB23 / TIOB5
PA5 / SCK0
PA6 / TXD0
PA7 / RXD0
PA8 / SCK1
PA9 / TXD1 / NTRI
PA10 / RXD1
PA22 / NPCSB1
PA23 / NPCSB2
PA24 / NPCSB3
PA12 / MISOA
PA13 / MOSIA
PA11 / SPCKA
PA14 / NPCSA0 / NSSA
PA15 / NPCSA1
I/O Ext. Conn.
IOB_[0..29]
IOB_[30..53]
IOB_[54..57]
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB[0..23]
PA5
PA6
PA7
PA8
PA9
PA10
PA22
PA23
PA24
PA12
PA13
PA11
PA14
PA15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
PA0
PA1
PA2
PA3
PA4
PA28
PA29
PA26
VIN[1..4]
PA18
PA19
PA21
PA27
PA17
PA16
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VIN1
VIN2
VIN3
VIN4
P2A
A1
GND
A2
VCC3V3
A3
PA0 / IRQ0
A4
PA1 / IRQ1
A5
GND
A6
PA2 / IRQ2
A7
VCC3V3
A8
PA3 / IRQ3
A9
GND
A10
PA4 / FIQ
A11
VCC3V3
A12
PA28 / HOLDA
A13
PA29 / HOLD
A14
VCC3V3
A15
PA26
A16
GND
A17
VIN1
A18
VIN2
A19
VIN3
A20
VIN4
A21
GND
A22
PA18 / SPCKB
A23
PA19 / MISOB
A24
PA20 / MOSIB
A25
PA21 / NPCSB0 / NSSB
A26
PA27 / BMS
A27
GND
A28
PA17 / NPCSA3
A29
PA16 / NPCSA2
A30
GND
A31
VCC3V3
A32
GND
I/O Ext. Conn.
PA[0..29]
PB[0..23]
VIN[1..4]
EBI_[0..42] IOB_[0..57]
Appendix B – Schematics
1708C–ATARM–12-May-05
Page 32
Appendix B – Schematics
Figure 6-5. Push-buttons, LEDs and Serial Interface
Usart 0:
SERIAL A
Usart 1:
SERIAL B
PB[6..15]
PB[6..15]
VCC3V3
VCC3V3
100R
100R
R6
Red LED
D1
D2 R7
18
EN
U8
12468
PB8
R43
100k
R42
100k
VCC3V3
16
PB9
100R
D3 R8
14
PB10
VCC3V3
100R
D4 R9
12
PB11
VCC3V3
VCC3V3
VCC3V3
VCC3V3
100R
100R
100R
R11
R12
D5 R10
D6
D7
579
EN
1911131517 3
PB14
PB12
PB13
PB21
VCC3V3
100R
D8 R13
VCC3V3
20
10
GND SIGNAL
PB15
R44
R45
74LV244D
C13
100k
100k
VCC3V3
100nF
VCC3V3
P3
RTS0
DSR0
DCD0
TX0
100nF
C17
VCC3V3
19
VCC
C16
100nF
18
GND
C1+2C1-4C2+5C2-
Sub D 9b F
C25
594837261
C21
22pF
CTS0
C20
DTR0
22pF
RX0
100nF
C19
3
7
V-
TP 33
V+
T1OUT17T2OUT
T1IN13T2IN
6
P4
10nF
C24
22pF
C23
22pF
8
9
R1IN16R2IN
R1OUT15R2OUT
10
12
20
11
INVALID
FORCEOFF
EN1FORCEON
14
RX1
U10
Sub D 9b M
594837261
TX1
C27
22pF
C26
22pF
VCC3V3
MAX3223EC AP
VCC3V3
VCC3V3
VCC3V3
2
JP2
jumper_NO
VALBP
R4
100K
R3
100K
1
VALBP VALBP
TIOA0PB7
IRQ0PA0
VCC3V3
PB21 TCLK5
PB6 TCLK0
3
6
8
5109
11
13
12
VCC3V3
VCC3V3
14
C12
100nF
7
1 2
VCC3V3
VCC3V3
C14
SW3
VCC3V3
C15
47nF
SW4
47nF
TP 33
R15
100K
R14
100K
R5
100k
74LV125D
EN
U9
124
C11
47nF
SW2
TP 33
C10
47nF
SW1
TP 33
C18
100nF
C22
100nF
TXD0PA6
R76
100R
100R
JP3
jumper_NO
RS232 on IOB
D32
VCC3V3
D31
VCC3V3
R17
100K
1
R74
D30
D29
100R
VAL_RS232
VCC3V3
R75
2
VALID
R73
100R
PA9 TX D1
PA7 RXD0
PA7
PA[6..7]
PA[6..7]
PA10 RXD1
PA[9..10]
PA[9..10]
R16
100k
PA0
PA0
6-6 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 33
Figure 6-6. AT91M42800A
Appendix B – Schematics
VCC3V3
R71
JP4
CB16
R48
12
1 2
VCC3V3
VT
100K
PA29
NWAIT CTL3
R46
VCC3V3
100K
PA[0..29]
100K
C43
1 2
XOUT
PA26
PLLRCA
PLLRCB
PA27
PA28
PA29
JTAG[0..4]
JTAG[0..4]
120R 1%
R21
680R 1%
PLL filter B
R20
PA17
PA18
VDDIO
99
98
97
96
GND
VDDIO
PA19 / MISOB
PA18 / SPCKB
PA17 / NPCSA3
U11
AT91M42800A
VDDIO12GND
13
VDDIO
1 2
1µF 10%
C48
1 2
1 2
1 2
C47
100nF 10%
PLLRCB
Guard ring
PA16
PA14
PA15
PA13
92
93
94
95
PA15 / NPCSA1
PA16 / NPCSA2
PA14 / NPCSA0 / NSSA
TQFP 144
PA10
PA9
PA12
PA11
91
90
89
88
PA10 / RXD1
PA12 / MISOA
PA13 / MOSIA
PA11 / SPCKA
NWDOVF
JTAGSEL
JTAGSEL
NWDOVF
PA8
PA7
VDDIO
87
86
85
84
GND
VDDIO
PA8 / SCK1
PA7 / RXD0
PA9 / TXD1 / NTRI
GND
VDDIO
25
24
VDDIO
NRST
CTL5
PA6
PA5
PA4
81
82
83
PA4 / FIQ
PA6 / TXD0
PA5 / SCK0
PB3 / A21 / CS6
PB4 / A22 / CS5
27
28
29
PB3
PB2
PB4
IOB_[0..29]
PA[0..29]
PA1
PA3
PA2
PA0
77
78
79
80
PA1 / IRQ1
PA2 / IRQ2
PA3 / IRQ3
PB5 / A23 / CS430D031D132D233D3
PB5
D0
D1
PB23
PB22
75
76
PA0 / IRQ0
PB23 / TIOB5
VDDCORE
PB21 / TCLK5
PB20 / TIOB4
PB19 / TIOA4
PB18 / TCLK4
PB17 / TIOB3
PB16 / TIOA3
PB15 / TCLK3
PB14 / TIOB2
PB13 / TIOA2
PB12 / TCLK2
PB11 / TIOB1
PB10 / TIOA1
PB9 / TCLK1
PB8 / TIOB0
PB7 / TIOA0
PB6 / TCLK0
34
D2
D3
IOB_[30..53]
PB[0..23]
74
PB22 / TIOA5
VDDIO
GND
VDDIO
GND
VDDIO
GND
GND
VDDCORE35VDDIO
36
1 2
C46
100nF 10%
100R 1%
1 2
C29
VDDIO
100nF
111
112
113
114
116
118
VDDIO
122
123
124
125
126
127
128
129
130
131
VDDIO
134
135
136
137
138
139
140
141
142
109
110
115
117
119
120
121
132
133
143
144
VDDIO
C30
100nF
R19
1K50 1%
PLL filter A
1 2
1 2
R18
C45
10nF 10%
PLLRCA
Guard ring
PA25
PA20
PA22
PA23
PA21
PA19
PA24
VDDCORE
100
101
102
103
104
105
106
108
107
VDDIO
VDDCORE
PA25 / MCKO
GND
GND
PA26
GND
XIN
XOUT
GND
PLLRCA
VDDPLL
PLLRCB
VDDPLL
VDDIO
GND
NWDOVF
PA27 / BMS
JTAGSEL
TMS
TDI
TDO
TCK
NTRST
NRST
PA28
VDDIO
GND
PA29 / PME
NWAIT
NOE / NRD
NWE / NWR0
NUB / NWR1
NCS0
NCS1
PB0 / NCS2
PB1 / NCS3
VDDCORE
VDDIO
PA20 / MOSIB
PA22 / NPCSB1
PA23 / NPCSB2
PA24 / NPCSB3
PA21 / NPCSB0 / NSSB
GND1GND
NLB / A03A14A25A36A47A58A69A710A811A914A1015A1116A1217A1318A1419A1520A1621A1722A1823A1926PB2 / A20 / CS7
2
Y1
32,768kHz
12
C44
1 2
XIN
Guard ring
100nF
C28
VT
XIN
XOUT
VDDPLL
NWDOVF
JTAGSEL
JTAG2
JTAG1
JTAG4
JTAG3
JTAG0
CTL5 D14
CTL3
CTL2
CTL0
CTL1
CTL4
CTL6
CTL[0..6]
PB0
PB1
PB[0..23]
VDDCORE
D15
D14
D13
D12
D11
D10
GND73GND
D9
D8
D7
D6
D5
D4
C51
72
71
61
60
49
48
38
37
C49
100nF
C50
IOB_[0..53]
100nF
VDDIO
VDDIO
VDDCORE
PB21
70
69
PB20
68
PB19
67
PB18
PB17
66
PB16
65
64
PB15
PB14
63
PB13
62
PB12
59
PB11
58
PB10
57
56
PB9
PB8
55
54
PB7
53
PB6
52
51
50
47
46
45
44
43
42
41
40
39
VDDCORE
100nF
VDDCORE
VDDIO
D15
VDDIO
PB[0..23]
D13
D12
D11
D10
D9
D7
D6
D5
D4
BMS PA27
A0
A5
A7
A2
A6
A4
A8
A3
A1
VCC3V3
A9
A[0..19]
CB12
1 2
Default
boot Mode :
16 Bits
R41
100K
A10D8A12
A11
A17
A13
A15
A14
A19
A16
A18
D[0..15]
A[0..19]
CTL[0..6]
PB[0..23]
EBI_[0..15]
EBI_[16..35]
EBI_[36..42]
EBI_[0..42]
AT91EB42 Evaluation Board User Guide 6-7
1708C–ATARM–12-May-05
Page 34
Appendix B – Schematics
Figure 6-7. Reset and JTAG Interface
JTAG Connector (Front View)
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
6-8 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 35
Figure 6-8. Power Supply and Battery Charger
Appendix B – Schematics
U15
1N914
D12
Vps
VCC3V3
L1
C54
100nF
3
LT1507CS8-3.3
VSW
1
BOOST
VIN
2
VIN_1VIN
D24
VIN1F
F1
2
JP5
10µH
7
SENSE
SYNC5SHTDN
4
1N4001
D17
10MQ100N
D16
10MQ100N
D14
1000m A/30V
VDDPLL
I Vddio
1
jumper_NO
+
C58
D15
1N5817
8
VC
6
GND
C57
10µF / 25V
D19
10MQ100N
D18
10MQ100N
SMT6T15CA
VDDA
100µF / 10V
C60
3,3nF / 10%
JP6
1 2
VDDIO
jumper_NO
VDDCORE
TP2
Test Point Corner 2
TP1
Test Point Corner 1
1 2
BT1
R61
6V / 300mAH
TP3
TP4
10K CTN
34
Test Point Corner 3
Test Point Corner 4
I Vddcore
D26
1N4001
D25
1N4001
Vbatt+
v+
Vbatt+
2
U16
MAX 712/713
Batt+
14
150R
R30
C99
10µF / 25V
C100
DRV
15
V+
1µF 10%
12
V+
Q1
2N6109
C98
10nF
VIN
JUMPER_NO
CB21
5 cel. NiCd
Timeout 264mn
10
PGM29PGM3
Vlimit
FASTCHG
REF
8
1
16
R59
Rth1
D28
CB19
R29
100R
Vbatt-
CB22
1 2
1 2
4
THI5TLO
1K
1 2
1 2
PGM03PGM1
7
Rth2
Vbatt-
JUMPER_NO
CB23
12
GND
Temp
1 2
Batt-
CC
6
R58
C102
R60
C101
R79
1K
2
JP8
jumper_3P
1
Rth2
Rth1
R62
2R49 / 1%
13
C103
10nF
11
1K
10nF
Vbatt-
1K
T˚C
1µF 10%
3
VDDCORE=3.3V
VDDIO
VDDCORE=1.8V
VCC1V8
6
1
C2+
Vout
Vin
C1+3C1-
U17
4
C63
C62
C61
C64
1µF 10%
+
1µF 10%
8
C2-
2
1µF 10%
10µF / 16V
7
GND
SHDN/SS
LT1503CS8-1.8
5
VINplug1
C55
22pF / 25V
J1
C59
22pF / 25V
VINplug2
Jack Dia.2.1mm
VCC3V3
R77
680R
PB18
VCC3V3
AT91EB42 Evaluation Board User Guide 6-9
1708C–ATARM–12-May-05
Page 36
Appendix B – Schematics
Figure 6-9. SPI Memories, Two-wire Interface Memories and SPI ADC
VCC3V3
VCC3V3
VCC3V3
VCC3V3
32
7
VCC
RDY/BUSY1WP3RESET2SCK14SI15SO16CS13NC4NC5NC6NC9NC10NC11NC
U18
R32
100k
R34
100k
MOSIA
MISOA
NRST
C65
SPCKA
100nF
NPCSA0
1 2
CB15
8
NC17NC18NC19NC20NC21NC22NC23NC24NC25NC26NC27NC28NC29NC30NC31NC
GND
Data Flash Memory
AT45DB321-TC
12
R40
100k
VCC3V3
C70
100nF
VCC3V3
R53
100K
R52
100K
3
7
4
8
WP
GND
VCC
HOLD
CS
SO2SI5SCK
U21
6
1
R66
100k
Not Mounted
AT25256W-10SC-2.7
Serial EEPROM memory on SPIA
NPCSA1_1
MOSIA
MISOA
SPCKA
CB17
1 2
C90
100nF
NPCSA1
VDDCORE
R80
9.09K1%
R81
7.5K1%
VCC3V3
VCC3V3
VCC3V3
C106
R69
C7
R67
C6
1µF
750-1%
1µF
750-1%
1µF
VIN4
10
CSTART
VIN2
VIN2
IOB_57VIN3
VIN4VBATT+
9
A3
8
VIN3
1 2
VPS
CB6
TLV1504
R70
2.37K1%
R68
6.65K-1%
VIN[1..4]
IOB_54
12
IOB_56
IOB_55
+
NRST
MISOA
MOSIA
SPCKA
IOB_14
R65
100K
100nF
C67
18
19
20
WP
VCC
A12A0
1
NC3NC4NC5NC6NC7NC8NC
U19
10
NC13NC14NC15NC16NC17NC
GND
TWCK
TWD
9
12
11
Not Mounted
AT24C512W1-10SC-2.7
CB4
1 2
NPCSA2
C104
U20
Serial EEPROM memory on PIO
R31
100k
CB13
R51
100K
1 2
TWD
PB17
CB14
1 2
TWCK
PB16
VCC3V3 VCC3V3
C110
U23
100nF
1
VCC
3
GND
Vout
LM61BIM3
2
VCC3V3
10µF / 16V
12
15
16
CS
REFP
SDO1SDI2SCLK3IOC(INT)4VCC5A06A17A2
MISOA
MOSIA
14
REFM
SPCKA
C105
13
CB3
1 2
100nF
FS
IRQ3
11
GND
PWDN
VIN1
VIN1
CB812CB512CB7
VCC3V3
6-10 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 37
Section 7
Appendix C – Bill of Materials
Figure 7-1. Bill of Materials for AT91EB42
Item Qty. Reference Part Designation Manufacturer
1 1 BT1 6V battery NiCd pack battery 6V – 300 mAh Saft
2 2 JP1, JP8 3-point jumper Jumper
3 2 JP4, JP5 2-point Jumper
4 CB24(*) 2-point strap Soft-soldering jumper
5 30 C1, C2, C3, C4, C5, C12, C13, C16,
C17, C18, C19, C22, C28, C29,
C30, C49, C50, C51, C52, C53,
C54, C65, C67, C70, C89, C90,
C94, C96, C105, C110
6 3 C6, C7, C106 1 µF Ceramic Y5V 10V AVX
7 4 C10, C11, C14, C15 47 nF Ceramic X7R 10V AVX
8 5 C20, C21, C23, C24, C26, C27 22 pF Ceramic NPO 10V AVX
9 14 C25, C71, C72, C73, C74, C75,
C76, C77, C82, C83, C86, C98,
C102, C103
10 7 C43, C78, C79, C80, C81, C84, C85 10 pF Ceramic NPO 10V 5% AVX
11 1 C44 4 - 25 pF Varicap. serie TZBX4 MURATA
12 1 C45 10 nF CeramicX7R 10V 10% AVX
13 2 C46, C47 100 nF CeramicX7R 10V 10% AVX
14 3 C48, C100, C101 1 µF CeramicX7R 10V 10% AVX
15 2 C55, C59 22 pF CeramicX7R 25V AVX
16 2 C57, C99 10 µF Tantalum
18 1 C58 100 µF Tantalum
20 1 C60 3.3 nF Ceramic X7R/25V/10% SIEMENS
21 3 C61, C62, C64 1 µF CeramicX7R 10V 10% AVX
22 2 C104, C63 10 µF Tantalum 16V 10% TAJ AVX
23 9 D1, D2, D3, D4, D5, D6, D7, D8,
D11
100 nF Ceramic Y5 10V AVX
10 nF Ceramic X7R 16V AVX
AVX
(TPS ou OS-CON) 25V ESR < 0.5Ω
AVX
(TPS ou 593D) 10V ESR < 0.5Ω
Red LED Red LED H.R. 3mm T1 7mcd 60° HP
AT91EB42 Evaluation Board User Guide 7-1
Rev. 1708C–ATARM–12-May-05
Page 38
Appendix C – Bill of Materials
Figure 7-1. Bill of Materials for AT91EB42 (Continued)
Item Qty. Reference Part Designation Manufacturer
24 2 D10, D28 Red LED Red CMS LED HP
25 2 D30, D29 Orange LED SMT Orange LED HP
26 2 D32, D31 Green LED SMT Green LED HP
27 1 D12 1N914 Diode Fairchild
28 1 D14 SMT6T15CA Transil 12.8V/600W/VBRmin. 14.3V ST
29 1 D15 1N5817 Schottky 1A/0.45V ST
30 7 D16, D17, D18, D19, D24, D25, D26 10MQ100N Rectifier diode 0.62V/0.77A I.R.
31 1 F1 1000 mA/30V Fuse rarm 1000 mA/30V Polyswitch
32 1 J1 Jack diam. 2.1mm Jack socket diam. 2.1 mm LUMBERG
33 1 L1 10 µH Self 10 µH @ 1A and 500 kHz COILCRAFT
34 1 P3 Sub D 9b F Sub D 9b F, female socket, right
35 1 P4 Sub D 9b M Sub D 9b M, male socket, right angle,
36 1 P5 HE10 2x10 HE10 2 x 10, low-profile T&B
37 1 Q1 MJD45H11 Transistor PNP MOTOROLA
38 29 R1, R2, R3, R4, R5, R14, R15, R16,
R17, R25, R27, R31, R32, R34,
R40, R41, R42, R43, R44, R45,
R46, R48, R51, R52, R53, R65,
R66, R71, R78
39 15 R6, R7, R8, R9, R10, R11, R12,
R13, R23, R24, R29, R73, R74,
R75, R76
40 1 R18 1K50 1% Resistor @ 1%, 125 mW Vishay
41 1 R19 100R 1% Resistor @ 1%, 125 mW Vishay
42 1 R20 680R 1% Resistor @ 1%, 125 mW Vishay
43 1 R21 120R 1% Resistor @ 1%, 125 mW Vishay
44 1 R30 150R Resistor @ 1%, 125 mW Vishay
45 1 R58 10K Resistor @ 1%, 125 mW Vishay
46 1 R59, R60, R79 1k Resistor @ 1%, 125 mW Vishay
47 1 R61 10K CTN Therm. CTN 10k @ 25°C,
48 4 R62d, R62c, R62b, R62a (****) 10R Resistor 0.25W 5% RC01
49 1 R67 7.5K1% Resistor @ 1%, 125 mW Vishay
50 1 R68 66.5K1% Resistor @ 1%, 125 mW Vishay
51 1 R69 31.6K1% Resistor @ 1%, 125 mW Vishay
52 1 R70 100K1% Resistor @ 1%, 125 mW Vishay
53 1 R77 (****) 6R8 Resistor @ 1%, 125 mW Vishay
54 1 R80 90.9K1% Resistor @ 1%, 125 mW Vishay
55 1 R81 75K1% Resistor @ 1%, 125 mW Vishay
56 4 SW1, SW2, SW3, SW4 TP 33 Push-button with black cap APEM
100K Resistors @ 5% Vishay
100R Resistor @ 5% Vishay
angle, mechanical strength, locking
mechanical strength, locking
B = 3730°K
ETEC
ETEC
SIEMENS
7-2 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 39
Appendix C – Bill of Materials
Figure 7-1. Bill of Materials for AT91EB42 (Continued)
Item Qty. Reference Part Designation Manufacturer
57 1 SW5 TP 33 Push-button with red cap APEM
58 1 S1 B.P. SMT Push-button J.RENAUD
59 4 TP1, TP2, TP3, TP4 Test Point Corner SMT Test point
60 1 U1
61 2 U3, U2
62 2 U5, U4
63 1 U6 74LVC02AD QUAD 2-INPUT NOR Gate TI Philips
64 1 U8 74LV244D Buffer TI Philips
65 1 U9 74LV125D Tri-state buffer TI Philips
66 1 U10 MAX3223ECAP Driver RS232 + ESD “E” MAXIM
67 1 U11 AT91M42800A 32-bit Arm/Thumb Microcontroller Atmel
68 1 U12 74LVC74AD D flip-flop (LVC Serial) TI Philips
69 2 U13, U14 MAX6315US30D4-T Circuit LVD-reset Maxim
70 1 U15 LT1507CS8-3.3 Voltage Regulator DC/DC Linear Technology
71 1 U16 MAX 712/713 NiCd/NiMH Battery Fast-charge
72 1 U17 LTC 1503CS8-2 Voltage Regulator DC/DC Linear Technology
73 1 U18
75 1 U20 TLV1504 4 analog-to-digital converter with
77 1 U23 LM61BIM3 2.7V, SOT-23 Temperature Sensor NS
78 1 U30 74LCX74 D flip-flop (LCX serie) TI Philips
79 1 Y1 32,768kHz Crystal 32.768 kHz/50 ppm MICRO CRYSTAL
80 2 P1, P2 2 x 32 male HE10 Header 2.54 mm FCI
81 4 R62d, R62c, R62b, R62a 14R7 Resistor 0.25W 5% RC01
82 1 R77 680 Resistor 0.25W 5% RC01 Vishay
83 2 P1, P2 2 x 32-point, male HE13 Header 2.54 mm FCI
84 4 R62d, R62c, R62b, R62a 14R7 Resistor 0.25W 5% RC01
85 1 Socket to be bonded to BT1
86 1 Connector to supply battery
Notes: 1. The AT91EB42 board is equipped with SRAM U2/U3 or U4/U5. The difference is in the type of case used. The selection is
2. U18 is wired according to availability.
3. Cannot be seen in Figure 6-1.
(1)
(2)
(2)
(3)
made based on availability.
AT49BV162A-70TI 2-Mbyte x 16-bit Flash Atmel
IDT71V424S10Y Static memory:
IDT
128K x 8 - 15 ns/36-pin 400 mil SOJ
IDT71424S10PH Static memory:
IDT
128K x 8 - 15 ns/44-pin TSOP Type II
MAXIM
Controllers
AT45DB321-TC Serial DataFlash Atmel
TI
SPI protocol (D package)
(4)
4-point socket, male 2.54 mm pitch KK® vertical friction
Molex
lock header, series 6410/7395
(1)
4-point connector, female 2.54 mm pitch KK crimp terminal
Molex
housing, series 6471
AT91EB42 Evaluation Board User Guide 7-3
1708C–ATARM–12-May-05
Page 40
Appendix C – Bill of Materials
7-4 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 41
Section 8
Appendix D – Flash
Memory Mapping
Figure 8-1 shows the embedded software mapping after the remap. It describes the
location of the different programs in the AT49BV162A Flash memory and the division
into sectors.
Figure 8-1. EB42 Flash Memory Software Mapping
0x011FFFFF
Not Used
15 Sectors
(64K Bytes/Sector)
0x01100000
LED Swing Application
(Example)
1M Byte
User Mode
Not Used
Not Used
0x01011FFF
Angel Debug
Monitor
0x01006000
0x01005FFF
Free Sector for
Boot Upgrade
0x01004000
0x01000000
Flash Uploader
Functional Test Software
Boot Program
AT91EB42 Evaluation Board User Guide 8-1
14 Sectors
(64K Bytes/Sector)
1 Sector
(64K Bytes/Sector)
5 Sectors
(8K Bytes/Sector) +
1 Sector
(64K Bytes/Sector)
1 Sector
(8K Bytes/Sector)
2 Sectors
(8K Bytes/Sector)
1M Byte
Standard
Mode
Rev. 1708C–ATARM–12-May-05
Page 42
Appendix D – Flash Memory Mapping
8-2 AT91EB42 Evaluation Board User Guide
1708C–ATARM–12-May-05
Page 43
Document Details
Title AT91EB42 Evaluation Board User Guide
Literature Number 1708
Revision History
Version C Publication Date: 12-May-05
Revisions since last issue
All pages Removed all references to SRAM Downloader
Removed all references to two-wire interface
Changed all occurrences of AT49B1604(A) or AT49BV1614(A) or AT49BV16x4 to
AT49BV162A.
Section 1.3 Removed references to:
64K bytes of EEPROM with two-wire access
32K bytes of SPI EEPROM
Fig.1-1 Removed the 2 "SERIAL EEPROM" boxes
Section 2.7 Changed
- D4 for the EEPROM with two-wire access to D4 reserved
- D6 for the SPI EEPROM to D6 reserved
Section 3.2 Replaced the description of "When SW2 button is pressed" by Reserved
Section 3.4 Removed
Section 3.5 Replaced AT91F40816 and AT91FR4081 by AT91FR4042 and AT91FR40162/S
Section 4.3 Added note:
The AT24C512 64K byte EEPROM and the AT25256 32K byte EEPROM are not
mounted.
Appendix A Removed the table describing CB24
Figure 6-3 EBI Memories
Changed AT49BV16X4-90TC to AT49BV162A for U1 part.
Figure 6-9 Changed figure names into SPI and TWI Memories.
For U19 & U21 part: Add note NOT MOUNTED
Table 7-1 Removed items 74 & 76
Item 60 / "Part" Column --> changed to AT49BV162A-70TI
1708C–ATARM–12-May-05
1
Page 44
Figure 8-1 Updated with new memory sizes
2
1708C–ATARM–12-May-05
Page 45
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1708C–ATARM–12-May-05
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