Datasheet AT89LV55-12AC, AT89LV55-12PI, AT89LV55-12PC, AT89LV55-12JI, AT89LV55-12JC Datasheet (ATMEL)

203Features

•

Compatible with MCS-51™ Products

•

20K Bytes of Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

•

Fully Static Operation: 0 Hz to 12 MHz

•

Three-Level Program Memory Lock

•

256 x 8-bit Internal RAM

•

32 Programmable I/O Lines

•

Three 16-bit Timer/Counters

•

Eight Interrupt Sources

•

Low Power Idle and Power Down Modes

•

2.7V to 6.0V Operating Range

Description

The AT89LV55 is a low-voltage, low-power CMOS 8-bit microcomputer with 20K
bytes of Flash programmable and erasable read only memory. The device is manu­factured using At mel’ s high dens ity nonv olat ile m emory te chnol ogy an d is compat ible
with the industry sta nda rd 80 C51 in struction set and pi nou t. Th e o n- ch ip Flash allows
the program memory to be rep rogrammed. By combining a ve rsatile 8-bit CPU with
Flash on a monolithic chip, the Atmel AT89LV55 is a powerful microcomputer which
provides a highly flex ible and co st effe ctive solu tion to many embedd ed con trol app li­cations.

(continued)

Pin Configurations

TQFP

PLCC

8-Bit
Microcontroller
with 20K Bytes
Flash

AT89LV55

PDIP

0811B-B–12/97

4-193

Block Diagram

V

CC

GND

P0.0 - P0.7

PORT 0 DRIVERS

P2.0 - P2.7

PORT 2 DRIVERS

RAM ADDR.

REGISTER

B

REGISTER

RAM

ACC

TMP2 TMP1

ALU

PSW

PORT 0

LATCH

INTERRUPT, SERIAL PORT,

PORT 2

LATCH

AND TIMER BLOCKS

STACK

POINTER

FLASH

PROGRAM

ADDRESS

REGISTER

BUFFER

PC

INCREMENTER

PROGRAM

COUNTER

ALE/PROG

EA / V

4-194

PSEN

RST

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

DPTR

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

AT89LV55

AT89LV55

The AT89LV55 provides the following standard features:
20K bytes of Flash, 256-bytes of RAM, 32 I/O li nes, three
16-bit timer/counters, a six-vector two-level interrupt archi­tecture, a full duplex serial port, on-chip os cillator, and
clock circuitry. In addition, the AT89LV55 is designed with
static logic for operation down to zero frequency and sup­ports two softwar e selectable po wer saving modes . The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial p or t, and int er rupt s yst em to co nti nue
functioning. The Power Down Mode saves the RAM con­tents but freezes the oscillator, disabling all other chip func­tions until the next hardware reset. The low-voltage option
saves power and operates with a 2.7-volt power supply.

Pin Description

V

CC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 can also be configu red to be the multiplex ed low­order address/data bus during accesses to ex ternal pro­gram and data memory. In this mode, P0 has internal pul­lups.

Port 0 also rece ives th e code by tes dur ing Fla sh prog ram­ming and outputs the code bytes during program ver ifica­tion. External pu llups are requ ired during pr ogram v erific a­tion.

Port 1

Port 1 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins , they are p ulled hi gh by
the internal pullups and can be used as inputs. As inputs ,
Port 1 pins that are externally being pulled low will source
current (I

In addition, P1.0 and P1. 1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

) because of the internal pullups.

IL

clock-out

Port 2

Port 2 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 2 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

IL

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory th at u se 16 -b it a ddres s es ( MO VX @
DPTR). In this application, Port 2 uses strong internal pul­lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 3 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also serv es t he fun ctions of v arious spe cial f eatures
of the AT89LV55, as shown in the following table.

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD

(external interrupt 1)

(external data memory write strobe)

(external data memory read strobe)

Port 3 also receives the highest-order address bit and
some control signals fo r Flash pro grammin g and veri fica­tion.

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

P1.1 T2EX (Timer/Counter 2 capture/reload trigger and

direction control)

Port 1 also receives the low-order address bytes during
Flash programming and verification.

4-195

ALE/PROG

Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem­ory. This pin is also the program pulse input (PROG
Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim­ing or clocking purposes. No te, however, that one ALE
pulse is skipped durin g each access to extern al data me m­ory.

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur­ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

When the AT89LV55 is executing code from external pro­gram memory, PSEN
cycle, except that two PSEN
each access to external data memory.

/V

EA

PP

External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA
internally latched on reset.

should be strapped to VCC for internal program execu-

EA
tions.

This pin also receives the 12-volt programming enable volt­age (V

XTAL1

Input to the inverting os cillator ampl ifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

) during 12-volt Flash programming.

PP

is activated twice each machine

activations are skipped during

) during

will be

Timer 2 Registers:

registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCA P2L )
are the Capture/ Reloa d regist ers for Timer 2 i n 16-bit c ap­ture mode or 16-bit auto-reload mode.

Interrupt Registers:

are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.

Control and status bits are contained in

The individual interrupt enable bits

Data Memory

The AT89LV55 implements 256 bytes of on-chip RAM. The
upper 128 bytes oc cupy a parall el address sp ace to the
Special Function Registers. That means the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU acce sses the u pper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.

For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing inst ructi on, where R0 contains 0A 0H, a cc ess es
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail ­able as stack space.

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi­nate effect.

User software should not write 1s to these unlisted loca­tions, since they may be used in future products to invoke
new features. In th at case, th e reset or i nactive va lues of
the new bits will always be 0.

4-196

AT89LV55

AT89LV55

Table 1.

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

AT89LV55 SFR Map and Reset Values

B

00000000

ACC

00000000

PSW

00000000

98H

90H

88H

80H

T2CON

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

RCAP2L

00000000

TL0

00000000

DPL

00000000

RCAP2H

00000000

TL1

00000000

DPH

00000000

TL2

00000000

TH0

00000000

TH2

00000000

TH1

00000000

PCON

0XXX0000

0F7H

0E7H

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

4-197

Table 2.

T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable

T2CON—Timer/Counter 2 Control Register

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

Bit

Symbol Function

TF2 Timer 2 ove rflo w fla g set b y a Tim er 2 o v erfl ow an d m ust be clea red b y so ftwa re. TF2 will no t be set when eith er RCLK

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

RCLK Receive clo ck enab le. Whe n set, caus es the serial port to use Timer 2 o v erflow pulses fo r its receiv e cl ock in serial port

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2

CP/RL2

76543210

= 1 or TCLK = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must
be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative tr ansiti ons at T2EX if EXEN2 = 1. CP/RL2 =
0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.
When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

CP/RL2

Timer 0 and 1

Timer 0 and 1 in the AT89LV55 operate the same way as
Timer 0 and Timer 1 in the AT 89C51 and AT89C52. F or
further information, see the Microcontroller Data Book, sec­tion titled, “Timer Counters.”

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.

Timer 2 consists of two 8- bi t regi st er s, TH2 and TL2. I n the
Timer function, the TL2 r egister is incremented ever y
machine cycle. Since a machine cycle consists of 12 oscil­lator periods, the count rate is 1/12 of the oscillator fre­quency.

In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In thi s func tion, the extern al i nput is sa mpled
during S5P2 of every machin e cycle. When the samples

in the SFR T2 C ON (sh o w n i n Ta bl e 2).

show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator perio ds ) ar e re qui red to recognize a 1-to -0 transi­tion, the maximum count rate is 1/24 of the oscillator fre­quency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.

Table 3.

Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-Reload
0 1 1 16-bit Capture
1 X 1 Baud Rate

Generator

X X 0 (Off)

4-198

AT89LV55

AT89LV55

Capture Mode

In the capture mode, two option s are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Tim er 2 p erfor ms t he s ame op erati on, but a 1-

Figure 1.

Timer 2 in Capture Mode

to-0 transition at external input T2EX also causes the cur­rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, respec tively. In addition, the tran sition at T2EX
causes bit EXF2 in T2CON to be set. The EXF2 bit, li ke
TF2, can generate an interrupt. The capture mode is illus­trated in Figure 1.

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
is set to 0 so that tim er 2 will default to count up. Wh en
DCEN is set, Timer 2 can coun t up or down, depend ing on
the value of the T2EX pin.

Figure 2 shows Timer 2 aut omatically counting u p when
DCEN = 0. In this mod e, two options a re selecte d by bit
EXEN2 in T2CON. If EXEN2 = 0, Tim er 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The over­flow also causes the tim er r egi ste rs to be r e loa ded with the
16-bit value in RCAP2H and RCAP2L. The values in
RCAP2H and RCAP2L are preset by software. If EXEN2 =
1, a 16-bit reload can be triggered either by an overflow or
by a 1-to-0 transition at external input T2EX. This transition
also sets the EXF2 bit. Both th e TF2 and EXF2 bits c an
generate an interrupt if enabled.

Setting the DCEN bit ena ble s Ti mer 2 t o c ount up o r d own,
as shown in Figure 3. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in
RCAP2H and RCAP2L to be reloaded into the timer regis­ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stor ed in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.

4-199

Figure 2.

Timer 2 Auto Reload Mode (DCEN = 0)

Table 4.

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable

Bit76543210

Symbol Function

— Not implemented, reserved for future use.
T20E Timer 2 Output Enable bit.
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

T2MOD—Timer 2 Mode Control Register

——————T20EDCEN

4-200

AT89LV55

AT89LV55

Figure 3.

Timer 2 Auto Reload Mode (DCEN = 1)

Figure 4.

Timer 2 in Baud Rate Generator Mode

4-201

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the baud
rates for transmit and receive can be different if Timer 2 is
used for the rece iver or tr ansm itter a nd Tim er 1 is used f or
the other function. Setting RCLK and/or TCLK puts Timer 2
into its baud rate generator mode, as shown in Figure 4.

The baud rate gener ator mod e is s imilar to the au to-rel oad
mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.

The baud rates in Mod es 1 a nd 3 ar e det ermin ed by Tim er
2’s overflow rate according to the following equation.

Modes 1 and 3 Baud Rates

The Timer can be configured for either timer or counter
operation. In most applicat ions, it is configured for tim er
operation (CP/T2
Timer 2 when it is used as a baud rate generator. Normally,
as a timer, it increments every machine cycle (at 1/12 the
oscillator frequency ). As a ba ud rate generator , howev er, it
increments every state time (at 1/2 the oscillator fre­quency). The baud rate formula is given below.

= 0). The timer ope ration is different for

Timer 2 Overflow Rate

----------------------------------------------------------- -=

16

Modes 1 and 3

---------------------------------------

Baud Rate

where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 4. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not gener­ate an interrupt. Note too, that if EXEN2 is set, a l-to-0 tran­sition in T2EX will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is
in use as a baud rate generator, T2EX can be used as an
extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in
the baud rate generator mode, TH2 or TL2 should not be
read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or
write may not be accurate. The RCAP2 registers may be
read but should not be written to, because a write might
overlap a reload and cause write and/or reload errors. The
timer should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.

Oscillator Frequency

----------------------------------------------------------------------------------------------=

32 65536 RCAP2H,RCAP2L

()–[]×

Figure 5.

Timer 2 in Clock-Out Mode

4-202

AT89LV55

AT89LV55

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 5. This pin, besides being a regu­lar I/O pin, has two alternat e functions. It can be pro­grammed to input the e xte rn al clo ck for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 3
MHz at a 12

MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit

(T2CON.1) must be cleared and bit T2OE (T2MOD.1)

C/T2
must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator fre­quency and the r eload valu e of Time r 2 capture registers
(RCAP2H, TCAP2L), as shown in the following equation:

Clock-Out Frequency

Oscillator Frequency

------------------------------------------------------------------------------------------=

4 65536 RCAP2H RCAP2L

(,)–[]×

In the clock-out mode, Timer 2 roll-overs will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock g enerator simul ta­neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.

UART

The UART in the AT89LV55 operates the same way as the
UART in the AT89C51 and AT89C52. For further informa­tion, see the Microcontroller Data Book, section titled,
“Serial Interface.”

Interrupts

The AT89LV55 has a total of six interrupt vectors: two
external interrupts (INT0
(Timers 0, 1, and 2), and th e serial port interrupt. These
interrupts are all shown in Figure 6.

Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Fu nction
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.

Note that Tab le 5 shows that bit po sition IE .6 is uni mple­mented. In the AT89C51 and AT89LV51, bit position IE.5 is
also unimplemented. User software should not write 1s to
these bit positions, since they may be used in future AT89
products.

Timer 2 interrupt is gen er ated by the log ic al OR o f bi ts TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware whe n the servi ce routine i s vectored
to. In fact, the service rout ine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.

The Timer 0 and Timer 1 fl ags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers ov erflow. The va lues

and INT1), three timer interrupts

are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows. For further infor­mation, see the Microcontroller Data Book, section titled
“Interrupts.”

Table 5.

(MSB) (LSB)

Symbol Position Function

User software should never write 1s to unimplemented bits,
because they may be used in future AT89 products.

Figure 6.

Interrupt Enable (IE) Register

EA — ET2 ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.

EA IE.7 Disables all interrupts. If EA = 0, no

interrupt is acknowledged. If EA = 1,
each interrupt source is individually
enabled or disabled by setting or
clearing its enable bit.

— IE.6 Reserved.

ET2 IE.5 Timer 2 interrupt enable bit.

ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.

Interrupt Sources

4-203

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, resp ectively,
of an inverting amplifier that can be confi gured for use as
an on-chip oscillator, as shown in Figure 7. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 8.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi­mum voltage high and low time specifications must be
observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on­chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe­cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any en abled
interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware
reset, the device norm ally resumes program execution
from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi­nated by a reset, the instruction following the one that
invokes idle m ode s hou ld not write to a por t p in or to exter­nal memory.

Figure 7.

Note: C1, C2 = 30 pF ± 10 pF for Cry s tals

Figure 8.

Oscillator Connections

= 40 pF ± 10 pF for Ceramic Resonators

External Clock Drive Configuration

Status of External Pins During Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Po w er Do wn Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data

4-204

AT89LV55

AT89LV55

Power Down Mode

In the power down mode, the oscillator is stopped, and the
instruction t hat invo kes po wer down is th e last instru ction
executed. The on-chip RAM and Special Function Regis­ters retain their values until the power d own m ode is ter mi­nated. The only exit fr om power do wn is a hard ware reset .
Reset redefines the SFRs but does not change the on-c hip
RAM. The reset should not be activated before V
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta­bilize.

CC

Program Memory Lock Bits

The AT89LV55 has three lock bits that can be left unpro­grammed (U) or can be programmed (P) to obtain the addi­tional features listed in the following table:

is

Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features.
2 P U U MOVC instructions executed from external program memory are disabled from fetching code

bytes from internal memory, EA

the Flash memory is disabled.
3 P P U Same as mode 2, but verify is also disabled.
4 P P P Same as mode 3, but external execution is also disabled.

is sampled and latched on reset, and further programming of

When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during rese t. If the device is pow­ered up without a reset, the latch initi alizes to a random
value and holds that value until reset is activated. The
latched value of EA
at that pin in order for the device to function properly.

The AT89LV55 code memory array is programmed byte­by-byte.

To program any non-blank by te in the on-chip

must agree with the current logic le vel

Flash Memory, the entire memory mus t be erased using
the Chip Erase Mode.

Programming the Flash

The AT89LV55 is normally shipped with the on-chip Flash
memory array in th e erased st ate (that i s, conten ts = FFH)
and ready to be programmed.

Programming Algorithm:

AT89LV55, the address, data and control signals should be
set up according to the Flash programming mode table and
Figure 9 and Figure 10. To program the AT89LV55, take
the following steps:

1. Input the desired memory location on the address
lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA

/VPP to 12V

Before programming the

5. Pulse ALE/PROG once to pro gram a byte in the Flash
array or the lock bits. The byte-write cycle is self-timed
and typically takes no more tha n 1.5 ms. Repeat ste ps
1 through 5, changing the address and data for the
entire array or until the end of the object file is reached.

Polling:

Data

cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com­plement of the written data on PO.7. O nce the write cycle
has been completed, true data is valid o n all outputs, and
the next cycle may begin . Data
after a write cycle has been initiated.

Ready/Busy

be monitored by the RDY/BUSY
pulled low after ALE goe s h ig h du ring pr ogram mi ng to i ndi ­cate BUSY
done to indicate READY.

Program Verify:

programmed, the programmed code data can be read back
via the address and data line s for verific ation . The lock bits
cannot be verified dire ctly. Verificati on of the lock bits is
achieved by observing that their features are enabled.

The AT89LV55 features Data

Polling may begi n any ti me

:

The progress of byte programming can also

output signal. P3.4 is

. P3.4 is pulled high again when programming is

If lock bits LB1 and LB2 have not been

Polling to indi-

4-205

Figure 9.

Programming the Flash Memory

Figure 10.

Verifying the Flash Memory

+5V

AT89LV55

ADDR.

0000H/4FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-12 MHz

A0-A7

A8 - A13

A14*

P1.0 - P1.7
P2.0 - P2.5
P3.0

P2.6
P2.7

P3.6
P3.7

XTAL2 EA

XTAL1
GND

V

CC

P0

ALE

RST

PSEN

PGM
DATA

PROG

V/V

I H PP

V

I H

*Programming ad dr es s li ne A 14 ( P3 .0) i s not the same
as the external memory address line A14 (P2.6)

ADDR.

0000H/4FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-12 MHz

A0-A7

A8 - A13
A14*

AT89LV55

V

P1.0 - P1.7
P2.0 - P2.5

P3.0
P2.6
P2.7
P3.6
P3.7

XTAL2 EA

XTAL1
GND

CC

P0

ALE

RST

PSEN

+5V

PGM DATA
(USE 10K
PULLUPS)

V

I H

V

I H

Chip Erase:

The entire Flash array is erased electrically
by using the proper combinati on of control s ignals and by
holding ALE/PROG

low for 10 ms. The code array is written
with all 1s. The chip erase operation must be executed
before the code memory can be reprogrammed.

Reading the Signature Bytes:

The signature bytes are
read by the same procedure as a normal verification of
locations 030H, an d 03 1H, e xc ep t tha t P 3.6 and P3 .7 m us t
be pulled to a logic low. The values returned are as follows:

(030H) = 1EH indicates manufactured by Atmel
(031H) = 65H indicates 89LV55
(032H) = FFH indicates 12V programming

Programming Interface

Every code byte in the Flash array can be written, and the
entire array can be erased, by using the appropriate combi­nation of control signals. The write operation cycle is self­timed and once initiated, will automatically time itself to
completion.

All major programmi ng ve ndors o ffer wo rldwide suppor t for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.

4-206

AT89LV55

Flash Programming Modes

AT89LV55

Mode RST PSEN

Write Code Data H L 12V L H H H

Read Code Data H L H H L L H H
Write Lock Bit-1 H L 12V H H H H

Bit-2 H L 12V H H L L

Bit-3H L 12V HLHL

Chip Erase H L 12V H L L L

Read Signature Byte H L H H L L L L

Note: 1. Chip Erase re quires a 10-ms PROG pulse.

ALE/PROG EA/V

(1)

PP

P2.6 P2.7 P3.6 P3.7

4-207

Flash Programming and Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0V ± 10%

Symbol Parameter Min Max Units

V

PP

I

PP

1/t

CLCL

t

AVGL

t

GHAX

t

DVGL

t

GHDX

t

EHSH

t

SHGL

t

GHSL

t

GLGH

t

AVQV

t

ELQV

t

EHQZ

t

GHBL

t

WC

Programming Enable Voltage 11.5 12.5 V
Programming Enable Current 1.0 mA
Oscillator Frequency 3 12 MHz
Address Setup to PROG Low 48t
Address Hold After PROG 48t
Data Setup to PROG Low 48t
Data Hold After PROG 48t
P2.7 (ENABLE) High to V

PP

48t

CLCL
CLCL
CLCL
CLCL
CLCL

VPP Setup to PROG Low 10
VPP Hold After PROG 10
PROG Width 1 110
Address to Data Valid 48t
ENABLE Low to Data Valid 48t
Data Float After ENABLE 0 48t

CLCL
CLCL
CLCL

PROG High to BUSY Low 1.0
Byte Write Cycle Time 2.0 ms

s

µ

s

µ

s

µ

s

µ

Flash Programming and Verification Waveforms (VPP = 12V)

4-208

AT89LV55

AT89LV55

Absolute Maximum Ratings*

Operating Temperature................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage............................................. 6.6V

DC Output Current......................................................15.0 mA

DC Characteristics

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 2.7V to 6.0V, unless otherwise noted.

Symbol Parameter Condition Min Max Units

V

IL

V

IL1

V

IH

V

IH1

V

OL

V

OL1

V

OH

V

OH1

I

IL

I

TL

I

LI

RRST Reset Pulldown Resistor 50 300 k
C

IO

I

CC

Input Low Voltage (Except EA)-0.50.2 V
Input Low Voltage (EA)-0.50.2 V
Input High V oltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V
Input High Voltage (XTAL1, RST) 0.7 V
Output Low Voltage

(Ports 1, 2, 3)
Output Low Voltage

(Port 0, ALE, PSEN)

Output High Voltage
(Ports 1, 2, 3, ALE, PSEN

Output High Voltage
(Port 0 in External Bus Mode)

Logical 0 Input Current
(Ports 1, 2, 3)

Logical 1 to 0 Transition Current
(Ports 1, 2, 3)

Input Leakage Current
(Port 0, EA

Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF

Power Supply Current

Power Down Mode

)

(1)

(1)

)

(1)

I

= 1.6 mA 0.45 V

OL

I

= 3.2 mA 0.45 V

OL

I

= -60 µA, VCC = 5V ± 10% 2.4 V

OH

I

= -25 µA 0.75 V

OH

I

= -10 µA0.9 VCCV

OH

I

= -800 µA, VCC = 5V ± 10% 2.4 V

OH

I

= -300 µA 0.75 V

OH

I

= -80 µA0.9 VCCV

OH

= 0.45V -50

V

IN

= 2V -650

V

IN

0.45 < V

Active Mode, 12 MHz 25 mA
Idle Mode, 12 MHz 6.5 mA
VCC = 6V 100
V

CC

< V

IN

CC

= 3V 40

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the de vi ce at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

- 0.1 V

CC

- 0.3 V

CC

CC

CC

CC

VCC + 0.5 V

±

10

V

V

µ

A

µ

A

µ

A

Ω

µ

A

µ

A

Notes: 1. Under steady state (non-transient) conditions, IOL

must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum I

per 8-bit port:

OL

Port 0: 26 mA, Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA

If I

exceeds the tes t conditio n, VOL may exceed the

OL

related specification. Pins are not guaranteed to sink
current greater than the listed test conditions.

2. Minimum V

for Power Down is 2V.

CC

4-209

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.

External Program and Data Memory Characteristics

Symbol Parameter 12 MHz Oscillator Variable Oscillator Units

Min Max Min Max

1/t

CLCL

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

PLAZ

t

RLRH

t

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

t

WHLH

Oscillator Frequency 0 12 MHz
ALE Pulse Width 127 2t
Address Valid to ALE Low 43 t
Address Hold After ALE Low 48 t
ALE Low to Valid Instruction In 233 4t
ALE Low to PSEN Low 43 t
PSEN Pulse Width 205 3t
PSEN Low to Valid Instruction In 145 3t

- 40 ns

CLCL

- 40 ns

CLCL

- 35 ns

CLCL

- 100 ns

CLCL

- 40 ns

CLCL

- 45 ns

CLCL

- 105 ns

CLCL

Input Instruction Hold After PSEN 00ns
Input Instruction Float After PSEN 59 t
PSEN to Address Valid 75 t

- 8 ns

CLCL

Address to Valid Instruction In 312 5t

- 25 ns

CLCL

- 105 ns

CLCL

PSEN Low to Address Float 10 10 ns
RD Pulse Width 400 6t
WR Pulse Width 400 6t
RD Low to Valid Data In 252 5t

- 100 ns

CLCL

- 100 ns

CLCL

- 165 ns

CLCL

Data Hold After RD 00ns
Data Float After RD 97 2t
ALE Low to Valid Data In 517 8t
Address to Valid Data In 585 9t
ALE Low to RD or WR Low 200 300 3t
Address to RD or WR Low 203 4t
Data Valid to WR Transition 23 t
Data Valid to WR High 433 7t
Data Hold After WR 33 t

- 50 3t

CLCL

- 130 ns

CLCL

- 60 ns

CLCL

- 150 ns

CLCL

- 50 ns

CLCL

- 70 ns

CLCL

- 150 ns

CLCL

- 165 ns

CLCL

+ 50 ns

CLCL

RD Low to Address Float 0 0 ns
RD or WR High to ALE High 43 123 t

CLCL

- 40 t

+ 40 ns

CLCL

4-210

AT89LV55

External Program Memory Read Cycle

AT89LV55

External Data Memory Read Cycle

4-211

External Data Memory Write Cycle

External Clock Drive Waveforms

External Clock Drive

Symbol Parameter Min Max Units

1/t

CLCL

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

4-212

Oscillator Frequency 0 12 MHz
Clock Period 83.3 ns
High Time 20 ns
Low Time 20 ns
Rise Time 20 ns
Fall Time 20 ns

AT89LV55

AT89LV55

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF.

Symbol Parameter 12 MHz Osc Variable Oscillator Units

Min Max Min Max

t

XLXL

t

QVXH

Serial Port Clock Cycle Time 1.0 12t
Output Data Setup to Cl ock Ri sing

Edge

700 10t

CLCL

CLCL

- 133 ns

ns

t

XHQX

t

XHDX

t

XHDV

Output Data Hold After Clock
Rising Edge

Input Data Hold After Clock Rising
Edge

Clock Rising Edge to Input Data
Valid

50 2t

00ns

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms

(1)

- 117 ns

CLCL

700 10t

Float Waveforms

(1)

- 133 ns

CLCL

Note: 1. AC Inputs during testing are driven at 2.4V for a

logic “1” and 0.45V for a logic “0”. Timing measure­ments are made at 2.0 V f or a logic “1” and 0.8V fo r a
logic “0”.

Note: 1. For timing purposes, a port pin is no longer floating

when a 100 mV change fro m lo ad voltage occu rs. A
port pin begins to float w h en a 100 mV change from
the loaded V

OH/VOL

level occurs.

4-213

Notes: 1. XTAL1 tied to GND for ICC (power down)

2. Lock bits programmed

4-214

AT89LV55

Ordering Information

AT89LV55

Speed

(MHz)

12 2.7V - 6.0V AT89LV55-12AC

Power

Supply Ordering Code Package Operation Range

AT89LV55-12JC
AT89LV55-12PC

AT89LV55-12AI
AT89LV55-12JI
AT89LV55-12PI

44A
44J
40P6

44A
44J
40P6

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

4-215