Page 1
1-Megabyte
Flash Memory
PCMCIA Card
AT5FC001
Features
Single Power Supply
•
Read and Write Volta ge, 5 V ± 5%
High Performance
•
200 ns Maximum Access Time
6 ms Typical Sector Write
CMOS Low Power Consumption
•
20 mA Typical Active Current (Byte Mode)
400 µA Typic al Standby Current
Fully MS-DOS Compatible Flash Driver and Formatter
•
Virtual-Disk Flash Driver with 256 By tes/Sector
Random Read/Write to any Sector
No Erase Operation Required Prior to any Write
Zero Data Retention Power
•
Batteries not Required for Data Storage
PCMCIA/JEIDA 68-Pin Standard
•
Selectable Byte- or Word-Wide Configuration
High Re-programmable Endurance
•
Built-in Redundancy for Sector Replacement
Minimum 100,000 Write Cycles
Five Levels of Write Protection
•
Prevent Accidental Data Loss
Block Diagram
Pin Configuration
Pin Name Function
A0-A19 Addresses
D0-D15 Data
CE1,CE2,
WE, OE, REG
CD, WP
BVD1, BVD2
Control Signals
Card Status
GND
CE1
A10
A11
A13
A14
WE
NC
VCC
NC
A16
A15
A12
WP
GND
1
2
D3
3
D4
4
D5
5
D6
6
D7
7
8
9
OE
10
11
A9
12
A8
13
14
15
16
17
18
19
20
21
22
A7
23
A6
24
A5
25
A4
26
A3
27
A2
28
A1
29
A0
30
D0
31
D1
32
D2
33
34
GND
35
36
CD1
37
D11
38
D12
39
D13
40
D14
41
D15
42
CE2
43
NC
44
RFU
45
RFU
A17
46
A18
47
A19
48
NC
49
NC
50
VCC
51
NC
52
NC
53
NC
54
NC
55
56
NC
57
NC
58
NC
59
NC
60
NC
61
REG
62
BVD2
63
BVD1
64
D8
65
D9
66
D10
67
CD2
68
GND
Page 2
Description
Atmel’s Flash Memory Card provides the highest system level
performance for data and file storage solutions to the portable
PC market segme nt. Data files and applic ations program s can be
stored on the AT5FC001. This allows OEM manufacturers of
portable system to eliminate the weight, powe r consumption and
reliability issues associated with electro-mechanical disk-based
systems. The AT5F C001 requires a single voltage power sup ply
for total system operation. No batteries are needed for data retention due to its Flash-based technology. Since no high volta ge
(12-volt) is required to perform any write operation, the
AT5FC001 is suitable for the emerging "mobile" personal systems.
The AT5FC001 is co mp atible with the 68- pin PC M CIA/ JEI DA
international standard. Atmel’s Flash Memory Cards can be
read in either a byte-wide or word-wide mode which allows for
flexible integration into various system platforms. It can be read
like any typical PCMCIA SRAM or ROM card.
Block Diagram
The Card Information Structure (CIS) can be written by the
OEM or by Atmel at the attribute memory address space using a
format utility. The CIS appears at the beginning of the card’s
attribute memory space and defines the low-level organization
of data on the PC card. The AT5FC001 contains a separate
2 Kbyte EEPROM memory for the card’s attribute memory
space.
The third party software solutions such as AWARD Software’s
CardWare system and the SCM’s Flash File System (FFS),
enables Atmel’s Flash Memory Card to emulate the function of
essentially all the major brand personal computers that are
DOS/Windows compatible.
For some unique portable computers, such as the
HP200/100/95LX series, the so ftw ar e Dr iver an d Fo rmatter are
also available. The Atmel Driver and Formatter utilizes a selfcontained spare sector replacement algorithm, enabled by Atmel’s small 256-byte sectors, to achieve long term card
reliability and endurance.
2 AT5FC001
Page 3
Absolute Maximum Ratings*
Storage Temperature........................-30°C to +70°C
Ambient Temperature with
Power Applied................................... -10°C to +70°C
Voltage with
Respect to Ground, All pins
(1)
V
............................................... -2.0 V to +7.0 V
CC
Output Short Cir c uit Current
(1)
.......... -2.0 V to +7.0 V
(2)
....................-200 mA
AT5FC001
*NOTICE: Stresses beyond those listed under "Absolute Maximum
Ratings" may cause perm an en t dam ag e to the card . T his is a stress
rating only and functional operation of the card at these or any
other conditions beyond those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transients, inputs may overshoot V
up to 20 ns. Maximum DC voltage on output and I/O pins is
V
+0.5 V. During voltage transitions, outputs may overshoot to
CC
V
+2.0 V for periods up to 20 ns.
CC
2. No more than one output shorted at a time. Durati on of the short circuit should not be greater than one second. Conditions equal
V
= 0.5 V or 5.0 V, VCC = Max.
OUT
to -2.0 V for periods of
SS
D.C. and A.C. Operating Range
AT5FC001-20
o
Operating Temperature (Case) Com. 0
Power Supply 5 V ± 5%
V
CC
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Symbol Parameter Conditions Typ Max Units
C
IN1
C
OUT
C
IN2
C
I/O
Note: 1. This parameter is characterized and is not 100% tested.
Address Capacitance VIN = 0 V 20 pF
Output Capacitance V
= 0 V 20 pF
OUT
Control Capacitance VIN = 0 (CE) 45 pF
I/O Capacitance V
= 0 V 20 pF
I/O
C - 70oC
3
Page 4
PC Card Pin Assignments
I = Input, O = Output, I/O = Bi-directional, NC = No Connect
Pin Signal I/O Function
1 GND Ground
2 D3 I/O Data Bit 3
3 D4 I/O Data Bit 4
4 D5 I/O Data Bit 5
5 D6 I/O Data Bit 6
6 D7 I/O Data Bit 7
7
CE
1
I Card Enable 1
8 A10 I Address Bit 10
9
OE I Output Enable
10 A11 I Address Bit 11
11 A9 I Address Bit 9
12 A8 I Address Bit 8
13 A13 I Address Bit 13
14 A14 I Address Bit 14
15
WE I Write Enable
16 NC No Connect
17 V
CC
Power Supply
18 NC No Connect
19 A16 I Address Bit 16
20 A15 I Address Bit 15
21 A12 I Address Bit 12
22 A7 I Address Bit 7
23 A6 I Address Bit 6
24 A5 I Address Bit 5
25 A4 I Address Bit 4
26 A3 I Address Bit 3
27 A2 I Address Bit 2
28 A1 I Address Bit 1
29 A0 I Address Bit 0
30 D0 I/O Data Bit 0
31 D1 I/O Data Bit 1
32 D2 I/O Data Bit 2
33 WP O Write Protect
34 GND Ground
(1)
(1)
Pin Signal I/O Function
35 GND Ground
36
CD
1
O Card Detect 1
37 D11 I/O Data Bit 11
38 D12 I/O Data Bit 12
39 D13 I/O Data Bit 13
40 D14 I/O Data Bit 14
41 D15 I/O Data Bit 15
42
CE
2
I Card Enable 2
43 NC No Connect
44 RFU Reserved
45 RFU Reserved
46 A17 I Address Bit 17
47 A18 I Address Bit 18
48 A19 I Address Bit 19
49 NC No Connect
50 NC No Connect
51 V
CC
Power Supply
52 NC No Connect
53 NC No Connect
54 NC No Connect
55 NC No Connect
56 NC No Connect
57 NC No Connect
58 NC No Connect
59 NC No Connect
60 NC No Connect
61
62
63 BVD
REG I Register Select
BVD
O Ba ttery Voltage Detect 2
2
O Ba ttery Voltage Detect 1
1
64 D8 I/O Data Bit 8
65 D9 I/O Data Bit 9
66 D10 I/O Data Bit 10
67
CD
2
O Card Detect 2
68 GND Ground
(1)
(1)
(2)
(2)
(1)
Notes: 1. Signal must not be connected between cards.
BVD = Internally pulled up.
2.
4 AT5FC001
Page 5
AT5FC001
Pin Description
Symbol Name Type Function
A0-A19 Address Inputs Input Address Inputs are internally latched during write cycles.
Data Input/Outputs are internally latched on write cycles.
D0-D15 Data Input/Output
CE1, CE
2
Card Enable Input
Input/Output
Data outputs are latched during read cycles. Data pins
are active high. When the memory card is de-selected or
the outputs are disabled the outputs float to tri-state.
Card Enable is active low. The memory card is
de-selected and power consumption is reduced to
standby levels when
memory card circuitry that controls the high and low byte
control logic of the card, input buffers, segment decoders,
and associated m emory devices.
CE is high. CE activates the inte rnal
OE Output Enable Input
WE Write Enable Input
V
CC
GND Ground Ground
CD1, CD
WP Write Protect Output
NC No Connect Corresponding pin is not connected internally.
BVD1, BVD2Battery Voltage Detect Output Internally pulled up. (There is no battery in the card.)
REG Register Select Input
2
PC Card Power
Supply
Card Detect Output
Output Enable is active low and e nables the data buffers
through the card outputs during rea d cycles.
Write Enable is active low and controls the write function
to the memory array . The target address is la tched on the
falling edge of the
latched on the rising edge of the pulse.
PC Card Power Supply for device operation
(5.0 V ± 5%)
When Card Detect 1 a nd 2 = Ground the system de tects
the card.
Write Protect is active high and indicates that all card
write operations are disabled by the write protect switch.
Provide access to Card Information Structure in the
Attribute Memory Device
WE pulse and the appropriate data is
5
Page 6
Memory Card Operations
The AT5FC001 Flash Memory Ca rd is orga nize d as an arr ay of
eight individual AT29C010A devices. They are logically defined as contiguous sectors of 256 bytes. Eac h sector can be read
and written randomly as designated by the host. There is NO
need to erase any sector prior to any write operation. Al so, there
is NO high voltage (12 V) required to perform any write operations.
The common memory space data contents are altered in a similar manner as writing to individual Flash memory devices. Oncard address and data buffers activate the appropriate Flash device in the memory array. Ea ch device inte rnally latches addr ess
and data during write cycles. Refer to the Memory Operations
Table.
Byte-Wide Op erations
The AT5FC001 provides the flexibility to operate on data in
byte-wide or word-wide op era tions. B yte- wide da ta is av ailab le
on D0-D7 for read and write operations (
high). Even and odd bytes are stored in a pair of memory chip
segments (i.e., S0 and S1) and are accessed when A0 is low and
high respectively.
Word-Wide Op er ations
The 16-bit words are accessed when both CE1 and CE2 are
forced low, A0 = don’t care. D0-D15 are used for word-wide
operations
Read Enable/Output Dis ab le
Data outputs from the card are disabled when OE is at a logichigh level. Under this condition, outputs are in the high-impedance state. The A18 and A19 select the paired memory chip segments, while A0 decides the upper or low er bank. The
pins determine either byte or word mode operation. The Output
Enable (
chip segments. The on-card I/O transceiver is set in the output
mode. The AT5FC001 sends data to the host. Refer to A.C.
Read Waveforms drawing.
OE) is forced low to activate all outputs of the memory
Standby Operations
When both CE1 and CE2 are at logic-high level, the A T5 FC001
is in Standby mode; i.e., all memory chip segments as well as the
decoder/transceiver are completely de-selected at minimum
power consumption. Even in the byte-mode read operation, only
one memory chip segment (even or odd) is active at any time.
The other seven memory chip segments remain in standby. In
the word-mode there are two memory chip segments in active
and six in standby.
Write Operations
The AT5FC010 is written on a sector basis. Each sector of 256
bytes can be selected randomly and written indepe ndently without any prior erase cycle. A8 to A17 specify the sector address,
while A18 and A19 spec ify the F la sh chip segment pair. W ithin
each sector, the indivi dua l byt e address is latched on the falling
CE1 = low, CE2 =
CE1/CE
edge of
the first rising edge of
grammed must have its high-to-low transition on
within 150 µs of the low-to- high transition of
preceding byte pair. If a high-to-low transition is not detected
within 150 µs of the last low-to-high transition, the data load
period will end and the internal programming period will start.
All the bytes of a sector are simultaneously programmed during
the internal programming period. A maximum write time of 10
ms per sector is self-controlled by the Flash devices. Refer to
A.C. Write Waveforms drawings.
CE or WE, whicheve r occurs last. The data is latched by
CE or WE. Each byte pair to be pro-
WE (or CE) of the
Write Protecti on
The AT5FC001 has five types of write protection. The
PCMCIA/JEIDA socket itself provides the first type of write
protection. Power supply and control pins have specific pin
lengths in order to protect the card with proper power supply
sequencing in the case of hot insertion and removal.
A mechanical write protection switch pr ovides a se cond type of
write protection. When this switch is activate d,
forced high. The Flash memory arrays are therefore write-disabled.
The third type of write protection is achieved with the built-in
low VCC sensing circuit within each Flash device. If the external VCC is below 3.8 V (typical), the write function is inh ibited.
The fourth type of write p rotection is a noise filte r ci rcuit within
each Flash device. Any pulse of less than 15 ns (typical) on the
WE, CE1 or CE2 inputs will not initiate a program cycle.
The last type of write protection is based on the Software Data
Protection (SDP) scheme of the AT29C010A devices. Each of
2
the eight devices needs to enable and disable the SDP individually. Refer to the SDP Algorithm Table for descriptions of enable and disable SDP operations.
WE is internally
Card Detection
Each CD (output) pin should be read by the host system to determine if the memory card is properly seated in the socket.
and CD2 are internally tied to the ground. If both bits are not
detected, the system should indicate that the card must be
re-inserted.
CIS Data
The Card Information Structure (CIS) describes the capabilities
and specifications of a card. The CIS of the AT5FC001 can be
written either by the OEM or by Atmel at the attribute memory
space beginning at address 00000H by using a format utility.
The AT5FC001 conta ins a s epar ate 2 Kbyte EEPROM m e mo ry
for the card’s attribute memory space. The attribute is active
when the
tribute memory access. D8-D15 should be ignored. Odd order
bytes present invalid data. Refer to the Attribute Memory
Operations table.
REG pin is driven low. D0-D7 are active during at-
WE (or CE)
CD
1
6 AT5FC001
Page 7
Common Memory Operations
X = Don’t Care, where Don’t Care is either VIL or VIH levels.
AT5FC001
Pins REG CE
CE
2
OE WE A0 D8-D15 D0-D7
1
Read-Only
Read (x8)
Read (x8)
Read (x8)
Read (x16)
Output Disable V
Standby X V
(1)
(2)
(3)
(4)
V
IH
V
IH
V
IH
V
IH
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
XXVIHV
IH
V
IH
X X X High Z High Z
Write-Only
Write (x8)
Write (x8)
Write (x8)
Write (x16)
(1)
(2)
(3)
(4)
Output Disable V
Notes:
1. Byte access - Even. In this x8 mode, D0-D7 contain the "even"
byte (low byte) of the x16 word. D8-D15 are inactive.
2. Byte access - Odd. In this x8 mode, D0-D7 contain the "odd" byte
(high byte) of the x16 word. This is accomplished internal to the
card by transposin g D 8 -D 15 to D0 -D 7. D 8-D 15 are inactive.
V
IH
V
IH
V
IH
V
IH
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
IH
V
IH
XXVIHV
V
IH
V
IH
V
IH
V
IH
IH
V
IL
V
IL
V
IL
V
IL
IL
V
V
High Z Data Out-Even
IL
High Z Data Out-Odd
IH
X Data Out-Odd High Z
X Data Out-Odd Data Out-Even
X High Z High Z
V
V
High Z Data In-Even
IL
High Z Data In-Odd
IH
X Data In-Odd High Z
X Data In-Odd Data In-Even
X High Z High Z
3. Odd byte only access. In this x8 mode, D8-D15 contain the "odd"
byte (high byte) of the x16 word. D0-D7 are inactive. A1 = X.
4. Word access. In this mode D0-D7 contain the "eve n" byte while
D8-D15 contain the "odd" byte. A0 = X
Memory Card Program Routine
Byte Mode
BEGIN
SELECT
SECTOR
LOAD ADDRESS/DATA
OF 256 BYTES
WAIT FOR A
MAXIMUM OF 10 ms
SECTOR
PROGRAM COMPLETE
INTERLEAVINGLOW
128 BYTES AND
HIGH 128 BYTES
Memory Card Program Routine
Word Mode
BEGIN
SELECT
SECTOR
LOAD ADDRESS/DATA
OF 128 WORDS
WAIT FOR A
MAXIMUM OF 10 ms
SECTOR
PROGRAM COMPLETE
LOW AND HIGH BYTES
SIMULTANEOUSL Y
7
Page 8
Attribute Memory Operations
X = Don’t Care, where Don’t Care is either VIL or VIH levels.
Pins REG CE
CE
2
OE WE A0 D8-D15 D0-D7
1
Read-Only
Read (x8)
(1)
Read (x8) V
Read (x8) V
Read (x16) V
Output Disable V
Standby X V
V
IL
IL
IL
IL
IL
VIH V
VIH V
VIL V
VIL V
IL
IL
IH
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
V
High Z Data Out-Even
IL
High Z Not Valid
IH
X Not Valid High Z
X Not Valid Data Out-Even
XXVIHVIHX High Z High Z
IH
V
IH
X X X High Z High Z
Write-Only
Write (x8)
(1)
Write (x8) V
Write (x8) V
Write (x16) V
Output Disable V
Note: 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive.
V
IL
IL
IL
IL
IL
V
IH
VIH V
VIL V
VIL V
V
IL
IL
IH
IL
V
IH
V
IH
V
IH
V
IH
XXVIHV
V
IL
V
IL
V
IL
V
IL
IL
V
V
High Z Data In-Even
IL
High Z Not Valid
IH
X Not Valid High Z
X Not Valid Data In-Even
X High Z High Z
8 AT5FC001
Page 9
AT5FC001
D.C. Characteristics, Byte-Wide Operation
Symbol Parameter Condition Min Typ Max Units
= VCC Max,
V
I
LI
I
LO
I
SB
I
CC1
Input LeakageCurrent
Output Leakage Current
VCC Standby Current
(1)
V
Active Read Current
CC
CC
= VCC or V
V
IN
= VCC Max,
V
CC
V
= VCC or V
OUT
= VCC Max,
V
CC
SS
CE = VCC ± 0.2 V
= VCC Max, CE = VIL,
V
CC
OE = VIH, I
OUT
= 0 mA,
at 5 MHz
SS
1.0 ±20 µA
1.0 20 µA
0.4 0.8 mA
20 40 mA
V
I
CC2
V
IL
V
IH
V
OL
V
OH
Notes: 1. One Flash device acti ve, seven in standby.
Active Write Current
CC
Input Low Voltage 0.8 V
Input High Voltage 2.4 V
Output Low Voltage IOL = 3.2 mA 0.40 V
Output High Voltage IOH = -2.0 mA 3.8 V
CE = VIL,WE = VIL,
Programming in Progress
20 40 mA
D.C. Characteristics, Word-Wide Operation
Symbol Parameter Condition Min Typ Max Units
= VCC Max,
V
I
LI
I
LO
I
SB
Input LeakageCurrent
Output Leakage Current
VCC Standby Current
CC
V
= VCC or V
IN
= VCC Max,
V
CC
V
= VCC or V
OUT
= VCC Max,
V
CC
SS
CE = VCC ± 0.2 V
SS
1.0 ±20 µA
1.0 20 µA
0.4 0.8 mA
V
OE = VIH, I
I
CC1
(1)
V
Active Read Current
CC
at 5 MHz
V
I
CC2
V
IL
V
IH
V
OL
V
OH
Notes: 1. Two Flash devices active, six in standby.
Active Write Current
CC
Input Low Voltage 0.8 V
Input High Voltage 2.4 V
Output Low Voltage IOL = 3.2 mA 0.40 V
Output High Voltage IOH = -2.0 mA 3.8 V
CE = VIL, WE = VIL,
Programm ing in Progress
= VCC Max, CE = VIL,
CC
OUT
= 0 mA,
40 80 mA
40 80 mA
9
Page 10
A.C. Read Characteristics
Symbol Parameter Min Max Units
t
RC
t
CE
t
ACC
t
OE
t
Lz
t
DF
t
OLZ
t
DF
t
OH
t
WC
Read Cycle Time 200 ns
Chip Enable Access Time 200 ns
Address Access Time 200 ns
Output Enable Access Time 100 ns
Chip Enable to Output in Low Z 5 ns
Chip Disable to Output in High Z 60 ns
Output Enable to Output in Low Z 5 ns
Output Disable to Output in High Z 60 ns
Output Hold Time fro m First of Address, CE, or OE Change 5 ns
Write Recovery Time B efore Read 10 ms
Input test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
A.C. Read Waveforms
POWER-UP,
STANDBY
ADDRESS ADDRESSES STABLE
CE
OE
WE
DATA
VCC
Note:
1.
CE refers to CE
5.0 V
0V
, and/or CE
1
(1)
DEVICE AND
ADDRESS
SELECTION
t
WC
t
CE
t
OLZ
t
LZ
t
ACC
2
OUTPUT
ENABLED
t
OE
t
RC
DATA
VALID
t
OUTPUT VALID
OH
STANDBY,
POWER-DOWN
t
DF
t
DF
HIGH Z
10 AT5FC001
Page 11
AT5FC001
Write Cycle Characteristics
Symbol Parameter Min Max Units
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Write Cycle Time 10 ms
Address Set-up Time 10 ns
Address Hold Time 60 ns
Data Set-up Time 60 ns
Data Hold Time 10 ns
Write Pulse Width 100 ns
Byte Load Cycle Time 150 µs
Write Pulse Width High 100 ns
A.C. Write Waveforms (Byte Mode)
OE
CE
2
CE
1
WE
A0
A1-A7
A8-A19
DATA
Notes:
1. A18 and A19 specify the pair of AT29C010A devices to be
written, while A0 controls the selection of even and odd bytes.
A0, A18 and A19 must be valid throughout the entire
pulse.
2. A8 through A17 must specify the sector address during each high
to low transition of
t
AS
WE (or CE).
BYTE
ADDRESS
SECTOR
ADDRESS
BYTE 0 BYTE 1 BYTE 254BYTE 2 BYTE 255
t
WP
t
AH
t
DS
WE low
t
WPH
t
t
BLC
t
DH
3.
OE must be high when WE and CE are both low.
All bytes that are not loaded within the sector being pro-
4.
WC
grammed will be indeterminate.
11
Page 12
A.C. Write Waveforms (Word Mode)
OE
CE
1,2
WE
A1-A7
t
AS
BYTE
ADDRESS
t
WP
t
AH
t
DH
t
WPH
t
BLC
t
WC
A8-A19
SECTOR
ADDRESS
t
DS
DATA
WORD 0 WORD 1
1. A18 and A19 specify the pair of AT29C010A devices to be written; they must be valid throughout the entire
WE low pulse. A0 is
don’t care.
2. A8 through A17 must specify the sector address during each high
to low transition of
WE (or CE).
WORD 2
WORD 126
3.
OE must be high when WE and CE are both low.
4.
All bytes that are not loaded within the sector being pro-
WORD 127
grammed will be indeterminate.
12 AT5FC001
Page 13
AT5FC001
Software Data Protected Programming Algorithm
Device 01234567
Data
Address
Data
Address
Data
Address
Writes
Enabled
Note: 1. Load 3 bytes to corresponding Flash chip segment individually to enable software data protection.
Software Data Protected Disable Algorithm
AA
0AAAA
55
05554
A0
0AAAA
Write
Bytes
AA
0AAAB
55
05555
A0
0AAAB
Write
Bytes
AA
4AAAA
55
45554
A0
4AAAA
Write
Bytes
AA
4AAAB
55
45555
A0
4AAAB
Write
Bytes
(1)
(1)
AA
8AAAA
55
85554
A0
8AAAA
Write
Bytes
AA
8AAAB
55
85555
A0
8AAAB
Write
Bytes
AA
CAAAA
55
C5554
A0
CAAAA
Write
Bytes
AA
CAAAB
55
C5555
A0
CAAAB
Write
Bytes
Device 01234567
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Writes
Enabled
Note: 1. Load 6 bytes to corresponding Flash chip segment individually to disable software data protection.
AA
0AAAA
55
05554
80
0AAAA
AA
0AAAA
55
05554
20
0AAAA
Write
Bytes
AA
0AAAB
55
05555
80
0AAAB
AA
0AAAB
55
05555
20
0AAAB
Write
Bytes
AA
4AAAA
55
45554
80
4AAAA
AA
4AAAA
55
45554
20
4AAAA
Write
Bytes
AA
4AAAB
55
45555
80
4AAAB
AA
4AAAB
55
45555
20
4AAAB
Write
Bytes
AA
8AAAA
55
85554
80
8AAAA
AA
8AAAA
55
85554
20
8AAAA
Write
Bytes
AA
8AAAB
55
85555
80
8AAAB
AA
8AAAB
55
85555
20
8AAAB
Write
Bytes
AA
CAAAA
55
C5554
80
CAAAA
AA
CAAAA
55
C5554
20
CAAAA
Write
Bytes
AA
CAAAB
55
C5555
80
CAAAB
AA
CAAAB
55
C5555
20
CAAAB
Write
Bytes
13
Page 14
Ordering Information
t
ACC
(ns)
200 AT5FC001-20 PCMCIA Type 1 Commercial
Ordering Code Package Operation Range
(0°C to 70°C)
Packaging Information
PCMCIA, Type 1 PC Memory Card
Dimensions in millimeters
85.6 0.2mm
10.0 MIN. (mm)
10.0 MIN. (mm)
54.0 0.1mm
3.3 0.1mm
FRONT SIDE
34
68
BACK SIDE
1
35
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14 AT5FC001
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