Datasheet AT52BR1672T-85CI, AT52BR1674-85CI, AT52BR1672-85CI, AT52BR1674T-85CI Datasheet (ATMEL)
Page 1
Features
• 16-Mbit Flash and 2-Mbit/4-Mbit SRAM
• Single 66-ball 8 mm x 10 mm x 1.2 mm CBGA Package
• 2.7V to 3.3V Operating Voltage
Flash
• 2.7V to 3.3V Read/Write
• AccessTime–85ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
• Fast Word Program Time – 20 µs
• Fast Sector Erase Time – 300 ms
• Dual-plane Organization, Permitting Concurrent Read While Program/Erase
– Memory Plane A: Eight 4K Word and Seven 32K Word Sectors
– Memory Plane B: Twenty-four 32K Word Sectors
• Erase Suspend Capability
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
–30mAActive
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Accelerated Program/Erase Operations
• RESET Input for Device Initialization
• Sector Lockdown Support
• Top/Bottom Block Configuration
• 128-bit Protection Register
16-megabit
Flash and
2-megabit/
4-megabit
SRAM Stack
Memory
AT52BR1672(T)
AT52BR1674(T)
SRAM
• 2-megabit (128K x 16)/4-megabit (256K x 16)
• 2.7V to 3.3V V
• 70 ns Access Time
• Fully Static Operation and Tri-state Output
• 1.2V (Min) Data Retention
• Industrial Temperature Range
Device Number
AT52BR1672(T) 12M + 4M 16M (1M x 16) 2M (128K x 16)
AT52BR1674(T) 12M + 4M 16M (1M x 16) 4M (256K x 16)
Operating Voltage
CC
Flash Plane
Architecture
Flash
Configuration
SRAM
Configuration
Preliminary
Rev. 2604B–STKD–09/0 2
1
Page 2
CBGA Top View
1
2
45678910
3
11 12
A
NC
NC
NC
A11
A15
A14
A13
A12
GND
NC
NC
NC
B
A16
A10
A8
I/O15
SWE
I/O14
I/O7
A9
C
I/O13
I/O6
I/O4
WE
RDY BUSY
I/O5
D
I/O12
SCS2
SVcc
SGND
RESET
Vcc
E
NC
Vpp
A19
I/O10
I/O2
I/O3
I/O11
F
SLB
SUB
SOE
I/O9
I/O8
I/O0
I/O1
G
A18
A17
A7
A3
A2
A1
SCS1
A6
H
NC
NC
NC
A0
A4
A5
CE
GND
OE
NC
NC
NC
Pin Configurations
Pin Name Function
A0 - A16 Flash/SRAM Common Address Input for 2M SRAM
A0 - A17 Flash/SRAM Common Address Input for 4M SRAM
A18 - A19 Flash Address Input
CE
OE
/SOE Flash/SRAM, Output Enable
WE
/SWE Flash/SRAM, Write Enable
Flash Chip Enable
VCC Flash Power Supply
VPP Optional Flash Power Supply for Faster Program/Erase Operations
I/O0-I/O15 Data Inputs/Outputs
SCS1
, SCS2 SRAM Chip Select
RDY/BUSY
Flash Ready/Busy Output
SVCC SRAM Power Supply
GND/SGND Flash/SRAM GND
SUB
SLB
SRAM Upper Byte
SRAM Lower Byte
NC No Connect
RESET
Flash Reset
2
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 3
AT52BR1672(T)/1674(T)
Description The AT52BR1672(T) combines a 16-megabit Flash (1M x 16) and a 2-megabit SRAM (orga-
nized as 128K x 16) in a stacked CBGA package; while the AT52BR1674(T) combines a 16megabit Flash (1M x 16) and a 4-megabit SRAM (organized as 256K x 16) in a stacked CBGA
package. Both devices operate at 2.7V to 3.3V in the industrial temperature range. The modules use a 16-megabit Flash with dual plane architecture for concurrent read/write operations.
The Flash is organized as 12M + 4M for planes B and A, respectively.
Block Diagram
WEOE SWESOE
RESET
CE
FLASH SRAM
RDY/BUSY
ADDRESS
SCS1
Absolute Maximum Ratings
Temperature under Bias .................................. -40°Cto+85°C
Storage Temperature ..................................... -55°Cto+150°C
All Input Voltages
except V
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
Voltage on V
with Respect to Ground ..................................-0.2V to + 6.25V
Voltage on RESET
with Respect to Ground ...................................-0.2V to +13.5V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
and RESET
PP
PP
DC and AC Operating Range
DATA
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
AT52BR1672(T)/1674(T)
Operating Temperature (Case) Industrial -40°C-85°C
V
Power Supply 2.7V to 3.3V
CC
2604B–STKD–09/02
3
Page 4
16-megabit Flash Description
The 16-megabit Flash memory organized as 1,048,576 words of 16 bits each. The x16 data
appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations.The
device has CE
reprogrammed using a single 2.7V power supply, making it ideally suited for in-system
programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see Sector Lockdown section).
The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice
versa. This operation allows improved system performance by not requiring the system to wait
for a program or erase operation to complete before a read is performed. To further increase
the flexibility of the device, it contains an Erase Suspend feature. This feature will put the
erase on hold for any amount of time and let the user read data from or program data to any of
the remaining sectors within the same memory plane. There is no reason to suspend the
erase operation if the data to be read is in the other memory plane. The end of a program or
an erase cycle is detected by the Ready/Busy
and OE control signals to avoid any bus contention. This device can be read or
pin, Data Polling or by the toggle bit.
The VPP pin provides faster program/erase times. With V
erase operations are accelerated.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Word Program) is exited by powering down
the device, or by pulsing the RESET
to V
. Erase and Erase Suspend/Resume commands will not work while in this mode; if
CC
entered they will result in data being programmed into the device. It is not recommended that
the six-byte code reside in the software of the final product but only exist in external programming code.
pin low for a minimum of 500 ns and then bringing it back
at 5.0V or 12.0V, the program and
PP
4
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 5
16-megabit Flash Memory Block Diagram
I/O0 - I/O15
AT52BR1672(T)/1674(T)
A0 - A19
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
OUTPUT
BUFFER
OUTPUT
IDENTIFIER
MULTIPLEXER
COMPARATOR
PLANE B
SECTORS
REGISTER
STATUS
REGISTER
DATA
Y-GATING
INPUT
BUFFER
DATA
REGISTER
COMMAND
REGISTER
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
RDY/BUSY
VPP
VCC
GND
2604B–STKD–09/02
PLANE A SECTORS
5
Page 6
Device Operation
READ: The 16-megabit Flash is accessed like an EPROM. When CE and OE are low and WE
is high, the data stored at the memory location determined by the address pins are asserted
on the outputs. The outputs are put in the high-impedance state whenever CE
or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE
or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE
CE
or WE. Standard microprocessor write timings are used. The address locations used in the
or WE, whichever occurs last. The data is latched by the first rising edge of
command sequences are not affected by entering the command sequences.
RESET: A RESET
a logic high level, the device is in its standard operating mode. A low level on the RESET
input pin is provided to ease some system applications. When RESET is at
input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET
pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is t
EC
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE
the 30H data input command is latched on the rising edge of WE
the rising edge of WE
of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a section is t
edge of the sixth cycle while
. The sector erase starts after
. When the sec-
SEC
tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the operation terminating in 2 µs.
.
WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”)
on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required
internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”;onlyerase
operations can convert “0”sto“1”s. Programming is completed after the specified t
time. The Data
Polling feature or the Toggle Bit feature may be used to indicate the end of a
BP
cycle
program cycle.
VPP PIN: The circuitry of the 16-megabit Flash is designed so that the device can be programmed or erased from the V
than or equal to the VCC pin, the device selects the V
6
AT52BR1672(T)/1674(T)
power supply or from the VPP input pin. When VPPis less
CC
supply for programming and erase
CC
2604B–STKD–09/02
Page 7
AT52BR1672(T)/1674(T)
operations. When the VPP pin is greater than the VCCsupply, the device will select the V
PP
input as the power supply for programming and erase operations. The device will allow for
some variations between the V
input and the VCCpower supply in its selection of VCCor V
PP
PP
for program or erase operations. If the VPP pin is within 0.3V of VCCfor 2.7V < VCC<3.3V,
then the program or erase operations will use V
the V
signal is used to accelerate program and erase operations, the VPPmust be in the 5V
PP
± 0.5V or 12V ± 0.5V range to ensure proper operation. The V
and disregard the VPPinput signal. When
CC
pin can be left unconnected.
pp
SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled.
These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is
updated. This feature does not have to be activated; any sector’s usage as a write protected
region is optional to the user.
At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.
SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification
mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on
I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown
feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation.
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is
through reset or power-up cycles. After power-up or reset, the content of a sector that is
locked down can be erased and reprogrammed.
ERASE SUSPEND/ERASE RESUME: TheEraseSuspendcommandallowsthesystemto
interrupt a sector erase operation and then program or read data from a different sector within
the same plane. Since this device has a dual-plane architecture, there is no need to use the
Erase Suspend feature while erasing a sector when you want to read data from a sector in the
other plane. After the Erase Suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
plane that contains the suspended sector enters the erase-suspend-read mode. The system
can then read data or program data to any other sector within the device. An address is not
required during the Erase Suspend command. During a sector erase suspend, another sector
cannot be erased. To resume the sector erase operation, the system must write the Erase
Resume command. The Erase Resume command is a one-bus cycle command, which does
require the plane address (determined by A18 and A19). The device also supports an erase
suspend during a complete chip erase. While the chip erase is suspended, the user can read
from any sector within the memory that is protected. The command sequence for a chip erase
suspend and a sector erase suspend are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see “Operating Modes” on page 13 (for hardware operation) or “Software Product
Identification Entry/Exit” on page 21. The manufacturer and device codes are the same for
both modes.
2604B–STKD–09/02
7
Page 8
128-BIT PROTECTION REGISTER: The 16-megabit Flash contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the Command Definition table on
page 9. To lock out block B, the four-bus cycle Lock Protection Register command must be
used as shown in the Command Definition table. Data bit D1 must be zero during the fourth
bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Protection Register Addressing Table” on page 10 for the address locations in the protection
register. To read the protection register, the Product ID Entry command is given followed by a
normal read operation from an address within the protection register. After reading the protection register, the Product ID Exit command must be given prior to performing any other
operation.
DATA
POLLING: The Flash features Data Polling to indicate the end of a program cycle. Dur-
ing a program cycle an attempted read of the last word loaded will result in the complement of
the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to
read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true
data will be read from the device. Data
Polling may begin at any time during the program
cycle. Please see “Status Bit Table” on page 22 for more details.
TOGGLE BIT: In addition to Data
Polling, the 16-megabit Flash provides another method for
determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle
bit that is available on I/O6. While a sector is erase suspended, a read or a program operation
from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on
page 22 for more details.
RDY/BUSY
another method of detecting the end of a program or erase operation. RDY/BUSY
: For the 16-megabit Flash, an open-drain Ready/Busy output pin provides
is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY
line.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the Flash in the following ways: (a) V
(typical), the program function is inhibited. (b) V
V
sense level, the device will automatically time out 10 ms (typical) before programming. (c)
CC
Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (d)
Noise filter: pulses of less than 15 ns (typical) on the WE
power-on delay: once VCChas reached the
CC
or CE inputs will not initiate a pro-
sense: if VCCis below 1.8V
CC
gram cycle.
INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and
control inputs (OE
operation of the device. The I/O lines can only be driven from 0 to V
OUTPUT LEVELS: For the 16-megabit Flash, output high levels (V
0.2V (not V
levels, V
CC
CCQ
,CEand WE) may be driven from 0 to 5.5V without adversely affecting the
+0.6V.
CC
) are equal to V
). For 2.7V - 3.3V output levels, V
must be tied to VCC. For 1.8V - 2.2V output
CCQ
OH
CCQ
must be regulated to 2.0V ± 10%, while VCCmust be regulated to 2.7V - 3.0V (for
minimum power).
-
8
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 9
AT52BR1672(T)/1674(T)
OUT
30
(1)
2nd Bus
Cycle
(2)
55 555 80 555 AA AAA 55 555 10
IN
3rd Bus
Cycle
4th Bus
Cycle
OUT
5th Bus
Cycle
IN
IN
(7)
6th Bus
Cycle
(3)(4)
(3)(4)
30
60
CommandDefinitioninHex
1st Bus
Command
Sequence
Read 1 Addr D
Chip Erase 6 555 AA AAA
Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
Word Program 4 555 AA AAA 55 555 A0 Addr D
Enter Single Pulse
Program Mode
Single Pulse
Word Prog ram
Sector Lockdown 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
Erase Suspend 1 XXX B0
Erase Resume 1 PA
Product ID Entry 3 555 AA AAA 55 555 90
Product ID Exit
Product ID Exit
Program Protection
Register
Lock Protection
Register - Block B
Status of Block B
Protection
(6)
(6)
Bus
Cycles
6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0
1AddrD
3 555 AA AAA 55 555 F0
1 XXX F0
4 555 AA AAA 55 555 C0 Addr D
4 555 AA AAA 55 555 C0 080 X0
4 555 AA AAA 55 555 90 80 D
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
(5)
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’tCare.
The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’tCare.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see page 11 for
details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.
5. PA is the plane address (A19-A18).
6. Either one of the Product ID Exit commands can be used.
7. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°Cto+125°C
Storage Temperature ..................................... -65°Cto+150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
Voltage on OE
and V
PP
with Respect to Ground ...................................-0.6V to +13.0V
2604B–STKD–09/02
CC
+0.6V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
9
Page 10
Protection Register Addressing Table
Word Use Block A7 A6 A5 A4 A3 A2 A1 A0
0 Factory A 10000001
1 Factory A 10000010
2 Factory A 10000011
3 Factory A 10000100
4 User B 10000101
5 User B 10000110
6 User B 10000111
7 User B 10001000
Note: 1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A19 - A8 = 0.
10
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 11
AT52BR1672(T)/1674(T)
Top Boot 16-megabit Flash (12M + 4M) – Sector Address Table
Plane Sector Size (Words)
B SA0 32K 00000 - 07FFF
B SA1 32K 08000 - 0FFFF
B SA2 32K 10000 - 17FFF
B SA3 32K 18000 - 1FFFF
B SA4 32K 20000 - 27FFF
B SA5 32K 28000 - 2FFFF
B SA6 32K 30000 - 37FFF
B SA7 32K 38000 - 3FFFF
B SA8 32K 40000 - 47FFF
B SA9 32K 48000 - 4FFFF
B SA10 32K 50000 - 57FFF
B SA11 32K 58000 - 5FFFF
B SA12 32K 60000 - 67FFF
B SA13 32K 68000 - 6FFFF
B SA14 32K 70000 - 77FFF
B SA15 32K 78000 - 7FFFF
B SA16 32K 80000 - 87FFF
B SA17 32K 88000 - 8FFFF
B SA18 32K 90000 - 97FFF
B SA19 32K 98000 - 9FFFF
B SA20 32K A0000 - A7FFF
B SA21 32K A8000 - AFFFF
B SA22 32K B0000 - B7FFF
B SA23 32K B8000 - BFFFF
A SA24 32K C0000 - C7FFF
A SA25 32K C8000 - CFFFF
A SA26 32K D0000 - D7FFF
A SA27 32K D8000 - DFFFF
A SA28 32K E0000 - E7FFF
A SA29 32K E8000 - EFFFF
A SA30 32K F0000 - F7FFF
A SA31 4K F8000 - F8FFF
A SA32 4K F9000 - F9FFF
A SA33 4K FA000 - FAFFF
A SA34 4K FB000 - FBFFF
A SA35 4K FC000 - FCFFF
A SA36 4K FD000 - FDFFF
A SA37 4K FE000 - FEFFF
A SA38 4K FF000 - FFFFF
Address Range (A19 - A0)
x16
2604B–STKD–09/02
11
Page 12
Bottom Boot 16-megabit Flash (12M + 4M) – Sector Address Table
x16
Plane Sector Size (Words)
A SA0 4K 00000 - 00FFF
A SA1 4K 01000 - 01FFF
A SA2 4K 02000 - 02FFF
A SA3 4K 03000 - 03FFF
A SA4 4K 04000 - 04FFF
A SA5 4K 05000 - 05FFF
A SA6 4K 06000 - 06FFF
A SA7 4K 07000 - 07FFF
A SA8 32K 08000 - 0FFFF
A SA9 32K 10000 - 17FFF
A SA10 32K 18000 - 1FFFF
A SA11 32K 20000 - 27FFF
A SA12 32K 28000 - 2FFFF
A SA13 32K 30000 - 37FFF
A SA14 32K 38000 - 3FFFF
B SA15 32K 40000 - 47FFF
B SA16 32K 48000 - 4FFFF
B SA17 32K 50000 - 57FFF
B SA18 32K 58000 - 5FFFF
B SA19 32K 60000 - 67FFF
B SA20 32K 68000 - 6FFFF
B SA21 32K 70000 - 77FFF
B SA22 32K 78000 - 7FFFF
B SA23 32K 80000 - 87FFF
B SA24 32K 88000 - 8FFFF
B SA25 32K 90000 - 97FFF
B SA26 32K 98000 - 9FFFF
B SA27 32K A0000 - A7FFF
B SA28 32K A8000 - AFFFF
B SA29 32K B0000 - B7FFF
B SA30 32K B8000 - F7FFF
B SA31 32K C0000 - C7FFF
B SA32 32K C8000 - CFFFF
B SA33 32K D0000 - D7FFF
B SA34 32K D8000 - DFFFF
B SA35 32K E0000 - E7FFF
B SA36 32K E8000 - EFFFF
B SA37 32K F0000 - F7FFF
B SA38 32K F8000 - FFFFF
Address Range (A19 - A0)
12
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 13
AT52BR1672(T)/1674(T)
DC and AC Operating Range
AT52BR1672(T)-85 AT52BR1674(T)-85
Operating Temperature (Case) Industrial -40°C-85°C-40°C-85°C
V
Power Supply 2.7V to 3.3V 2.7V to 3.3V
CC
Operating Modes
Mode CE OE WE RESET V
Read V
Program/Erase
(2)
Standby/Program Inhibit V
Program Inhibit
V
V
IL
V
IL
X
IH
XXV
XV
Output Disable X V
Reset X X X V
V
IL
V
IH
(1)
XVIHXXHigh-Z
XVIHX
IL
XVIHXHigh-Z
IH
V
IH
IL
IH
IH
V
IH
V
IH
IL
Product Identification
Hardware V
Software
(5)
V
IL
V
IL
V
IH
IH
V
IH
Notes: 1. X can be VILor VIH.
2. Refer to AC programming waveforms on page 18.
3. V
= 12.0V ± 0.5V.
H
4. Manufacturer Code: 001FH. Device Code: 00C2H (Top Boot); 00C0H (Bottom Boot).
5. See details under “Software Product Identification Entry/Exit” on page 21.
6. V
can be left unconnected or 0V ≤ VPP≤ 3.3V. For faster erase/program operations, VPPcan be set to 5.0V ± 0.5V or
PP
12V ± 0.5V.
PP
XAiD
(6)
V
PP
Ai I/O
Ai D
OUT
IN
X
XXHigh-Z
A1 - A19 = VIL,A9=V
A1 - A19 = VIL,A9=V
A0 = VIL,A1-A19=V
A0 = VIH,A1-A19=V
(3)
,A0=V
H
(3)
,A0=V
H
Manufacturer Code
IL
Device Code
IH
IL
IL
Manufacturer Code
Device Code
(4)
(4)
(4)
(4)
2604B–STKD–09/02
13
Page 14
DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
I
LO
I
SB1
I
SB2
I
SB3
(1)(2)
I
CC
I
CC1
I
PP1
I
CC2
I
PP2
I
CC3
I
PP3
V
IL
V
IH
V
OL1
V
OL2
V
OH1
V
OH2
Notes: 1. In the erase mode, ICCis 50 mA.
Input Load Current VIN=0VtoV
Output Leakage Current V
=0VtoV
I/O
CC
CC
VCCStandby Current CMOS CE =VCC-0.3VtoV
VCCStandby Current TTL CE =2.0VtoV
CC
CC
10 µA
10 µA
10 µA
1mA
VCCStandby Current TTL CE =2.0VtoVCC,VCC= 2.85V 10 µA
VCCActive Read Current f = 5 MHz; I
=0mA,3.3V≤ V
OUT
CC
30 mA
VCCProgramming Current (VPP=VCC) 45 mA
=0V,VCC=3.0V 10 µA
V
VPPInput Load Current
PP
V
PP=VCC
=3.0V 10 µA
VCCProgramming Current (VPP= 5.0V ± 0.5V) 40 mA
VPPProgramming Current (VPP= 5.0V ± 0.5V) 5mA
VCCProgramming Current (VPP= 12.0V ± 0.5V) 40 mA
VPPProgramming Current (VPP= 12.0V ± 0.5V) 6mA
Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL=2.1mA 0.45 V
Output Low Voltage IOL=1.0mA 0.20 V
I
Output High Voltage
Output High Voltage
2. For 3.3V < V
<3.6V,ICC(max) = 35 mA.
CC
=-400µA
OH
I
=-400µA
OH
I
=-100µA
OH
I
=-100µA
OH
<2.6V
V
CCQ
V
≥ 2.6V
CCQ
<2.6V
V
CCQ
V
≥ 2.6V
CCQ
-0.2
V
CCQ
2.4
-0.1
V
CCQ
2.5
V
V
V
V
14
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 15
AC Read Characteristics
Symbol Parameter
t
t
t
t
t
t
ACC
CE
OE
DF
OH
RO
(1)
(2)
(3)(4)
Address to Output Delay 85 85 ns
CE to Output Delay 85 85 ns
OE to Output Delay 0 40 0 40 ns
CE or OE to Output Float 0 25 0 25 ns
Output Hold from OE,CEor Address, whichever occurred first 0 0 ns
RESET to Output Delay 100 100 ns
AT52BR1672(T)/1674(T)
AT52BR1672(T)-85 AT52BR1674(T)-85
UnitsMin Max Min Max
AC Read Waveforms
(1)(2)(3)(4)
ADDRESS
CE
OE
RESET
OUTPUT
Notes: 1. CE may be delayed up to t
2. OE
may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t
without impact on t
3. t
is specified from OE or CE, whichever occurs first (CL = 5 pF).
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
ACC-tCE
ADDRESS VALID
tCE
tOE
tDF
tOH
VALID
HIGH Z
tACC
tRO
OUTPUT
after the address transition without impact on t
ACC
.
ACC-tOE
after an address change
2604B–STKD–09/02
15
Page 16
Input Test Waveforms and Measurement Level
tR,tF<5ns
Output Test Load
Pin Capacitance
f=1MHz,T=25°C
Symbol Typ Max Units Conditions
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
(1)
46pFV
812pFV
IN
OUT
=0V
=0V
16
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 17
AT52BR1672(T)/1674(T)
AC Word Load Characteristics
Symbol Parameter Min Max Units
t
AS,tOES
t
AH
t
CS
t
CH
t
WP
t
DS
t
DH,tOEH
t
WPH
Address, OE Setup Time 0 ns
Address Hold Time 40 ns
Chip Select Setup Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)40ns
Data Setup Time 30 ns
Data, OE Hold Time 0 ns
Write Pulse Width High 30 ns
AC Word Load Waveforms
WE Controlled
Controlled
CE
2604B–STKD–09/02
17
Page 18
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
t
BPVPP
t
AS
t
AH
t
DS
t
DH
t
WP
t
WPH
t
WC
t
SR/W
t
RP
t
RH
t
EC
t
ECVPP
t
SEC
t
EPS
Word Programming Time (0V < VPP< 4.5V) 20 50 µs
Word Programming Time (VPP> 4.5V) 10 25 µs
Address Setup Time 0ns
Address Hold Time 40 ns
Data Setup Time 30 ns
Data Hold Time 0ns
Write Pulse Width 40 ns
Write Pulse Width High 30 ns
Write Cycle Time 70 ns
Latency between Read a nd Write Operations 50 ns
Reset Pulse Wi dth 500 ns
Reset High Time before Read 50 ns
Chip Erase Cyc le Time (VPP<4.5V) 12 seconds
Chip Erase Cyc le Time (VPP> 4.5V) 6 seconds
Sector Erase Cycle Time (VPP<4.5V) 300 400 ms
Erase or Program Suspen d Time 15 µs
Program Cycle Waveforms
OE
CE
WE
A0- A19
DA
TA
PROGRAM CYCLE
t
WP
t
AS
555
t
WC
t
AH
t
DS
AA
AAA
t
DH
55
555
t
WPH
t
SR/W
ADDRESS
A0
INPUT DATA
t
BP
VALID
READ ADDRESS
t
ACC
OUTPUT
DATA
18
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 19
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
WE
t
WP
t
AS
t
AH
t
DH
t
WPH
AT52BR1672(T)/1674(T)
t
t
EC
t
SR/W
A0 - A19
DATA
555
t
WC
WORD 0
AA
AAA AAA
t
DS
55 55
WORD 1 WORD 2
555
80
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
555
WORD 3
AA
WORD 4
Note 2
Note 3
WORD 5
ADDRESS
VALID
OUTPUT
VALID
t
ACC
2604B–STKD–09/02
19
Page 20
Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
spec in “AC Read Characteristics” on page 15.
OE
Data Polling Waveforms
Toggle Bit Characteristics
Symbol Parameter Min Typ Max Units
(1)
ns
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 50 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
Toggle Bit Waveforms
spec in “AC Read Characteristics” on page 15.
OE
(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The t
specification must be met by the toggling input(s).
OEHP
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
ns
20
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 21
AT52BR1672(T)/1674(T)
Software Product Identification Entry
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 90
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
(2)(3)(5)
MODE
Software Product Identification Exit
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
(1)(6)
(1)
Sector Lockdown Enable Algorithm
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 60
TO
SECTOR ADDRESS
(1)
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A19 (Don’tCare).
2. A1 - A19 = V
Device Code is read for A0 = V
. Manufacturer Code is read for A0 = VIL;
IL
.
IH
Additional Device Code is read for address 0003H
3. The device does not remain in identification mode if powered
down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH.
Device Code: 00C2H (Top Boot); 00C0H (Bottom Boot).
Additional Device Code: 00C8H.
6. Either one of the Product ID Exit commands can be used.
PAUSE 200 µs
(2)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A19 (Don’t
Care).
2. Sector Lockdown feature enabled.
2604B–STKD–09/02
21
Page 22
Status Bit Table
Status Bit
I/O7 I/O6 I/O2
Read Address In Plane A Plane B Plane A Plane B Plane A Plane B
While
Programming in Plane A I/O7
Programming in Plane B DATA I/O7
Erasing in Plane A 0 DATA TOGGLE DATA TOGGLE DATA
Erasing in Plane B DATA 0 DATA TOGGLE DATA TOGGLE
Erase Suspended & Read
Erasing Sector
Erase Suspended & Read
Non-erasing Sector
Erase Suspended &
ProgramNon-erasing Sector
in Plane A
Erase Suspended &
ProgramNon-erasing Sector
in Plane B
1 1 1 1 TOG GLE TOG GLE
DATA DATA DATA DATA DATA DATA
I/O7
DATA I/O7
DATA TOGGLE DATA 1 DATA
DATA TOGGLE DATA 1
DATA TOGGLE DATA TOGGLE DATA
DATA TOGGLE DATA TOGGLE
22
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 23
AT52BR1672(T)/1674(T)
2-megabit SRAM Description
Features
Block Diagram
The 2-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 128K
words by 16 bits. The SRAM uses high-performance full CMOS process technology and is
designed for high-speed and low-power circuit technology. It is particularly well-suited for the
high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
• Fully Static Operation and Tri-state Output
• TTL Compatible Inputs and Outputs
• Battery Backup
– 1.2V (Min) Data Retention
Operation
Current/I
Voltage (V) Speed (ns)
2.7 - 3.3 70 10 10 -40 - 85
A0
ADD INPUT BUFFER
PRE DECODER
DECODER
BLOCK
(mA)
CC
(Max)
ROW DECODER
Standby
Current (µA)
(Max)
Temperature
SENSE AMP
(°C)
I/O0
DATA I/O BUFFER
I/O7
A16
SCS1
SCS2
SOE
SLB
SUB
SWE
DECODER
COLUMN
MEMORY ARRAY
512K X 16
I/O8
WRITE DRIVER
I/O15
2604B–STKD–09/02
23
Page 24
Absolute Maximum Ratings
(1)
Symbol Parameter Rating Unit
V
IN,VOUT
V
CC
T
A
T
STG
P
D
Input/Output Voltage -0.3 to 3.6 V
Power Supply -0.3 to 4.6 V
Operating Temperature -40 to 85 °C
Storage Temperature -55 to 150 °C
Power Dissipation 1.0 W
Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Truth Table
I/O Pin
SCS1 SCS2 SWE SOE SLB
(1)
H
(1)
X
L
XX
(2)
XX
XX HH
LH
(1)
L
HHH
LL
SUB
(2)
Mode
PowerI/O0 - I/O7 I/O8 - I/O15
Deselected High-Z High-Z StandbyX
Output Disabled High-Z High-Z ActiveHL
LHLX
LHHL
Notes: 1. H = V
2. SUB
,L=VIL,X=Don'tCare(VILor VIH)
IH
,SLB(Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O8. When SUB
LH
Write
LL D
LH
Read
LL D
is LOW, data is written or read to the upper byte, I/O9
D
IN
IN
D
OUT
OUT
High-Z
IN
D
IN
High-Z
OUT
D
OUT
- I/O16.
Recommended DC Operating Condition
Symbol Parameter Min Typ Max Unit
V
CC
V
SS
V
IH
(1)
V
IL
Note: 1. Undershoot: V
Supply Voltage 2.3 3.0 3.3 V
Ground 0 0 0 V
Input High Voltage 2.2 VCC+0.3 V
Input Low Voltage -0.2
= -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
IL
(1)
0.4 V
ActiveHL High-Z D
ActiveHL High-Z D
24
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 25
AT52BR1672(T)/1674(T)
DC Electrical Characteristics
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Typ
(1)
Max Unit
I
LI
I
LO
I
CC
I
CC1
Input Leakage Current VSS<VIN<V
Output Leakage Current VSS<V
SCS1
SOE
=VIHor SWE =VILor
SUB
=VIH,SLB=V
CC
OUT<VCC
,
=VIHor SCS2=VILor
IH
Operating Power Supply Current SCS1 =VIL,SCS2=VIH,
V
IN=VIH
or VIL,I
=0mA
I/O
Average Operating Current Cycle Time = 1 µs
I
=0mA,
I/O
SCS1
= 0.2V, SCS2 = VCC-0.2V,
V
≤ 0.2V or VIN≥ VCC-0.2V
IN
Cycle Time = Min,
or V
=0mA
I/O
IL
IL
I
I
SB
SB1
100% Duty, I
=VIL,SCS2=VIH,
SCS1
V
IN=VIH
Standby Current (TTL Input) SCS1 =VIHor SCS2 = V
Standby Current (CMOS Input) SCS1 ≥ VCC-0.2V
or
SCS2 ≤ V
V
OL
V
OH
Output Low IOL=0.5mA 0.4 V
Output High IOH=-0.5mA 2.0 V
SS
+0.2V
Note: 1. Typical values are at VCC=3.0V,TA=25°C. Typical values are not 100% tested.
-1 1 µA
-1 1 µA
510mA
46mA
30 45 mA
0.5 mA
LL 0.4 10 µA
SL 2 µA
Capacitance
(1)
(Temp = 25°C, f = 1.0 M Hz)
Symbol Parameter Condition Max Unit
C
IN
C
OUT
Note: 1. These parameters are sampled and not 100% tested.
Input Capacitance (Add, SCS1,
SCS2, SLB
,SUB,SWE,SOE)
Output Capacitance (I/O) V
=0V 8 pF
V
IN
=0V 10 pF
I/O
2604B–STKD–09/02
25
Page 26
AC Characteristics
TA=-40°Cto85°C, Unless Otherwise Specified
# Symbol Parameter
70 ns
UnitMin Max
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
22 t
23 t
RC
AA
ACS
OE
BA
CLZ
OLZ
BLZ
CHZ
OHZ
BHZ
OH
WC
CW
AW
BW
AS
WP
WR
WHZ
DW
DH
OW
Read Cycle Time 70 ns
Address Access Time 70 ns
Chip Select Access Time 70 ns
Output Enable to Output Valid 35 ns
SLB,SUBAccess Time 35 ns
Chip Select to Output in Low Z 5 ns
Output Enable to Output in Low Z 0 ns
SLB,SUBEnable to Output in Low Z 0 ns
Chip Deselection to Output in High Z 0 30 ns
Out Disable to Output in High Z 0 30 ns
SLB,SUBDisable to Output in High Z 0 30 ns
Output Hold from Address Change 10 ns
WriteCycleTime 70 ns
Chip Selection to End of Write 60 ns
Address Valid to End of Write 60 ns
SLB,SUBValidtoEndofWrite 60 ns
Address Setup Time 0 ns
Write Pulse Width 50 ns
Write Recovery Time 0 ns
Write to Output in High Z 0 25 ns
Data to Write Time Overlap 30 ns
Data Hold from Write Time 0 ns
Output Active from End of Write 5 ns
AC Test Conditions
TA = - 4 0 °Cto85°C, Unless Otherwise Specified
Parameter Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 5 pF + 1 TTL Load CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
26
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 27
Output Test Load
Timing Diagrams
AT52BR1672(T)/1674(T)
Read Cycle 1
(1),(4)
Read Cycle 2
ADDRESS
SUB, SLB
DATA OUT
(1),(2),(4)
ADDRESS
DATA OUT
SCS1
SCS2
SOE
HIGH-Z
PREVIOUS DATA
t
RC
t
AA
t
ACS
t
BA
t
OE
(3)
t
OLZ
(3)
t
BLZ
(3)
t
CLZ
t
RC
t
AA
t
OH
DATA VALID
DATA VALID
t
OH
(3)
t
CHZ
(3)
t
BHZ
(3)
t
OHZ
t
OH
Read Cycle 3
(1),(2),(4)
SCS1
SUB, SLB
SCS2
DATA OUT
t
t
ACS
CLZ
(3)
DATA VALID
(3)
t
CHZ
Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE
=VIL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1
in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
27
2604B–STKD–09/02
Page 28
WriteCycle1(SWEControlled)
ADDRESS
SCS1
(1),(4),(8)
t
WC
t
CW
t
WR
(2)
SCS2
SUB, SLB
SWE
DATA IN
HIGH-Z
t
AS
t
AS
DATA OUT
WriteCycle2(SCS1, SCS2 Controlled)
ADDRESS
t
AS
SCS1
SCS2
SUB, SLB
(1),(4),(8)
t
t
WHZ
t
AW
AW
t
BW
(3)(7)
t
WC
t
t
BW
CW
t
WP
DATA VALID
t
DW
t
WR
t
DH
t
OW
(5) (5)
(2)
t
WP
SWE
DATA IN
DATA OUT
t
DW
HIGH-Z
DATA VALID
HIGH-Z
t
DH
Notes: 1. A write occurs during the overlap of a low SWE,alowSCS1, a high SCS2 and a low SUB and/or SLB.
2. t
is measured from the earlier of SCS1,SLB,SUB,orSWEgoing high or SCS2 going low to the end of write cycle.
WR
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1
the SWE
,SLBand SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1
in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
28
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 29
AT52BR1672(T)/1674(T)
Data Retention Electric Characteristic
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Typ Max Unit
V
DR
VCCfor Data Retention SCS1 >VCC-0.2V,
1.2 3.3 V
SCS2 ≤ 0.2V or
V
-0.2V,
CC
V
≤ VIN≤ V
I
CCDR
t
CDR
t
R
SS
Data Retention Current VCC=3.0V,
SCS1
SCS2 ≤ V
≤ VIN≤ V
V
SS
Chip Deselect to Data
Retention Time
See Data Retention Timing Diagram
Operating Recovery Time t
CC
>VCC-0.2Vor
+0.2Vor
SS
CC
(1)
0.4
0ns
(2)
RC
Notes: 1. Typical values are under the condition of TA=25°C. Typical values are sampled and not 100% tested.
2. t
is read cycle time.
RC
Data Retention Timing Diagram 1
VCC
2.3V
VDR
SCS1
IH
t
CDR
DATA RETENTION MODE
SCS1 > VCC - 0.2V
t
R
9.5 µA
0.7 µA
ns
VSS
Data Retention Timing Diagram 2
VCC
2.3V
SCS2
VDR
0.4V
VSS
t
CDR
DATA RETENTION MODE
SCS2 < 0.2V
t
R
2604B–STKD–09/02
29
Page 30
4-megabit SRAM Description
Features
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K
words by 16 bits. The SRAM uses high-performance full CMOS process technology and is
designed for high-speed and low-power circuit technology. It is particularly well-suited for the
high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
• Fully Static Operation and Tri-state Output
• TTL Compatible Inputs and Outputs
• Battery Backup
– 1.2V (Min) Data Retention
Block Diagram
Operation
Current/I
Voltage (V) Speed (ns)
2.7 - 3.3 70 5 15 -40 - 85
A0
DECODER
ADD INPUT BUFFER
A17
SCS1
SCS2
SOE
SLB
SUB
SWE
PRE DECODER
BLOCK
DECODER
COLUMN
(mA)
CC
(Max)
ROW DECODER
MEMORY ARRAY
256K X 16
Standby
Current (µA)
(Max)
Temperature
(°C)
SENSE AMP
DATA I/O BUFFER
WRITE DRIVER
I/O0
I/O7
I/O8
I/O15
30
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 31
AT52BR1672(T)/1674(T)
Absolute Maximum Ratings
(1)
Symbol Parameter Rating Unit
V
IN,VOUT
V
CC
T
A
T
STG
P
D
Input/Output Voltage -0.3 to 3.6 V
Power Supply -0.3 to 4.6 V
Operating Temperature -40 to 85 °C
Storage Temperature -55 to 150 °C
Power Dissipation 1.0 W
Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Truth Table
I/O Pin
SCS1 SCS2 SWE SOE SLB
(1)
H
(1)
X
L
XX
(2)
XX
XX HH
SUB
(2)
Mode
PowerI/O0 - I/O7 I/O8 - I/O15
Deselected High-Z High-Z StandbyX
LH
(1)
L
HHH
Output Disabled High-Z High-Z ActiveHL
LL
LHLX
LHHL
Notes: 1. H = V
2. SUB
,L=VIL,X=Don'tCare(VILor VIH)
IH
,SLB(Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB
LH
HL High-Z D
Write
LL
LH
HL High-Z D
Read
LL
is LOW, data is written or read to the upper byte, I/O8
D
IN
D
IN
D
IN
D
OUT
D
OUT
D
OUT
High-Z
IN
D
IN
High-Z
High-Z
OUT
D
OUT
High-Z
- I/O15.
Recommended DC Operating Condition
Symbol Parameter Min Typ Max Unit
V
CC
V
SS
V
IH
(1)
V
IL
Note: 1. Undershoot: V
Supply Voltage 2.7 3.0 3.3 V
Ground 0 0 0 V
Input High Voltage 2.2 VCC+0.3 V
Input Low Voltage -0.31
= -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
IL
(1)
0.6 V
Active
Active
2604B–STKD–09/02
31
Page 32
DC Electrical Characteristics
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Max Unit
I
LI
I
LO
I
CC
I
CC1
I
SB
I
SB1
V
V
OL
OH
Input Leakage Current VSS<VIN<V
Output Leakage Current VSS<V
SCS1
SOE
=VIHor SWE =VILor
SUB
=VIH,SLB=V
CC
OUT<VCC
,
=VIHor SCS2=VILor
IH
Operating Power Supply Current SCS1 =VIL,SCS2=VIH,
V
IN=VIH
or VIL,I
=0mA
I/O
Average Operating Current SCS1 =VIL,SCS2=VIH,
V
IN=VIH
100% Duty, I
SCS1
V
IN
or VIL,CycleTime=Min
=0mA
I/O
< 0.2V, SCS2 > VCC-0.2V
<0.2VorVIN>VCC-0.2V,
-1 1 µA
-1 1 µA
5mA
35 mA
5mA
CycleTime=1µs
100% Duty, I
Standby Current (TTL Input) SCS1 =VIHor SCS2 = VILor
SUB
,SLB=V
VIN=VIHor V
Standby Current (CMOS Input) SCS1 >VCC-0.2Vor
SCS2 < V
SUB
,SLB>VCC-0.2V
V
IN>VCC
V
IN<VSS
=0mA
I/O
IH
IL
+0.2Vor
SS
-0.2Vor
+0.2V
0.5 mA
SL 4 µA
LL 15 µA
Output Low IOL=0.1mA 0.4 V
Output High IOH=-0.1mA 2.4 V
Capacitance
(1)
(Temp = 25°C, f = 1.0 M Hz)
Symbol Parameter Condition Max Unit
C
IN
C
OUT
Note: 1. These parameters are sampled and not 100% tested.
32
Input Capacitance (Add, SCS1,
SCS2, SLB
,SUB,SWE,SOE)
Output Capacitance (I/O) V
AT52BR1672(T)/1674(T)
=0V 8 pF
V
IN
=0V 10 pF
I/O
2604B–STKD–09/02
Page 33
AC Characteristics
TA=-40°Cto85°C, Unless Otherwise Specified
AT52BR1672(T)/1674(T)
70 ns
# Symbol Parameter
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
22 t
23 t
RC
AA
ACS
OE
BA
CLZ
OLZ
BLZ
CHZ
OHZ
BHZ
OH
WC
CW
AW
BW
AS
WP
WR
WHZ
DW
DH
OW
Read Cycle Time 70 ns
Address Access Time 70 ns
Chip Select Access Time 70 ns
Output Enable to Output Valid 35 ns
SLB,SUBAccess Time 70 ns
Chip Select to Output in Low Z 10 ns
Output Enable to Output in Low Z 5 ns
SLB,SUBEnable to Output in Low Z 10 ns
Chip Deselection to Output in High Z 0 30 ns
Out Disable to Output in High Z 0 30 ns
SLB,SUBDisable to Output in High Z 0 30 ns
Output Hold from Address Change 10 ns
WriteCycleTime 70 ns
Chip Selection to End of Write 60 ns
Address Valid to End of Write 60 ns
SLB,SUBValidtoEndofWrite 60 ns
Address Setup Time 0 ns
Write Pulse Width 50 ns
Write Recovery Time 0 ns
Write to Output in High Z 0 20 ns
Data to Write Time Overlap 30 ns
Data Hold from Write Time 0 ns
Output Active from End of Write 5 ns
UnitMin Max
AC Test Conditions
TA = - 4 0 °Cto85°C, Unless Otherwise Specified
Parameter Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 5 pF + 1 TTL Load CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
2604B–STKD–09/02
33
Page 34
Output Test Load
Timing Diagrams
Read Cycle 1
(1),(4)
Read Cycle 2
DATA OUT
(1),(2),(4)
ADDRESS
DATA OUT
ADDRESS
SCS1
SCS2
SUB, SLB
SOE
HIGH-Z
PREVIOUS DATA
t
RC
t
AA
t
ACS
t
BA
t
OE
(3)
t
OLZ
(3)
t
BLZ
(3)
t
CLZ
t
RC
t
AA
t
OH
DATA VALID
DATA VALID
t
OHZ
t
OH
(3)
t
CHZ
(3)
t
BHZ
(3)
t
OH
Read Cycle 3
(1),(2),(4)
SCS1
SUB, SLB
SCS2
DATA OUT
t
t
ACS
CLZ
(3)
DATA VALID
(3)
t
CHZ
Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE
=VIL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1
in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
34
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Page 35
AT52BR1672(T)/1674(T)
WriteCycle1(SWEControlled)
(1),(4),(8)
ADDRESS
SCS1
SCS2
SUB, SLB
SWE
DATA IN
HIGH-Z
t
AS
t
AS
DATA OUT
WriteCycle2(SCS1, SCS2 Controlled)
ADDRESS
t
AS
SCS1
(1),(4),(8)
t
t
WHZ
AW
t
WC
t
CW
t
BW
(3)(7)
t
WC
t
CW
t
WP
DATA VALID
t
DW
t
WR
t
WR
(2)
t
DH
t
OW
(5) (5)
(2)
t
AW
SCS2
t
BW
SUB, SLB
t
WP
SWE
DATA IN
DATA OUT
t
DW
HIGH-Z
DATA VALID
HIGH-Z
t
DH
Notes: 1. A write occurs during the overlap of a low SWE,alowSCS1, a high SCS2 and a low SUB and/or SLB.
2. t
is measured from the earlier of SCS1,SLB,SUB,orSWEgoing high or SCS2 going low to the end of write cycle.
WR
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1
the SWE
,SLBand SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1
in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
2604B–STKD–09/02
35
Page 36
Data Retention Electric Characteristic
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Typ
(1)
Max Unit
V
DR
I
CCDR
t
CDR
t
R
VCCfor Data Retention SCS1 >VCC-0.2Vor
SCS2 < V
SUB
,SLB>VCC-0.2V
V
IN>VCC
V
IN<VSS
Data Retention Current Vcc=1.5V,
SCS1
SCS2 < V
SUB
,SLB>VCC-0.2V
V
IN>VCC
V
IN<VSS
+0.2Vor
SS
-0.2Vor
+0.2V
>VCC-0.2Vor
+0.2Vor
SS
-0.2Vor
+0.2V
SL 0.1 2 µA
LL 0.1 10 µA
Chip Deselect to Data
Retention Time
See Data Retention Timing Diagram
Operating Recovery Time t
1.2 3.3 V
0ns
(2)
RC
Note: 1. Typical values are under the condition of TA=25°C. Typical values are sampled and not 100% tested.
is read cycle time.
2. t
RC
Data Retention Timing Diagram 1
VCC
2.7V
VDR
SCS1
IH
t
CDR
DATA RETENTION MODE
SCS1 > VCC - 0.2V
t
R
ns
VSS
Data Retention Timing Diagram 2
VCC
2.7V
SCS2
VDR
0.4V
VSS
36
AT52BR1672(T)/1674(T)
t
CDR
DATA RETENTION MODE
SCS2 < 0.2V
t
R
2604B–STKD–09/02
Page 37
Ordering Information
t
(ns) Voltage Range Ordering Code Package Operation Range
ACC
85 2.7V - 3.3V AT52BR1672(T)-85CI 66C5 Industrial
85 2.7V - 3.3V AT52BR1674(T)-85CI 66C5 Industrial
85 2.7V - 3.3V AT52BR1672-85CI 66C5 Industrial
85 2.7V - 3.3V AT52BR1674-85CI 66C5 Industrial
AT52BR1672(T)/1674(T)
(-40° to 85°C)
(-40° to 85°C)
(-40° to 85°C)
(-40° to 85°C)
Package Type
66C5 66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)
2604B–STKD–09/02
37
Page 38
Package Drawing
66C5 – CBGA
E
Marked A1 Identifier
0.12
C
Seating Plane
C
0.60 REF
D
Top View
Side View
A1
A
E1
e
A1 Ball Corner
1.20 REF
A
B
C
D
E
F
G
H
2
101112
7
89
4
5
6
1
3
Øb
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
e
E 9.90 10.00 10.10
MIN
NOM
MAX
NOTE
E1 – 8.80 –
D 7.90 8.00 8.10
Bottom View
D1 – 5.60 –
A – – 1.20
A1 0.25 – –
e 0.80 BSC
Øb – 0.40 –
38
2325 Orchard Parkway
R
San Jose, CA 95131
66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA)
AT52BR1672(T)/1674(T)
TITLE
DRAWING NO.
66C5
2604B–STKD–09/02
09/19/01
REV.
A
Page 39
Atmel Headquarters Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
AT ME L®is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2604B–STKD–09/02 /0M
Loading...