Datasheet AT49HF010-90TI, AT49HF010-90TC, AT49HF010-90PI, AT49HF010-45JC, AT49HF010-12TI Datasheet (ATMEL)

AT49F010/HF010

1-Megabit
(128K x 8)
5-volt Only
CMOS Flash
Memory

AT49F010
AT49HF010

Features

•

Single Voltage Operation

- 5V Read

- 5V Reprogramming

•

Fast Read Access Time - 45 ns

•

Internal Program Control and Timer

•

8K bytes Boot Block With Lockout

•

Fast Erase Cycle Time - 10 seco nd s

•

Byte By Byte Programming - 10 µs/Byte

•

Hardware Data Protection

•

DATA Polling For End Of Program Detection

•

Low Power Dissipation

- 30 mA Active Current

- 100 µA CMOS Standby Current

•

Typical 10,000 Write Cycles

Pin Configurations

Pin Name Function

A0 - A16 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect

The AT49F010/HF010 are 5-volt-only in-system programmable and erasable Flash
Memories. Their 1-megabit of memory is organized as 131,072 words by 8 bits. Manu­factured with Atmel’s advanced nonvolatile CMOS technology, the devices offer ac­cess times to 45 ns (HF version) with a power dissipation of just 165 mW over the
commercial temperature range. When the device is deselected, the CMOS standby
current is less than 100 µA.

To allow for simple in-system reprogrammability, the AT49F010/HF010 does not re­quire high input voltages for programming. Five-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the AT49F010/HF010 is per­formed by erasing the entire 1 megabit of memory and then programming on a byte
by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle
can be optionally detected by the

DATA polling feature. Once the end of a byte pro-

Description

(continued)

DIP Top View

TSOP Top View

Type 1

PLCC Top View

0852AX–5/97

Device Operation

READ:

The AT49 F010/HF010 is accessed lik e an

EPROM. When

CE and OE are low and WE is high, the
data stored at the memory location determined by the ad­dress pins is asserted on the outputs. The outputs are put
in the high impedance state whenever

CE or OE is high.
This dual-line control gives designers flexibility in prevent­ing bus contention.

ERASURE:

Before a byte can be reprogrammed, the
128K bytes memory array (or 120K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical “1". The entire device can be
erased at one time by using a 6-byte software code. The
chip erase code consists of 6-byte load commands to spe­cific address locations with a specific data pattern (please
refer to the Chip Erase Cycle Waveforms).

After the chip erase has been initiated, the device will in­ternally time the erase operation so that no external clocks
are required. The maximum time needed to erase the
whole chip is t

EC

. If the bo ot block lockout feat ure has
been enable d, the data in the boot sector will not be
erased.

BYTE PROGRAMMING:

Once the memory array is
erased, the device is programmed (to a logical “0") on a
byte-by-byte basis. Please note that a data ”0" cannot be
programmed back to a “1"; only erase operations can con­vert ”0"s to “1"s. Programming is accomplished via the in­ternal device command register and is a 4 bus cycle op­eration (please refer to the Command Definitions table).
The device will automatically generate the required inter­nal program pulses.

The program cycle has addresses latched on the falling
edge of

WE or CE, whichever occurs last, and the data

latched on the rising edge of

WE or CE, whichever occurs

first. Programming is completed after the specified t

BP

cy-

Block Diagram

gram cycle has been detected, a new access for a read or
program can begin. The typical number of program and
erase cycles is in excess of 10,000 cycles.

The optional 8K bytes boot block section includes a repro­gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user s ecure code,

cle time. The

DATA polling feature may also be used to

indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The de­vice has one designated block that has a programming
lockout fea ture. This feature prev ents programming of
data in the designated block once the featur e has been
enabled. The size of the block is 8K bytes. This block, re­ferred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout fea­ture will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address range
of the boot block is 00000H to 01FFFH.

Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular
programming method. To activate the lockout feature, a
series of six program commands to specific addresses
with specific data must be performed. Please refer to the
Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Prod­uct Identification Entry and Exit sections) a read from ad­dress location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identifica­tion code should be used to return to standard operation.

2

AT49F010/HF010

Temperature Under Bias.................-55°C to +125°C

Storage Temperature......................-65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

CC

+ 0.6V

Voltage on OE

with Respect to Ground ................... -0.6V to +13.5V

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or an y ot he r con di t i on s be yo nd those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Absolute Maximum Ratings*

PRODUCT IDENTIFICATION:

The product identification
mode identifies the device and manufacturer as A tmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for
the Atmel product.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING:

The AT49F010/HF010 features

DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin.

DATA
polling may begin at any time during the program cycle.

Command Definition (in Hex)

Command
Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read

1AddrD

OUT

Chip Erase

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Byte
Program

4 5555 AA 2AAA 55 5555 A0 Addr D

IN

Boot Block
Lockout

(1)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

Product ID
Entry

3 5555 AA 2AAA 55 5555 90

Product ID
Exit

(2)

3 5555 AA 2AAA 55 5555 F0

Product ID
Exit

(2)

1 XXXX F0

Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.

2. Either one of the Product ID exit commands can be used.

TOGGLE BIT:

In addition to

DATA polling the
AT49F010/HF010 provides another method for determin­ing the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the device will result in I/O6 tog gling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

Hardware features
protect against inadvertent programs to the
AT49F010/HF010 in the following ways: (a) V

CC

sense: if

V

CC

is below 3.8V (typical), the program function is inhib-

ited. (b) Program inhibit: holding any one of

OE low, CE

high or

WE high inhibits program cycles. (c) Noise filter:

Pulses of less than 15 ns (typical) on the

WE or CE inputs

will not initiate a program cycle.

AT49F010/HF010

3

Operating Modes

Mode

CE OE WE

Ai I/O

Read V

IL

V

IL

V

IH

Ai D

OUT

Program

(2)

V

IL

V

IH

V

IL

Ai D

IN

Standby/Write Inhibit V

IH

X

(1)

X X High Z

Program Inhibit X X V

IH

Program Inhibit X V

IL

X

Output Disable X V

IH

X High Z

Product Identification

Hardware V

IL

V

IL

V

IH

A1 - A16 = VIL, A9 = VH,

(3)

A0 = V

IL

Manufacturer Code

(4)

A1 - A16 = VIL, A9 = VH,

(3)

A0 = V

IH

Device Code

(4)

Software

(5)

A0 = VIL, A1 - A16 = V

IL

Manufacturer Code

(4)

A0 = VIH, A1 - A16 = V

IL

Device Code

(4)

4. Manufacturer Code: 1FH, Device Code: 17H

5. See details unde r Soft ware Produ ct Ide nt if icat io n Ent ry/ Exit.

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

3. V

H

= 12.0V ± 0.5V.

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

Input Load Current VIN = 0V to V

CC

10

µ

A

I

LO

Output Leakage Current V

I/O

= 0V to V

CC

10

µ

A

I

SB1

VCC Standby Current CMOS CE = V

CC

- 0.3V to V

CC

Com. 100

µ

A

Ind. 300

µ

A

I

SB2

VCC Standby Current TTL CE = 2.0V to V

CC

3mA

I

CC

(1)

V

CC

Active Current f = 5 MHz; I

OUT

= 0 mA

Com. 30 mA
Ind. 40 mA

V

IL

Input Low Voltage 0.8 V

V

IH

Input High Voltage 2.0 V

V

OL

Output Low Voltage IOL = 2.1 mA .45 V

V

OH1

Output High Voltage IOH = -400 µA2.4V

V

OH2

Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

Note: 1. In the erase mode, ICC is 90 mA.

DC and AC Operating Range

AT49HF010-45 AT49HF010-55 AT49F010-70 AT49F010-90 AT49F010-12

Operating
Temperature (Case)

Com. 0°C - 70°C0

°

C - 70°C0

°

C - 70°C0

°

C - 70°C0

°

C - 70°C

Ind. -40°C - 85°C-40

°

C - 85°C-40

°

C - 85°C-40

°

C - 85°C-40

°

C - 85°C

V

CC

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

4

AT49F010/HF010

AC Read Characteristics

AT49HF010-45 AT49HF010-55 AT49F010-70 AT49F010-90 AT49F010-12

Symbol Parameter

Min Max Min Max Min Max Min Max Min Max

Units

t

ACC

Address to Output Delay 45 55 70 90 120 ns

t

CE

(1)

CE to Output Delay 45 55 70 90 120 ns

tOE

(2)

OE to Output Delay 25 30 35 0 40 0 50 ns

t

DF

(3, 4)

CE or OE to Output Float025025025025030ns

t

OH

Output Hold from OE,
CE or Address,
whichever occurred first

00000ns

70/90/120 ns

Notes: 1. CE may be delayed up to t

ACC

- tCE after the address

transition without impact on t

ACC

.

2.

OE may be delayed up to tCE - tOE after the falling
edge of

CE without impact on tCE or by t

ACC

- tOE

after an address change without impact on t

ACC

.

3. t

DF

is specified from OE or CE whichever occurs first

(C

L

= 5 pF).

4. This parameter is characterized and is not 100% tested.

AC Read Waveforms

(1, 2, 3, 4)

tR, tF < 5 ns

Input Test Waveforms and
Measurement Level

Output Test Load

45 ns / 55 ns

Pin Capacitance

(f = 1 MHz, T = 25°C)

(1)

Typ Max Units Conditions

C

IN

46pFV

IN

= 0V

C

OUT

812pFV

OUT

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

AT49F010/HF010

5

AC Byte Load Characteristics

Symbol Parameter Min Max Units

t

AS

, t

OES

Address, OE Set-up Time 0 ns

t

AH

Address Hold Time 50 ns

t

CS

Chip Select Set-up Time 0 ns

t

CH

Chip Select Hold Time 0 ns

t

WP

Write Pulse Width (WE or CE) 90 ns

t

DS

Data Set-up Time 50 ns

t

DH

, t

OEH

Data, OE Hold Time 0 ns

t

WPH

Write Pulse Width High 90 ns

AC Byte Load Waveforms

WE Controlled

CE Controlled

6

AT49F010/HF010

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

t

BP

Byte Programming Time 10 50

µ

s

t

AS

Address Set-up Time 0 ns

t

AH

Address Hold Time 50 ns

t

DS

Data Set-up Time 50 ns

t

DH

Data Hold Time 0 ns

t

WP

Write Pulse Width 90 ns

t

WPH

Write Pulse Width High 90 ns

t

EC

Erase Cycle Time 10 seconds

Program Cycle Waveforms

Chip Erase Cycle Waveforms

Note: OE must be high only when WE and CE are both low.

AT49F010/HF010

7

Toggle Bit Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

Data Hold Time 10 ns

t

OEH

OE Hold Time 10 ns

t

OE

OE to Output Delay

(2)

ns

t

OEHP

OE High Pulse 150 ns

t

WR

Write Recovery Time 0 ns

Notes: 1. These paramet ers are ch ara ct eri ze d and not 100% tested.

2. See t

OE

spec in AC Read Charact eri st ic s.

Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

Data Hold Time 10 ns

t

OEH

OE Hold Time 10 ns

t

OE

OE to Output Delay

(2)

ns

t

WR

Write Recovery Time 0 ns

Notes: 1. These paramet ers are ch ara ct eri ze d and not 100% tested.

2. See t

OE

spec in AC Read Charact eri st ic s.

Data Polling Waveforms

Toggle Bit Waveforms

(1, 2, 3)

Notes: 1. Toggling either OE or CE or both OE and CE will

operate toggle bit. The t

OEHP

specificatio n mu st be

met by the toggling input(s).

2. B eginning and ending state of I/O6 will vary.

3. Any address location may be used but the address
should not vary.

8

AT49F010/HF010

ENTER PRODUCT

IDENTIFICATION

MODE

(2, 3, 5)

LOAD DATA 90

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA AA

TO

ADDRESS 5555

Software Product
Identification Entry

(1)

LOAD DATA F0

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA AA

TO

ADDRESS 5555

Software Product
Identification Exit

(1)

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

LOAD DATA F0

TO

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

OR

Notes for software product identification:

1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).

2. A1 - A16 = V

IL

.

Manufacture Code is read for A0 = V

IL

;

Device Code is read for A0 = V

IH

.

3. The device does not remain in identification mode if
powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH
Device Code: 17H

LOAD DATA 80

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

Boot Block Lockout
Feature Enable Algorithm

(1)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA AA

TO

ADDRESS 5555

PAUSE 1 second

(2)

LOAD DATA 40

TO

ADDRESS 5555

Notes for boot block lockout feature enable:

1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).

2. Boot block lockout feature enabled.

AT49F010/HF010

9

Ordering Information

(1)

t

ACC

(ns)

I

CC

(mA)

Ordering Code Package Operation Range

Active Standby

45 30 0.1 AT49HF010-45JC 32J Commercial

AT49HF010-45PC 32P6 (0° to 70°C)
AT49HF010-45TC 32T

40 0.1 AT49HF010-45JI 32J Industrial

AT49HF010-45PI 32P6 (-40° to 85°C)
AT49HF010-45TI 32T

55 30 0.1 AT49HF010-55JC 32J Commercial

AT49HF010-55PC 32P6 (0° to 70°C)
AT49HF010-55TC 32T

40 0.1 AT49HF010-55JI 32J Industrial

AT49HF010-55PI 32P6 (-40° to 85°C)
AT49HF010-55TI 32T

70 30 0.1 AT49F010-70JC 32J Commercial

AT49F010-70PC 32P6 (0° to 70°C)
AT49F010-70TC 32T

40 0.3 AT49F010-70JI 32J Industrial

AT49F010-70PI 32P6 (-40° to 85°C)
AT49F010-70TI 32T

90 30 0.1 AT49F010-90JC 32J Commercial

AT49F010-90PC 32P6 (0° to 70°C)
AT49F010-90TC 32T

40 0.3 AT49F010-90JI 32J Industrial

AT49F010-90PI 32P6 (-40° to 85°C)
AT49F010-90TI 32T

120 30 0.1 AT49F010-12JC 32J Commercial

AT49F010-12PC 32P6 (0° to 70°C)
AT49F010-12TC 32T

40 0.3 AT49F010-12JI 32J Industrial

AT49F010-12PI 32P6 (-40° to 85°C)
AT49F010-12TI 32T

Note: 1. The AT49F010/HF010 has as optional boot block feature. The part number show n in the Ordering Information table is for

devices with the bo ot block in the lower addre ss rang e (i. e., 00000H to 01FFF H ). Use rs requiring the boot blo ck to be in
the higher address rang e should contact Atme l.

Package Type

32J

32 Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)

32P6

32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T

32 Lead, Thin Small Outline Package (TSOP)

10

AT49F010/HF010