Datasheet AT49F2048A-90TI, AT49F2048A-90TC, AT49F2048A-90RI, AT49F2048A-90RC, AT49F2048A-70TI Datasheet (ATMEL)

...
Page 1

Features

Single-voltage Operation
–5V Read – 5V Reprogramming
Fast Read Access Time – 70 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Word (16K Bytes) Boot Block with Programming Lockout – Two 4K Word (8K Bytes) Parameter Blocks – One 112K Word (224K bytes) Main Memory Array Block
Fast Sector Erase Time – 10 seconds
Byte-by-byte or Word-by-word Programming – 50 µs
Hardware Data Protection
Data Polling for End of Program Detection
Low Power Dissipation
– 50 mA Active Current – 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
2-megabit (256K x 8/ 128K x 16) 5-volt Only

Description

The AT49F2048A is a 5-volt-only, 2-megabit Flash memory organized as 262,144 words of 8 bits each or 128K words of 16 bits each. Manufactured with Atmel’s
(continued)

Pin Configurations

Pin Name Function
A0 - A16 Addresses
CE
OE
WE Write Enable
RESET
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (A-1)
BYTE
NC No Connect
NC NC NC
A7 A6 A5 A4 A3 A2 A1 A0
CE
OE I/O0 I/O8 I/O1 I/O9 I/O2
I/O10
I/O3
I/O11
Chip Enable
Output Enable
Reset
I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
SOIC (SOP)
1
44 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
RESET
43
WE
42
A8
41
A9
40
A10
39
A11
38
A12
37
A13
36
A14
35
A15
34
A16
33
BYTE
32
31
I/O15/A-1
30
I/O7
29
I/O14
28
I/O6
27
I/O13
26
I/O5
25
I/O12
24
I/O4
23
VCC
TSOP Top View
Typ e 1
A15 A14 A13 A12 A11 A10
RESET
1 2 3 4 5 6 7
A9
8
A8
9
NC
10
NC
11
WE
12 13
NC
14
NC
15
NC
16
NC
17
NC
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
48
A16
47
BYTE
46
GND
45
I/O15/A-1
44
I/O7
43
I/O14
42
I/O6
41
I/O13
40
I/O5
39
I/O12
38
I/O4
37
VCC
36
I/O11
35
I/O3
34
I/O10
33
I/O2
32
I/O9
31
I/O1
30
I/O8
29
I/O0
28
OE
27
GND
26
CE
25
A0
Note: “•” denotes a white dot marked on
the package.
CMOS Flash Memory
AT49F2048A
Rev. 1159F–04/01
1
Page 2
advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When deselected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F2048A does not require high input voltages for pro­gramming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE
, OE and WE inputs to avoid bus connec­tion. Reprogramming the AT49F2048A is performed by first erasing a block of data and then programming on a byte­by-byte or word-by-word basis.
The device is erased by executing the Erase command sequence; the device internally controls the erase opera­tion. The memory is divided into four blocks for erase oper­ations. There are two 4K word parameter block sections: the boot block and the main memory array block. The

Block Diagram

typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 8K word boot block section includes a repro­gramming lockout feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 5.5 volts or less are used. The boot sector is designed to con­tain user secure code.
The BYTE operate in the byte or word configuration. If the BYTE
pin controls whether the device data I/O pins
pin is set at a logic “1” or left open, the device is in word configu­ration; I/O0 - I/O15 are active and controlled by CE
If the BYTE
pin is set at logic “0”, the device is in byte con-
and OE.
figuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE
and OE. The data I/O pins I/O8 - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.

Device Operation

READ: The AT49F2048A is accessed like an EPROM.
When CE at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high­impedance state whenever CE line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first pow­ered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are dont care inputs for the command codes).
and OE are low and WE is high, the data stored
or OE is high. This dual
112
4
4
04000 03FFF
03000 02FFF
The command sequences are written by applying a low pulse on the WE tively) and OE edge of CE latched by the first rising edge of CE
or CE input with CE or WE low (respec-
high. The address is latched on the falling
or WE, whichever occurs last. The data is
or WE. Standard microprocessor write timings are used. The address loca­tions used in the command sequences are not affected by entering the command sequences.
RESET: A RESET tem applications. When RESET
input pin is provided to ease some sys-
is at a logic high level, the device is in its standard operating mode. A low level on the RESET
input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET
pin, the device
2
AT49F2048A
Page 3
AT49F2048A
returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V signal to the RESET
pin, the boot block array can be repro-
± 0.5V input
grammed even if the boot block program lockout feature has been enabled (see Boot Block Programming Lockout Override section).
ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased state of the memory bits is a logic “1”. The entire device can be erased at one time by using a 6-byte software code.
After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is t
EC
.
CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t
EC
.
If the boot block lockout has been enabled, the chip erase will not erase the data in the boot block; it will erase the main memory block and the parameter blocks only. After the chip erase, the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into four sectors that can be individually erased. There are two 4K word parameter block sections: one boot block, and the main memory array block. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE
edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE ing edge of WE
. The sector erase starts after the ris-
of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. Whenever the main memory block is erased and repro­grammed, the two parameter blocks should be erased and reprogrammed before the main memory block is erased again. Whenever a parameter block is erased and repro­grammed, the other parameter block should be erased and reprogrammed before the first parameter block is erased again. Whenever the boot block is erased and repro­grammed, the main memory block and the parameter blocks should be erased and reprogrammed before the boot block is erased again.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logic “0”) on a byte-by-byte or word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset hap­pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t
cycle time. The Data Polling feature may
BP
also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be acti­vated; the boot blocks usage as a write-protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the soft­ware product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lock­out feature has been enabled and the block cannot be pro­grammed. The software product identification exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout by taking the RESET
pin to 12 volts during the entire chip erase, sector erase or word programming operation. When the RESET
pin is brought back to TTL levels, the boot
block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes on page 5 (for hard­ware operation) or Software Product Identification Entry/Exit on page 10. The manufacturer and device codes are the same for both modes.
POLLING: The AT49F2048A features Data Polling
DATA
to indicate the end of a program cycle. During a program
3
Page 4
cycle, an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sec­tor erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has com­pleted, true data will be read from the device. Data
Polling
may begin at any time during the program cycle. TOGGLE BIT: In addition to Data
Polling, the AT49F2048A provides another method for determining the end of a pro­gram or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program
Command Definition (in Hex)
1st Bus
Command Sequence
Read 1 Addr D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA
Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D
Boot Block
(2)
Lockout
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1 and A15 - A16 (Dont Care).
2. The 8K word boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: (A16-A0) SA = 01XXX for BOOT BLOCK SA = 02XXX for PARAMETER BLOCK 1 SA = 03XXX for PARAMETER BLOCK 2 SA = 1FXXX for MAIN MEMORY ARRAY
Bus
Cycles
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
(3)
(3)
3 5555 AA 2AAA 55 5555 F0
1 xxxx F0
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
(1)
2nd Bus
Cycle
OUT
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F2048A in the following ways: (a) V ical), the program function is inhibited. (b) V delay: once V
has reached the VCC sense level, the
CC
sense: if VCC is below 3.8V (typ-
CC
power-on
CC
device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE inputs will not initiate a program cycle.
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
IN
6th Bus
Cycle
(4)
or CE
30

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
4
AT49F2048A
+ 0.6V
CC
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings may cause permanent dam­age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1159F–04/01
Page 5
AT49F2048A

DC and AC Operating Range

AT49F2048A-70 AT49F2048A-90
Operating Temperature (Case)
Power Supply 5V± 10% 5V± 10%
V
CC

Operating Modes

Mode CE OE WE RESET Ai I/O
Read V
Program/Erase
(2)
Standby/Write Inhibit V
Program Inhibit X X V
Program Inhibit X V
Output Disable X V
Reset X X X V
Product Identification
Hardware V
Software
(5)
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
= 12.0V ± 0.5V.
3. V
H
4. Manufacturer Code: 001FH, Device Code: 0082H
5. See details under Software Product Identification Entry/Exit.
IL
V
IL
IH
IL
Com. 0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C
X
V
IL
V
IH
(1)
IL
IH
V
IL
V
IH
V
IL
XV
IH
XV
XV
V
IH
V
IH
V
IH
IH
V
IH
IH
IH
IL
V
IH
V
IH
Ai D
Ai D
X High-Z
X High-Z
A1 - A16 = VIL, A9 = VH,
A0 = V
IL
A1 - A16 = VIL, A9 = VH,
A0 = V
IH
A0 = VIL, A1 - A16 = V
A0 = VIH, A1 - A16 = V
High-Z
(3)
Manufacturer Code
(3)
Device Code
IL
IL
Manufacturer Code
Device Code
OUT
IN
(4)
(4)
(4)
(4)

DC Characteristics

Symbol Parameter Condition Min Max Units
I
I
I
I
I
V
V
V
V
V
LI
LO
SB1
SB2
CC
(1)
IL
IH
OL
OH1
OH2
Input Load Current VIN = 0V to V
Output Leakage Current V
= 0V to V
I/O
CC
CC
VCC Standby Current CMOS CE = VCC - 0.3V to V
VCC Standby Current TTL CE = 2.0V to V
V
Active Current f = 5 MHz; I
CC
CC
= 0 mA 50.0 mA
OUT
CC
10.0 µA
10.0 µA
100.0 µA
3.0 mA
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA 2.4 V
Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
Note: 1. In the erase mode, ICC is 90 mA.
1159F–04/01
5
Page 6

AC Read Characteristics

Symbol Parameter
t
t
t
t
t
ACC
CE
OE
DF
OH
(1)
(2)
(3)(4)
Address to Output Delay 70 90 ns
CE to Output Delay 70 90 ns
OE to Output Delay 30 0 30 ns
CE or OE to Output Float 0 25 0 25 ns
Output Hold from OE, CE or Address, whichever occurred first
AT49F2048A-70 AT49F2048A-90
UnitsMin Max Min Max
00ns
AC Read Waveforms
(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
t
CE
t
t
ACC
HIGH Z
OE
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to t
2. OE may be delayed up to t
without impact on t
is specified from OE or CE, whichever occurs first (CL = 5 pF).
3. t
DF
ACC
.
OE
- tCE after the address transition without impact on t
ACC
- tOE after the falling edge of CE without impact on tCE or by t
CE
4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and Measurement Level

t
DF
t
OH
.
ACC
- tOE after an address change
ACC

Output Test Load

tR, tF < 5 ns

Pin Capacitance

(f = 1 MHz, T = 25°C)
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
6
AT49F2048A
(1)
Typ Max Units Conditions
46 pF V
812 pF V
IN
OUT
30
= 0V
= 0V
Page 7
AT49F2048A

AC Word Load Characteristics

Symbol Parameter Min Max Units
t
, t
AS
OES
t
AH
t
CS
t
CH
t
WP
t
DS
t
, t
DH
OEH
t
WPH

AC Byte/Word Load Waveforms

WE Controlled

Address, OE Setup Time 0 ns
Address Hold Time 50 ns
Chip Select Setup Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)50ns
Data Setup Time 50 ns
Data, OE Hold Time 0 ns
Write Pulse Width High 40 ns
OE
Controlled
CE
ADDRESS
CE
WE
DATA IN
OE
ADDRESS
WE
t
t
t
AS
CS
AS
t
OES
t
OES
t
t
AH
AH
t
t
WP
DS
t
OEH
t
CH
t
WPH
t
DH
t
OEH
t
CH
CE
DATA IN
t
CS
t
t
WP
DS
t
WPH
t
DH
7
Page 8

Program Cycle Characteristics

Symbol Parameter Min Max Units
t
BP
t
AS
t
AH
t
DS
t
DH
t
WP
t
WPH
t
EC
Byte/Word Programming Time 50 µs
Address Setup Time 0 ns
Address Hold Time 50 ns
Data Setup Time 50 ns
Data Hold Time 0 ns
Write Pulse Width 50 ns
Write Pulse Width High 40 ns
Erase Cycle Time 5 seconds

Program Cycle Waveforms

OE
CE
WE
t
AS
A0-A16
DATA
PROGRAM CYCLE
t
WP
t
AH
5555 2AAA 5555
t
DS
AA 55 A0
t
WPH
t
DH
ADDRESS
INPUT
DATA
t
BP
5555
AA

Sector or Chip Erase Cycle Waveforms

(1)
OE
CE
t
WP
WE
t
AH
t
DS
AA 55 80
BYTE/
WORD 0
BYTE/
WORD 1
A0-A16
DATA
t
AS
5555 2AAA 5555
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 4 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
8
AT49F2048A
t
WPH
t
DH
BYTE/
WORD 2
5555
BYTE/
WORD 3
2AAA Note 2
AA 55 Note 3
BYTE/
WORD 4
BYTE/
WORD 5
t
EC
Page 9
AT49F2048A
Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See t
spec in AC Read Characteristics on page 6.
OE

Data Polling Waveforms

WE
CE
t
OEH
OE
I/O7
A0-A16
t
DH
t
OE
HIGH Z
An
An An AnAn
t
WR
ns
Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
(2)
OE High Pulse 150 ns
Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics on page 6.
Toggle Bit Waveforms
(1)(2)(3)
WE
CE
OE
I/O6
t
t
OEH
DH
t
OEHP
t
OE
HIGH Z
t
WR
ns
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
1159F–04/01
specification must be met by the toggling
OEHP
9
Page 10
Software Product Identification Entry
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
Software Product Identification Exit
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
MODE
OR
(2)(3)(5)
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
(1)(6)
(1)
Boot Block Lockout Enable Algorithm
Notes: 1. Data Format: I/O15 - I/O8 (Dont Care);
I/O7 - I/O0 (Hex) Address Format: A15 - A0 (Hex); A-1 and A15 - A16 (Dont Care).
2. Boot Block Lockout feature enabled.
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
PAUSE 1 second
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
Notes: 1. Data Format: I/O15 - I/O8 (Dont Care);
I/O7 - I/O0 (Hex) Address Format: A15 - A0 (Hex); A-1 and A15 - A16 (Dont Care).
2. A1 - A16 = V
.
IL
Manufacturer Code is read for A0 = V Device Code is read for A0 = V
.
IH
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH
Device Code: 0082H
6. Either one of the Product ID Exit commands can be
used.
10
AT49F2048A
;
IL
Page 11

Ordering Information

I
(mA)
t
ACC
(ns)
70 50 0.3 AT49F2048A-70RC
90 50 0.3 AT49F2048A-90RC
CC
Ordering Code Package Operation RangeActive Standby
AT49F2048A-70TC
50 0.3 AT49F2048A-70RI
AT49F2048A-70TI
AT49F2048A-90TC
50 0.3 AT49F2048A-90RI
AT49F2048A-90TI
44R 48T
44R 48T
44R 48T
44R 48T
AT49F2048A
Commercial (0° to 70°C)
Industrial
(-40° to 85°C)
Commercial (0° to 70°C)
Industrial
(-40° to 85°C)
Package Type
44R 44-lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
48T 48-lead, Thin Small Outline Package (TSOP)
1159F–04/01
11
Page 12
Packaging Information
44R, 44-lead, 0.525" Wide,
Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters)
48T, 48-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches) *
JEDEC OUTLINE MO-142 DD
*Controlling dimension: millimeters
12
AT49F2048A
1159F–04/01
Page 13
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Atmel Smart Card ICs
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Companys standard warranty which is detailed in Atmels Terms and Conditions located on the Companys web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmels products are not authorized for use as critical components in life support devices or systems.
AT ME L®, Cache Logic®, AVR Studio® are the registered trademarks of Atmel Corporation; FPSLIC, FreeRAM and HDLPlanner are the trademarks of Atmel Corporation.
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1159F–04/01/xM
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