Datasheet AT49F1614-90TC, AT49F1614-90CI, AT49F1614-90CC, AT49F1614-70TI, AT49F1614-70TC Datasheet (ATMEL)

Features

•

4.5V to 5.5V Read/Write

•

Access Time - 70 ns

•

Sector Erase Architecture

– Thirty 32K Word (64K byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K byte) Sectors with Individual Write Lockout
– Two 16K Word (32K byte) Sectors with Individual Write Lockout

•

Fast Word Program Time - 10

•

Fast Sector Erase Time - 200 ms

•

Dual Plane Organization, Permitting Concurrent Read while Prog ram/E ra se

– Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
– Memory Plane B: Twenty-Four 32K Word Sectors

•

Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

•

Low Power Operation

– 40 mA Active

µµµµ

–10

A Standby

•

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

•

RESET Input for Device Initialization

•

Sector Program Unlock Command

•

TSOP, CBGA, and

•

Top or Bottom Boot Block Configuration Available

µµµµ

BGA Package Options

µµµµ

s

Description

The AT49F16X4(T) is a 5. 0 volt 16-megabi t Flash memory org anized as 1,048,57 6
words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0

- I/O15; the x 8 da ta ap pear s on I /O0 - I /O7. The m emory is divi ded into 40 b locks for
erase operations. The device i s offered in 48-pin TSO P and 48-ball µBGA packages.
The device has CE
can be read or reprogrammed using a single 5.0V power supply, mak ing it ideally
suited for in-system programming.

, and OE control signals to avoid any bus contention. This device

(continued)

Pin Configurations

16-Megabit
(1M x 16/2M x 8)
5-volt Only
Flash Memory

AT49F1604
AT49F1604T
AT49F1614
AT49F1614T
Adv ance
Information

AT49BV16X4(T)

Pin Name Function

A0 - A19 Addresses
CE
OE
WE Write Enable
RESET
RDY/BUSY
I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

BYTE
NC No Connect
DC Don’t Connect

Chip Enable
Output En able

Reset
READY/BUSY Out put

I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

AT49BV1604

Rev. 0977B–06/98

1

TSOP Top View

1
2
3
4
5
6

H

GFEDCB

VSS

I/O1

I/O3

I/O4

I/O6

VSS

OE

I/O9

I/O11

VCC

I/O13

I/O15

/A-1

CE

I/O8

I/O10

I/O12

I/O14

BYTE

A0

I/O0

I/O2

I/O5

I/O7

A16

A1

A5

NC

A19

A11

A15

A2

A6

A18

NC

A10

A14

A4

A17

NC

RESET

A8

A12

A3

A7

RDY/BUSY

WE

A9

A13

A

A

B
C
D

E

F

1

234567

A13

A14

A15

A16

VCC

GND

A11

A10

A12

I/O14

I/O15

I/O7

A8

WE

A9

I/O5

I/O6

I/O13

NC

RST

NC

I/O11

I/O12

I/O4

NC

A18

NC

I/O2

I/O3

VCC

A19

A17

A6

I/O8

I/O9

I/O10

A7

A5

A3

CE

I/O0

I/O1

A4

A2

A1

A0

GND

OE

8

Type 1

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE

RESET

NC

NC

A19
A18
A17

A7

A6

A5

A4

A3

A2

A1

RESET

RDY/BUSY

A15
A14
A13
A12
A11
A10

A19

WE

A18
A17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48

A16

47

VCC

46

GND

45

I/O15

44

I/O7

43

I/O14

42

I/O6

41

I/O13

40

I/O5

39

I/O12

38

I/O4

37

VCC

36

I/O11

35

I/O3

34

I/O10

33

I/O2

32

I/O9

31

I/O1

30

I/O8

29

I/O0

28

OE

27

GND

26

CE

25

A0

AT49F1604(T)

BGA Top View (Ball Down)

µ

TSOP T op View

Type 1

1
2
3
4
5
6
7

A9

8

A8

9
10

NC

11
12
13

NC

14

NC

15
16
17
18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

48

A16

47

BYTE

46

GND

45

I/O15/A-1

44

I/O7

43

I/O14

42

I/O6

41

I/O13

40

I/O5

39

I/O12

38

I/O4

37

VCC

36

I/O11

35

I/O3

34

I/O10

33

I/O2

32

I/O9

31

I/O1

30

I/O8

29

I/O0

28

OE

27

GND

26

CE

25

A0

AT49F1614(T)

CBGA Top View

The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any se ctor. Once the d ata
protection for a given sector is enabled, the data in that
sector cannot be changed us ing input levels between
ground and V

The device is segmented into two memory planes. Reads

CC

.

from memory plane B may be performed even while pro­gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by no t requiri ng the syst em to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it

2

AT49F16X4(T)

contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memo ry plane. There is no rea son
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an Erase
cycle is det e cte d by t he Re ady / Bu sy

pin, Data polling, or by

the toggle bit.
A six byte command (bypass unlock) sequence to remove

the requirement of entering the three byte prog ram
sequence is offered to further improve programming time.
After entering the six byte code, only single pulse s on the
write control lines are required for writing into the device.
This mode (single pulse byte/word program) is exited by

AT49F16X4(T)

powering down the device, or by pulsing the RESET
low and then bringing it back to V

. Erase and Erase Sus-

CC

pin

pend/Resume commands will not work while in this mode;
if entered they will result in data being programmed into the
device. It is not recommended that the six byte code reside
in the software of the final produ ct b ut only exist in external
programming code.

The BYTE
operate in the byte or word configuration. If the BYTE

pin controls whethe r the device data I/O pins

pin is

Block Diagram

I/O0 - I/O15/A-1

OUTPUT
BUFFER

IDENTIFIER

REGISTER

A0 - A19

INPUT

BUFFER

ADDRESS

LATCH

Y-DECODER

X-DECODER

OUTPUT

MULTIPLEXER

STATUS

REGISTER

DATA

COMPARATOR

Y-GATING

PLANE B

SECTORS

set at logic “1”, the device is in word configuration, I/O0­I/O15 are active and controlled by CE

If the BYTE

pin is set at logic “0”, the devi ce is in byte con-

and OE.

figuration, and only data I/O pins I/O0-I/O7 are active and
controlled by CE

and OE. The data I/O pins I/O8-I/O14 are
tri-stated, and the I/O1 5 pi n is us ed a s an inp ut for the LSB
(A-1) address function.

INPUT

BUFFER

DATA

REGISTER

COMMAND
REGISTER

WRITE STATE

MACHINE

PROGRAM/ERASE
VOLTAGE SWITCH

CE
WE
OE
RESET
BYTE

RDY/BUSY

VCC
GND

PLANE A SECTORS

Device Operation

READ:

When CE
at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high
impedance state whenever CE
control gives designers flexibility in preventing bus conten­tion.

COMMAND SEQUENCES:

ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions tabl e

The AT49F16X4(T) is accessed like an EPROM.

and OE are low and WE is high, the data stored

or OE is high. This dual-line

When the device is first pow-

(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE
tively) and OE
edge of CE
latched by the first rising edge of CE

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE, whichever occurs last. The data is

or WE. Standard
microprocessor write timings are used. The address loca­tions used in the command sequences are not affected by
entering the command sequences.

RESET:

A RESET

tem applications. When RESET

input pin is prov ided to eas e so me s ys-

is at a logic high level, the
device is in its standard operating mod e. A low lev el on th e
RESET

input halts the prese nt device operat ion and puts

3

the outputs of the de vice in a hi gh imped ance stat e. When
a high level is reasse rted on the RES ET

pin, the device
returns to the Read or Standby mod e, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET

pin any sector can be reprogrammed
even if the sector lockout feature has been enabled (see
Sector Programming Lockout Override section).

ERASURE:

Before a byte/word can be reprogrammed, it
must be erased. The erased state of memory bits is a logi­cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.

CHIP ERASE:

The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is t

EC

.

If the sector lockout has been enabled, the Chip Erase will
not erase the data in the secto r th at ha s be en l oc ked; it wi ll
erase only the unprotected sectors. After the chip erase,
the device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the
device is organized into forty sectors (SA0 - SA39) that can
be individually erased . The Secto r Erase comm and is a six
bus cycle operation. The sector ad dress is latc hed on the
falling WE
command is latched on the rising edge of WE
erase starts after the rising edge of WE

edge of the sixth cy cle whil e the 30H d ata inpu t

. The sector

of the sixth cycle.
The erase operation is i nternally controlled; it will aut omati­cally time to completion. The maximum time to erase a sec­tion is t

. When the sector programming lockout feature

SEC

is not enabled, the sector will erase (from the same sector
erase command). Once a sector has been protected, data
in the protected s ectors cannot be changed unles s the
RESET

pin is taken to 12V ± 0.5V. An atte mpt to erase a
sector that has bee n protected wi ll result in the operatio n
terminating in 2 µs.

BYTE/WORD PROGRAMMING:

Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or on a word-by- word basis. Programming i s ac co mpl ished
via the intern al device command register and is a 4 -bus
cycle operation. The dev ice will autom atically ge nerate the
required internal program pulses.

Any commands written to the c hip during the em bedded
programming cycle will be ignored. If a hardware reset hap­pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified t

cycle time. The DATA polling feature or the

BP

toggle bit feature may be used to indicate the end of a pro­gram cycle.

SECTOR PROGRAMMING LOCKOUT:

Each sector has a
programming lockout feature. This feature prevents pro­gramming of data in the des ignated sector s once the fea­ture has been enabled. These sectors can contain secure
code that is used to bring up the system. Enabling the lock­out feature will all ow the boot c ode to stay i n the device
while data in the rest of the device is upd ated. Thi s feat ure
does not have to be activated; any sector’s usage as a
write protected region is optional to the user.

Once the feature is enabled, the data in the protected sec­tors can no longer be erased or programmed when input
levels of 5.5V or less are used. Data in the remaining sec­tors can still be changed through the regular programming
method. To activate the lo ck ou t fea tur e, a ser ies of s ix pr o­gram commands to specific addresses with specific data
must be performed. P lease refer to the Co mmand Defin i­tions table.

SECTOR PROGRAMMING LOCKOUT OVERRIDE:

The
user can override the sector programming lockout by taking
the RESET

pin to 12V ± 0.5V. By doing this prote cted da ta
can be altered through a chip erase, sector era se or
byte/word program ming. When the RESET

pin is brought
back to TTL level s the secto r programm ing loc kout featu re
is again active.

ERASE SUSPEND/ERASE RESUME:

The erase suspen d
command allows the system to interrupt a sector erase
operation and then program or read data from a different
sector within the same plane. Since this device has a dual
plane architecture, there is no need to use the erase sus­pend feature while erasin g a sec tor when y ou want to r ead
data from a sector in the other plane. After the erase sus­pend command is given, the device requires a maximum
time of 15 µs to suspend the erase operation. After the
erase operation has been suspended, the plane which con­tains the suspended s ector enter s the erase-s uspend-r ead
mode. The system can then read data or program da ta to
any other sector within the device. An address is not
required during the erase suspend comm and. During a
sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write
the erase resume command. The erase resume command
is a one bus cy cle co mma nd, whi c h d oes req ui re the p lan e
address (determined by A18 and A19). The device also
supports an erase suspend during a complete chip erase.
While the chip erase is sus pended, the use r can read from
any sector within the me mory that is protec ted. The com­mand sequence for a chip erase suspen d and a sector
erase suspend are the same.

PRODUCT IDENTIFICATION:

The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for
the Atmel product.

4

AT49F16X4(T)

AT49F16X4(T)

For details, see O peratin g Modes (for har dware operatio n)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING:

The AT49F16X4(T) features DATA

poll­ing to indicate the end of a program cycle. During a pro­gram cycle an attempted read of the last byte/word loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and th e next cyc le may be gin. Du ring a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.

polling may begin at any time during the program

DATA
cycle. Please see “Status Bit Table” for more details.

TOGGLE BIT:

In addition to DATA

polling the
AT49F16X4(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.

An additional to ggle bit is available on I/O2 whi ch can be
used in conjunction with the toggle bit which is available on
I/O6. While a sector is erase suspe nded, a read or a pro-

gram operation fr om t he suspended sector wi ll re su lt in th e
I/O2 bit toggling. Please s ee “Status Bit Table” for more
details.

RDY/BUSY

:

An open drain READY/BUSY

output pin pro­vides another method of detectin g the end of a progr am or
erase operation. RDY/BUSY

is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR-tying of several devices to the same
RDY/BUSY

HARDWARE DATA PROTECTION:

line.

Hardware features
protect against in adverten t pro grams to the A T49F16X4 (T)
in the following ways: (a) V
(typical), the program function is inhibited. (b) V
delay: once V

has reached the VCC sense level, the

CC

sense: if VCC is below 3.8V

CC

power on

CC

device will au tomaticall y time out 10 ms (typical) be fore
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inh ibits pr ogram cycle s. (d) No ise
filter: pulses of les s than 15 ns (typ ical) on the W E

or CE

inputs will not initiate a program cycle.

INPUT LEVELS:

While operating with a 4.5V to 5.5V

power supply, th e address inpu ts and cont rol inputs (OE

, and WE) may be dr iven from 0 to 5.5V without

CE
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V

+ 0.6V.

CC

,

5

Command Definition in (Hex)

(1)

1st Bus

Command
Sequence

Bus

Cycles

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr D

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA
Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D

IN

(3)(4)

Bypass Unlock 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0
Single Pulse

Byte/Word Program
Sector Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

1 Addr D

IN

(3)(4)

Erase Suspend 1 xxxx B0
Erase Resume 1 PA

(5)

30
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit

(2)

(2)

3 5555 AA 2AAA 55 5555 F0
1 xxxx F0

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A19 (Don’t Care).

2. Either one of the Product ID Exit commands can be used.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next four
pages for details).

4. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command).
Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET

pin is taken to

12V ± 0.5V.

5. PA is the plane address (A19 - A18).

30

40

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

6

AT49F16X4(T)

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the device at these o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

Memory Plane A - Bottom Boot

AT49F16X4(T)

x8

Sector Size (Bytes/Words)

SA0 8K/4K 000000 - 001FFF 00000 - 00FFF
SA1 8K/4K 002000 - 003FFF 01000 - 01FFF
SA2 8K/4K 004000 - 005FFF 02000 - 02FFF
SA3 8K/4K 006000 - 007FFF 03000 - 03FFF
SA4 8K/4K 008000 - 009FFF 04000 - 04FFF
SA5 8K/4K 00A000 - 00BFFF 05000 - 05FFF
SA6 8K/4K 00C000 - 00DFFF 06000 - 06FFF
SA7 8K/4K 00E000 - 00FFFF 07000 - 07FFF
SA8 32K/16K 010000 - 017FFF 08000 - 0BFFF
SA9 32K/16K 018000 - 01FFFF 0C000 - 0FFFF
SA10 64K/32K 020000 - 02FFFF 10000 - 17FFF
SA11 64K/32K 030000 - 03FFFF 18000 - 1FFFF
SA12 64K/32K 040000 - 04FFFF 20000 - 27FFF
SA13 64K/32K 050000 - 05FFFF 28000 - 2FFFF
SA14 64K/32K 060000 - 06FFFF 30000 - 37FFF
SA15 64K/32K 070000 - 07FFFF 38000 - 3FFFF

Address Range (A19 - A-1)

Address Range (A19 - A0)

x16

7

Memory Plane B - Bottom Boot

x8

Sector Size (Bytes/Words)

SA16 64K/32K 080000 - 08FFFF 40000 - 47FFF
SA17 64K/32K 090000 - 09FFFF 48000 - 4FFFF
SA18 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF
SA19 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF
SA20 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF
SA21 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF
SA22 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF
SA23 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF
SA24 64K/32K 100000 - 10FFFF 80000 - 87FFF
SA25 64K/32K 110000 - 11FFFF 88000 - 8FFFF
SA26 64K/32K 120000 - 12FFFF 90000 - 97FFF
SA27 64K/32K 130000 - 13FFFF 98000 - 9FFFF
SA28 64K/32K 140000 - 14FFFF A0000 - A7FFF
SA29 64K/32K 150000 - 15FFFF A8000 - AFFFF
SA30 64K/32K 160000 - 16FFFF B0000 - B7FFF
SA31 64K/32K 170000 - 17FFFF B8000 - BFFFF
SA32 64K/32K 180000 - 18FFFF C0000 - C7FFF

Address Range (A19 - A-1)

Address Range (A19 - A0)

x16

SA33 64K/32K 190000 - 19FFFF C8000 - CFFFF
SA34 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF
SA35 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF
SA36 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF
SA37 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF
SA38 64K/32K 1E0000 - 1EFFFF F0000 - F7FFF
SA39 64K/32K 1F0000 - 1FFFFF F8000 - FFFFF

8

AT49F16X4(T)

Memory Plane B - Top Boot

AT49F16X4(T)

x8

Sector Size (Bytes/Words)

SA0 64K/32K 000000 - 00FFFF 00000 - 07FFF
SA1 64K/32K 010000 - 01FFFF 08000 - 0FFFF
SA2 64K/32K 020000 - 02FFFF 10000 - 17FFF
SA3 64K/32K 030000 - 03FFFF 18000 - 1FFFF
SA4 64K/32K 040000 - 04FFFF 20000 - 27FFF
SA5 64K/32K 050000 - 05FFFF 28000 - 2FFFF
SA6 64K/32K 060000 - 06FFFF 30000 - 37FFF
SA7 64K/32K 070000 - 07FFFF 38000 - 3FFFF
SA8 64K/32K 080000 - 08FFFF 40000 - 47FFF
SA9 64K/32K 090000 - 09FFFF 48000 - 4FFFF
SA10 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF
SA11 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF
SA12 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF
SA13 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF
SA14 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF
SA15 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF
SA16 64K/32K 100000 - 10FFFF 80000 - 87FFF

Address Range (A19 - A-1)

Address Range (A19 - A0)

x16

SA17 64K/32K 110000 - 11FFFF 88000 - 8FFFF
SA18 64K/32K 120000 - 12FFFF 90000 - 97FFF
SA19 64K/32K 130000 - 13FFFF 98000 - 9FFFF
SA20 64K/32K 140000 - 14FFFF A0000 - A7FFF
SA21 64K/32K 150000 - 15FFFF A8000 - AFFFF
SA22 64K/32K 160000 - 16FFFF B0000 - B7FFF
SA23 64K/32K 170000 - 17FFFF B8000 - BFFFF

9

Memory Plane A - Top Boot

x8

Sector Size (Bytes/Words)

SA24 64K/32K 180000 - 18FFFF C0000 - C7FFF
SA25 64K/32K 190000 - 19FFFF C8000 - CFFFF
SA26 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF
SA27 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF
SA28 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF
SA29 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF
SA30 32K/16K 1E0000 - 1E7FFF F0000 - F3FFF
SA31 32K/16K 1E8000 - 1EFFFF F4000 - F7FFF
SA32 8K/4K 1F0000 - 1F1FFF F8000 - F8FFF
SA33 8K/4K 1F2000 - 1F3FFF F9000 - F9FFF
SA34 8K/4K 1F4000 - 1F5FFF FA000 - FAFFF
SA35 8K/4K 1F6000 - 1F7FFF FB000 - FBFFF
SA36 8K/4K 1F8000 - 1F9FFF FC000 - FCFFF
SA37 8K/4K 1FA000 - 1FBFFF FD000 - FDFFF
SA38 8K/4K 1FC000 - 1FDFFF FE000 - FEFFF
SA39 8K/4K 1FE000 - 1FFFFF FF000 - FFFFF

Address Range (A19 - A-1)

Address Range (A19 - A0)

x16

10

AT49F16X4(T)

AT49F16X4(T)

DC and AC Operating Range

AT49F16X4(T)-70 AT49F16X4(T)-90

Operating
Temperature (Case)

V

Power Supply 4.5V to 5.5V 4.5V to 5.5V

CC

Operating Modes

Mode CE OE WE RESET Ai I/O

Read V
Program/Erase

(2)

Standby/Program Inhibit V

IL

V

IL

IH

Program Inhibit X X V
Program Inhibit X V
Output Disable X V
Reset X X X V
Product Identification

Hardware V

Software

(5)

IL

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

= 12.0V ± 0.5V.

3. V

H

4. Manufacturer Code: 1FH (x8); 161F (x16), Device Code: C0H (x8)-AT49F16X4; 16CO (x16)-AT49F16X4;
C2H (x8)-AT49F16X4T; 16C2 (x16)-AT49F16X4T.

5. See details under Software Product Identification Entry/Exit.

V

IL

V

IH
(1)

X

IL

IH

V

IL

Com. 0°C - 70°C0
Ind. -40°C - 85°C-40

V

IH

V

IL

XV

IH

XV
XV

V

IH

V

IH

V

IH

IH

V

IH

IH

IH

IL

A1 - A19 = VIL, A9 = V

V

IH

A1 - A19 = VIL, A9 = V

A0 = VIL, A1 - A19 = V

V

IH

A0 = VIH, A1 - A19 = V

Ai D
Ai D

X High Z

X High Z

(3)

A0 = V

A0 = V

H

IL

(3)

H

IH

IL

IL

OUT

IN

High Z

Manufacturer Code

Device Code

Manufacturer Code
Device Code

°

C - 70°C

°

C - 85°C

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

(1)

I

CC

I

CCRW

V

IL

V

IH

V

OL

V

OH

Input Load Current VIN = 0V to V
Output Leakage Current V
VCC Standby Current CMOS CE = VCC - 0.3V to V
VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

VCC Read While Write Current f = 5 MHz; I
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA2.4V

Note: 1. In the e rase mode, I

is 50 mA.

CC

= 0V to V

I/O

CC

CC

CC

CC

= 0 mA 40 mA

OUT

= 0 mA 60 mA

OUT

10
10
10

1mA

µ

A

µ

A

µ

A

11

AC Read Characteristics

Symbol Parameter

t
t
t
t
t
t

ACC

CE

OE

DF

OH

RO

(1)

(2)

(3)(4)

Address to Output Delay 70 90 ns
CE to Output Delay 70 90 ns
OE to Output Delay 0 35 0 40 ns
CE or OE to Output Float 0 25 0 25 ns
Output Hold from OE, CE or Address, whichever occurred first 0 0 ns
RESET to Output Delay 800 800 ns

AT49F16X4(T)-70 AT49F16X4(T)-90

UnitsMin Max Min Max

AC Read Waveforms

Notes: 1. CE may be delayed up to t

(1)(2)(3)(4)

ADDRESS

CE

OE

RESET

OUTPUT

ACC

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impac t on tCE or by t

without impact on t

ACC

.

3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and
Measurement Level

ADDRESS VALID

tCE

tOE

tDF

tOH

VALID

HIGH Z

tACC

tRO

OUTPUT

- tCE after the address transition without impact on t

Output Test Load

ACC

.

- tOE after an address c han ge

ACC

3.0

tR, tF < 5 ns

Pin Capacitance

f = 1 MHz, T = 25°C

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

12

(1)

Typ Max Units Conditions

46 pFV
812 pFV

AT49F16X4(T)

IN

OUT

= 0V

= 0V

AT49F16X4(T)

AC Byte/Word Load Characteristics

Symbol Parameter Min Max Units

tAS, t

OES

t

AH

t

CS

t

CH

t

WP

t

DS

tDH, t

OEH

t

WPH

AC Byte/Word Load Waveforms

WE Controlled

Address, OE Set-up Time 10 ns
Address Hold Time 50 ns
Chip Select Set-up Time 0 ns
Chip Select Hold Time 0 ns
Write Pulse Width (WE or CE)100ns
Data Set-up Time 50 ns
Data, OE Hold Time 10 ns
Write Pulse Width High 50 ns

CE Controlled

13

Program Cyc le Characteristics

Symbol Parameter Min Typ Max Units

t

BP

t

AS

t

AH

t

DS

t

DH

t

WP

t

WPH

t

EC

t

SEC

Byte/Word Program ming Time 10 50 µs
Address Set-up Time 0 ns
Address Hold Time 50 ns
Data Set-up Time 50 ns
Data Hold Time 0 ns
Write Pulse Width 100 ns
Write Pulse Width High 50 ns
Chip Erase Cycle Time 10 seconds
Sector Erase Cycle Time 200 ms

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

WP

WE

A0 -A19

DATA

t

AS

t

AH

5555 5555

AA

t

DH

2AAA

t

DS

55

Sector or Chip Erase Cycle Waveforms

(1)

OE

CE

WE

A0-A19

DATA

t

WP

t

AS

5555

WORD 0

t

AH

AA

t

DH

2AAA 2AAA

t

DS

55 55

WORD 1 WORD 2

t

5555

WPH

t

WPH

ADDRESS

5555

WORD 3

INPUT

DATA

AA

WORD 4

A0

80

t

BP

Note 2

Note 3

WORD 5

t

5555

AA

EC

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 5555. For sector era s e, the address depends on what sector is to be erased. (See

note 3 under command definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

14

AT49F16X4(T)

AT49F16X4(T)

Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay

(2)

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in AC Read Characteristics.

Data Polling Wavefo rms

ns

Toggle Bit Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay

(2)

OE High Pulse 150 ns
Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms

(1)(2)(3)

ns

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The t

specification must be met by the toggling input(s).

OEHP

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

15

Status Bit Table

Status Bit

I/O 7 I/O 6 I/O 2

Read Address In Plane A Plane B Plane A Plane B Plane A Plane B
While

Programming in Plane A I/O7
Programming in Plane B DATA I/O7

Erasing in Plane A 0 DATA TOGGLE DATA TOGGLE DATA
Erasing in Plane B DATA 0 DATA TOGGLE DATA TOGGLE

Erase Suspended & Read
Erasing Sector

Erase Suspended & Read
Non-Erasing Sector

Erase Suspended &
Program Erasing Sector

Erase Suspended &
Program Non-Erasing
Sector in Plane A

Erase Suspended &
Program Non-Erasing
Sector in Plane B

1 1 1 1 TOGGLE TOGGLE

DA TA DATA DATA DATA DA TA DATA

1 1 1 1 TOGGLE TOGGLE

I/O7

DATA I/O7

DATA TOGGLE DATA 1 DATA

DATA TOGGLE DATA 1

DATA TOGGLE D ATA TOGGLE DATA

DATA TOGGLE DATA TOGGLE

16

AT49F16X4(T)

Ordering Information

AT49F16X4(T)

t

ACC

(ns)

70 40 0.01 AT49F1604-70TC

90 40 0.01 AT49F1604-90TC

70 40 0.01 AT49F1604T-70TC

ICC (mA)

Ordering Code Package Operation RangeActive Standby

AT49F1604-70UC
AT49F1614-70CC

AT49F1614-70TC

40 0.01 AT49F1604-70TI

AT49F1604-70UI
AT49F1614-70CI

AT49F1614-70TI

AT49F1604-90UC
AT49F1614-90CC

AT49F1614-90TC

40 0.01 AT49F1604-90TI

AT49F1604-90UI
AT49F1614-90CI

AT49F1614-90TI

AT49F1604T-70UC

48T
48U

48C2
48T

48T
48U

48C2
48T

48T
48U

48C2
48T

48T
48U

48C2
48T

48T
48U

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

AT49F1614T-70CC
AT49F1614T-70TC

40 0.01 AT49F1604T-70TI

AT49F1604T-70UI
AT49F1614T-70CI

AT49F1614T-70TI

90 40 0.01 AT49F1604T-90TC

AT49F1604T-90UC
AT49F1614T-90CC

AT49F1614T-90TC

40 0.01 AT49F1604T-90TI

AT49F1604T-90UI
AT49F1614T-90CI

AT49F1614T-90TI

Package Type

48C2 48-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
48T 48-Lead, Thin Small Outline Package (TSOP)

48C2
48T

48T
48U

48C2
48T

48T
48U

48C2
48T

48T
48U

48C2
48T

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

48U 48-Ball, Micro Ball Grid Array Package (µBGA)

17

Packaging Information

48C2, 48-Ball, Plastic Chip-size Ball Grid Array

Package (CBGA)

8.2

7.8

4.0

5.6

0.40 DIA TYP

1.2 MAX

A

B

C

0.85

0.75

D

E

F

G

H

TYP

11.2

10.8

NON-ACCUMULATIVE

6 54321

48T, 48-Lead, Plastic Thin Small Outline Package
(TSOP) Dimensions in Millimeters and (Inches)*

JEDEC OUTLINE MO-142 DD

0.35

*Controlling dimension: millimeters

48-Ball, Micro Ball Grid Array Package (µBGA)

48U,

1

2

3

4

8.4

8.0

5

6

7

8

NON-ACCUMULATIVE

0.75 TYP

6.8

6.4

FEDCBA

3.75

0.30 DIA TYP

5.25

1.00

0.85

0.15 MIN.

0.70

18

AT49F16X4(T)