Datasheet AT49F040 Datasheet (ATMEL)

Page 1
4 Megabit (512K x 8) 5-volt Only CMOS Flash Memory
Preliminary
AT49F040
0359C
查询AT49F040-12JI供应商查询AT49F040-12JI供应商
Single Voltage Ope rati on
- 5V Read
- 5V Reprogramming
Fast Read Access Ti me - 90 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Tim e - 10 se co nds
Byte By Byte Programming - 50 µs/Byte
Hardware Data Protection
DATA Polling For End Of Program De tec tio n
Low Power Dissipation
- 50 mA Active Current
- 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvola­tile CMOS technology, the device offers access times to 90 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is dese­lected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F040 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F040 is performed by erasing the entire 4 megabits of memory and then programming on a byte by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the detected, a new access for a read or program can begin. The typical number of pro­gram and erase cycles is in excess of 10,000 cycles.
DATA polling feature. Once the end of a byte program cycle has been
(continued)
DIP Top View
Pin Configurations
AT49F040
Pin Name Function
A0 - A18 Addresses CE Chip Enable OE Output E nable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs
PLCC Top View
TSOP Top View
Type 1
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Description (Continued)
The optional 16K bytes boot block section includes a re­programming write lock out feature to provide data integ­rity. The boot sector is designed to contain user secure
Block Diagram
Device Operation
READ: The AT49F040 is accessed like an EPROM.
CE and OE are low and WE is high, the data stored
When at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever line control giv es designers flexibility in preventing bus contention.
ERASURE: Before a byte can be reprogrammed, the 512K bytes memory array (or 496K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1". The entire device can be erased at one time by using a 6-byte software code. The software chip eras e code consists of 6-byte load com­mands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the devic e will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is t been enable d, the data in the boot sector will not be erased.
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0") on a byte-by-byte basis. Please note that a data ”0" cannot be programmed back to a “1"; only erase operations can con­vert ”0"s to “1"s. Programming is accomplished via the in­ternal device command register and is a 4 bus cycle op­eration (please refer to the Command Definitions table). The device will automatically generate the required inter­nal program pulses.
The program cycle has addresses latched on the falling edge of latched on the rising edge of first. Programming is completed after the specified t
WE or CE, whichever occurs last, and the data
. If the boot block lockout feature has
EC
CE or OE is high. This dual-
WE or CE, whichever occurs
cy-
BP
code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
cle time. The DATA polling feature may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The de­vice has one designated block that has a programming lockout fea ture. This feature p revents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout fea­ture will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address r ange of the boot block is 00000H to 03FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series o f six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Prod­uct Identification Entry and Exit sections) a read from ad­dress location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identifica­tion code should be used to return to standard operation.
(continued)
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Device Operation (Continued)
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49F040 features
DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin.
DATA polling
may begin at any time during the program cycle.
Command Definition (in He x)
AT49F040
TOGGLE BIT: In addition to
provides another method for determining the end of a pro­gram or erase cycle. During a program or erase operation, successive attempts to read data from the device will re­sult in I/O6 toggling between one and zero. Once the pro­gram cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F040 in the following ways: (a) V (typical), the program function is inhibited. (b) Program in­hibit: holding any one of hibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the program cycle.
DATA polling the AT49F040
sense: if VCC is below 3.8V
CC
OE low, CE high or WE high in-
WE or CE inputs will not initiate a
Command Sequence
Read Chip Erase Byte
Program Boot Block
Lockout Product ID
Entry Product ID
(2)
Exit Product ID
(2)
Exit
Note: 1. The 16K byte boot sector ha s the address range 00000H to 03FFFH .
2. Either one of the Product ID exit commands can be used.
(1)
Bus
Cycles
1AddrD 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
4 5555 AA 2AAA 55 5555 A0 Addr D
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
3 5555 AA 2AAA 55 5555 90
3 5555 AA 2AAA 55 5555 F0
1 XXXX F0
1st Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
OUT
2nd Bus
Cycle
3rd Bus
Cycle
Absolute Maximum Rat ings*
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
4th Bus
Cycle
5th Bus
Cycle
IN
6th Bus
Cycle
All Input Voltages (including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
+ 0.6V
CC
Voltage on OE
with Respect to Ground .................. -0.6V to + 13.5V
*NOTICE: Stresses beyond those listed unde r “Absolu te Maxi-
mum Ratings” may cause permanent da ma ge to th e de vice . This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi­cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC and AC Operating Range
AT49F040-90 AT49F040-12 AT49F040-15
Operating Temperature (Case)
V
Power Supply 5V ± 10% 5V ± 10% 5V ± 10%
CC
Com. 0°C - 70°C0°C - 70°C0°C - 70°C Ind. -40°C - 85°C-40°C - 85°C -40°C - 85°C
Operating Modes
Mode CE OE WE Ai I/O
Read V Program
(2)
Standby/Write Inhibit V
IL
V
IL
IH
Program Inhibit X X V Program Inhibit X V Output Disable X V Product Identification
Hardware V
Software
(5)
IL
X
V
IL
V
IH (1)
IL
IH
V
IL
V
IH
V
IL
Ai D Ai D
OUT IN
X X High Z
IH
X X High Z
A1 - A18 = VIL, A9 = VH,
V
IH
A1 - A18 = VIL, A9 = VH,
A0 = VIL, A1 - A18 = V A0 = VIH, A1 - A18 = V
A0 = V A0 = V
IL
IH
(3)
Manufacturer Code
(3)
Device Code
IL IL
Manufacturer Code Device Code
(4)
(4)
(4)
(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 13H
5. See details unde r Soft ware Product Identific at io n Ent ry/Exit.
DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
I
LO
I
SB1
I
SB2
(1)
I
CC
V
IL
V
IH
V
OL
V
OH1
V
OH2
Input Load Current VIN = 0V to V Output Leakage Current V
VCC Standby Current CMOS CE = V
= 0V to V
I/O
CC
- 0.3V to V
VCC Standby Current TTL CE = 2.0V to V V
Active Current f = 5 MHz; I
CC
OUT
CC
CC
CC
CC
Com. 100 µA Ind. 300 µA
= 0 mA 50 mA
10 µA 10 µA
3mA
Input Low Voltage 0.8 V Input High Voltage 2.0 V Output Low Voltage IOL = 2.1 mA .45 V Output High Voltage IOH = -400 µA 2.4 V Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
Note: 1. In the erase mode, ICC is 90 mA.
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AC Read Characteristics
Symbol Parameter
t
ACC
t
CE
t
OE
t
DF
t
OH
(1) (2) (3, 4)
Address to Output Delay 90 120 150 ns CE to Output Delay 90 120 150 ns OE to Output Delay 0 40 0 50 0 70 ns CE or OE to Output Float 0 25 0 30 0 40 ns Output Hold from OE, CE or
Address, whichever occurred first
AT49F040
AT49F040-90 AT49F040-12 AT49F040-15
Min Max Min Max Min Max
00 0 ns
Units
AC Read Waveforms
Notes: 1. CE may be delayed up to t
transition without impact on t OE may be delayed up to tCE - tOE after the falling
2. edge of after an address change without impact on t
CE without impact on tCE or by t
(1, 2, 3, 4)
- tCE after the address
ACC
.
ACC
ACC
- tOE
ACC
3. tDF is specified from OE or CE whi chever occu r s first = 5 pF).
(C
L
4. This parameter is characterized and is not 100% tested.
.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ Max Units Conditions
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
46pFV 812pFV
= 0V
IN
= 0V
OUT
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AC Byte Load Characteristics
Symbol Parameter Min Max Units
t
AS
t
AH
t
CS
t
CH
t
WP
t
DS
t
DH
t
WPH
, t
, t
OES
OEH
Address, OE Set-up Time 0 ns Address Hold Time 50 ns Chip Select Set-up Time 0 ns Chip Select Hold Time 0 ns Write Pulse Width (WE or CE) 90 ns Data Set-up Time 50 ns Data, OE Hold Time 0 ns Write Pulse Width High 90 ns
AC Byte Load Waveform s
WE Controlled
CE Controlled
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AT49F040
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
t
AS
t
AH
t
DS
t
DH
t
WP
t
WPH
t
EC
Byte Programming Time 10 50 µs Address Set-up Time 0 ns Address Hold Time 50 ns Data Set-up Time 50 ns Data Hold Time 0 ns Write Pulse Width 90 ns Write Pulse Width High 90 ns Erase Cycle Time 10 seconds
Program Cycle Wave forms
Chip Erase Cycle Waveforms
Note: OE must be high only when WE and CE are both low.
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Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Notes: 1. These parameters are ch ara ct erized and not 100% teste d.
2. See t
Data Hold Time 10 ns OE Hold Time 10 ns OE to Output Delay
(2)
Write Recovery Time 0 ns
spec in AC Read Characteristics.
OE
Data Polling Wavefor ms
Toggle Bit Character i s ti cs
(1)
ns
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
OEHP
t
WR
Notes: 1. These parameters are ch ara ct erized and not 100% teste d.
2. See t
Toggle Bit Waveform s
Notes: 1. Toggling either
operate toggle bit. The t met by the toggli ng inp ut(s).
Data Hold Time 10 ns OE Hold Time 10 ns OE to Output Delay
(2)
OE High Pulse 150 ns Write Recovery Time 0 ns
spec in AC Read Characteristics.
OE
(1, 2, 3)
OE or CE or both OE and CE will
specification must be
OEHP
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should no t vary.
ns
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AT49F040
Software Product Identification Entry
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
Software Product
MODE
(2, 3, 5)
(1)
Identification Exit
LOAD DATA AA
TO
ADDRESS 5555
(1)
OR
LOAD DATA F0
TO
ANY ADDRESS
Boot Block Lockout Feature Enable Al gor ithm
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
PAUSE 1 second
(2)
(1)
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
EXIT PRODUCT
IDENTIFICATION
MODE
Notes for software prod uc t id en tification:
1. Data Format: I/O7 - I/O0 (Hex ); Address Format: A14 - A0 (Hex).
2. A1 - A18 = V Manufacture Code is read for A0 = V Device Code is read for A0 = V
.
IL
;
IL
.
IH
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH Device Code: 13H
(4)
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex ); Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
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Page 10
Ordering Information
(1)
t
ACC
(ns)
I
(mA)
CC
Active Standby
Ordering Code Package Operation Range
90 50 0.1 AT49F040-90JC 32J Commercial
AT49F040-90PC 32P6 (0° to 70°C) AT49F040-90TC 32T
50 0.3 AT49F040-90JI 32J Industrial
AT49F040-90PI 32P6 (-40° to 85°C) AT49F040-90TI 32T
120 50 0.1 AT49F040-12JC 32J Commercial
AT49F040-12PC 32P6 (0° to 70°C) AT49F040-12TC 32T
50 0.3 AT49F040-12JI 32J Industrial
AT49F040-12PI 32P6 (-40° to 85°C) AT49F040-12TI 32T
150 50 0.1 AT49F040-15JC 32J Commercial
AT49F040-15PC 32P6 (0° to 70°C) AT49F040-15TC 32T
50 0.3 AT49F040-15JI 32J Industrial
AT49F040-15PI 32P6 (-40° to 85°C) AT49F040-15TI 32T
Note: 1. The AT49F040 has as optional boot blo ck f ea tu re. The part number shown in the Orderi ng I nf ormat io n table is for devices
with the boot bloc k in the lower address range (i.e., 000 00H to 03FFFH). Users requ iri ng t he boo t bl ock to be in the higher address ran ge sho ul d contact Atmel.
Package Type
32J 32 Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32P6 32 Lead, 0.600" Wide, Plastic Dual Inl in e Packa ge (PDIP) 32T 32 Lead, Thin Small Outline Package (TSOP)
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