Datasheet AT49LV1614AT-70TI, AT49LV1614AT-70CI, AT49LV1614A-70TI, AT49LV1614A-70CI, AT49BV1614AT-90TI Datasheet (ATMEL)

Features

• Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)

• AccessTime–70ns

• Sector Erase Architecture

– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

• Fast Word Program Time – 20 µs

• Fast Sector Erase Time – 300 ms

• Dual-plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Eight 4K Word and Seven 32K Word Sectors
Memory Plane B: Twenty-four 32K Word Sectors

• Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

• Low-power Operation

–30mAActive
– 10 µA Standby

• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

• VPP Pin for Accelerated Program/Erase Operations

• RESET Input for Device Initialization

• Sector Lockdown Support

• TSOP and CBGA Package Options

• Top or Bottom Boot Block Configuration Available

• 128-bit Protection Register

16-megabit
(1Mx16/2Mx8)
3-volt Only
Flash Memory

AT49BV1604A
AT49BV1604AT

Description

The AT49BV/LV16X4A(T) is a 2.65- to 3.3-volt 16-megabit Flash memory organized
as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 39 sectors for erase operations. The device is offered in 48-lead TSOP and
48-ball CBGA packages. The device has CE
contention. This device can be read or reprogrammed using a single 2.65V power
supply, making it ideally suited for in-system programming.

and OE control signals to avoid any bus

Pin Configurations

Pin Name Function

A0 - A19 Addresses

CE

OE

WE

RESET

RDY/BUSY

VPP Power Supply for Accelerated Program/Erase Operations

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1) I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

BYTE

NC No Connect

VCCQ Output Power Supply

Chip Enable

Output Enable

Write Enable

Reset

READY/BUSY Output

Selects Byte or Word Mode

AT49BV1614A
AT49LV1614A
AT49BV1614AT
AT49LV1614AT

Rev. 1411F–FLASH–03/02

1

A15
A14
A13
A12
A11
A10

WE

RESET

VPP

A19
A18
A17

TSOP Top View

CBGA Top View (Ball Down)

1
2
3
4
5
6
7

A9

8

A8

9

NC

10

NC

11
12
13
14

NC

15
16
17
18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

A16

48

VCCQ

47

GND

46

I/O15

45

I/O7

44

I/O14

43

I/O6

42

I/O13

41

I/O5

40

I/O12

39

I/O4

38

VCC

37

I/O11

36

I/O3

35

I/O10

34

I/O2

33

I/O9

32

I/O1

31

I/O8

30

I/O0

29

OE

28

GND

27

CE

26

A0

25

AT49BV1604A(T)

A

B

C

D

E

F

234567

1

A8

A11

A13

A14

A15

A16

VCCQ

GND

A10

A12

I/O14

I/O15

I/O7

WE

A9

I/O5

I/O6

I/O13

VPP

RST

I/O11

I/O12

I/O4

A18

I/O2

I/O3

VCC

A19

A17

A6

I/O8

I/O9

I/O10

I/O0

I/O1

8

A7

A4

A5

A2

A3

A1

CE

A0

GND

OE

A15
A14
A13
A12
A11
A10

A19

WE

RESET

VPP*

NC*

RDY/BUSY

A18
A17

TSOP Top View

Type 1

1
2
3
4
5
6
7

A9

8

A8

9
10

NC

11
12
13
14
15
16
17
18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

48

A16

47

BYTE

46

GND

45

I/O15/A-1

44

I/O7

43

I/O14

42

I/O6

41

I/O13

40

I/O5

39

I/O12

38

I/O4

37

VCC

36

I/O11

35

I/O3

34

I/O10

33

I/O2

32

I/O9

31

I/O1

30

I/O8

29

I/O0

28

OE

27

GND

26

CE

25

A0

AT49BV/LV1614A(T)

A

B

C

D

E

F

G

H

CBGA Top View

2

1

A7

A3

A17

A4

A6

A2

A5

A1

I/O0

A0

I/O8

CE

I/O9

OE

I/O1

VSS

3456

RDY/BUSY

NC*

A18

NC

I/O2

I/O10

I/O11

I/O3

WE

RESET

VPP*

A19

I/O5

I/O12

VCC

I/O4

A9

A8

A10

A11

I/O7

I/O14

I/O13

I/O6

I/O15/A-1

A13

A12

A14

A15

A16

BYTE

VSS

Note: *For the AT49BV/LV1614A(T), either pin 13 or pin 14 (TSOP package) or ball B3 or ball C4 (CBGA package) can be connected

to V

or both pins can be unconnected. Accelerated program/erase operations are only achieved if a voltage of 5V ± 0.5 V or

PP

12V ± 0.5V is applied to pin 13 (TSOP package) or ball C4 (CBGA package).

2

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/0 2

AT49BV1604A(T)/1614A(T)

The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see Sector Lockdown section).

The device is segmented into two memory planes. Reads from memory plane B may be per­formed even while program or erase functions are being executed in memory plane A and vice
versa. This operation allows improved system performance by not requiring the system to wait
for a program or erase operation to complete before a read is performed. To further increase
the flexibility of the device, it contains an Erase Suspend feature. This feature will put the
erase on hold for any amount of time and let the user read data from or program data to any of
the remaining sectors within the same memory plane. There is no reason to suspend the
erase operation if the data to be read is in the other memory plane. The end of a program or
an erase cycle is detected by the Ready/Busy

The VPP pin provides faster program/erase times. With V
erase operations are accelerated.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering
down the device, or by pulsing the RESET
it back to V

. Erase and Erase Suspend/Resume commands will not work while in this mode;

CC

if entered they will result in data being programmed into the device. It is not recommended that
the six-byte code reside in the software of the final product but only exist in external program­ming code.

When using the AT49BV1604A(T) pinout configuration, the device always operates in the
word mode. In the AT49BV/LV1614A(T) configuration, the BYTE
device data I/O pins operate in the byte or word configuration. If the BYTE
“1”, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE

If the BYTE

pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0 - I/O7 are active and controlled by CE
stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.

pin, Data Polling or by the toggle bit.

at 5.0V or 12.0V, the program and

PP

pin low for a minimum of 500 ns and then bringing

pin controls whether the

pin is set at logic

and OE.

and OE. The data I/O pins I/O8 - I/O14 are tri-

1411F–FLASH–03/02

3

Block Diagram

I/O0 - I/O15/A-1

A0 - A19

INPUT

BUFFER

ADDRESS

LATCH

Y-DECODER

X-DECODER

OUTPUT
BUFFER

OUTPUT

IDENTIFIER

REGISTER

MULTIPLEXER

REGISTER

COMPARATOR

PLANE B

SECTORS

STATUS

DATA

Y-GATING

INPUT

BUFFER

DATA

REGISTER

COMMAND
REGISTER

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

CE
WE
OE
RESET
BYTE

RDY/BUSY

VPP

VCC
GND

PLANE A SECTORS

4

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

Device Operation

READ: The AT49BV/LV16X4A(T) is accessed like an EPROM. When CE and OE are low and

WE

is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE

or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE

or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE
CE

or WE. Standard microprocessor write timings are used. The address locations used in the

or WE, whichever occurs last. The data is latched by the first rising edge of

command sequences are not affected by entering the command sequences.

RESET: A RESET
a logic high level, the device is in its standard operating mode. A low level on the RESET

input pin is provided to ease some system applications. When RESET is at

input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET

pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com­mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is t

EC

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.

.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sec­tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE
the 30H data input command is latched on the rising edge of WE
the rising edge of WE

of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a section is t

edge of the sixth cycle while

. The sector erase starts after

. When the sec-

SEC

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the oper­ation terminating in 2 µs.

BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi­cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The device will automati­cally generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”;onlyerase
operations can convert “0”sto“1”s. Programming is completed after the specified t
time. The Data

Polling feature or the Toggle Bit feature may be used to indicate the end of a

BP

cycle

program cycle.

VPP PIN: The circuitry of the AT49BV/LV16X4A(T) is designed so that the device can be pro­grammed or erased from the V
than or equal to the VCC pin, the device selects the V

power supply or from the VPP input pin. When VPPis less

CC

supply for programming and erase

CC

1411F–FLASH–03/02

5

operations. When the VPP pin is greater than the VCCsupply, the device will select the V

PP

input as the power supply for programming and erase operations. The device will allow for
some variations between the V

input and the VCCpower supply in its selection of VCCor V

PP

PP

for program or erase operations. If the VPP pin is within 0.3V of VCCfor 2.65V < VCC<3.3V,
then the program or erase operations will use V
the V

signal is used to accelerate program and erase operations, the VPPmust be in the 5V

PP

± 0.5V or 12V ± 0.5V range to ensure proper operation. The V

and disregard the VPPinput signal. When

CC

pin can be left unconnected.

pp

SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre­vents programming of data in the designated sectors once the feature has been enabled.
These sectors can contain secure code that is used to bring up the system. Enabling the lock­down feature will allow the boot code to stay in the device while data in the rest of the device is
updated. This feature does not have to be activated; any sector’s usage as a write protected
region is optional to the user.

At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION: A software method is available to determine if program­ming of a sector is locked down. When the device is in the software product identification
mode (see Software Product Identification Entry and Exit sections) a read from address loca­tion 00002H within a sector will show if programming the sector is locked down. If the data on
I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown
feature has been enabled and the sector cannot be programmed. The software product identi­fication exit code should be used to return to standard operation.

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is
through reset or power-up cycles. After power-up or reset, the content of a sector that is
locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME: TheEraseSuspendcommandallowsthesystemto
interrupt a sector erase operation and then program or read data from a different sector within
the same plane. Since this device has a dual-plane architecture, there is no need to use the
Erase Suspend feature while erasing a sector when you want to read data from a sector in the
other plane. After the Erase Suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
plane that contains the suspended sector enters the erase-suspend-read mode. The system
can then read data or program data to any other sector within the device. An address is not
required during the Erase Suspend command. During a sector erase suspend, another sector
cannot be erased. To resume the sector erase operation, the system must write the Erase
Resume command. The Erase Resume command is a one-bus cycle command, which does
require the plane address (determined by A18 and A19). The device also supports an erase
suspend during a complete chip erase. While the chip erase is suspended, the user can read
from any sector within the memory that is protected. The command sequence for a chip erase
suspend and a sector erase suspend are the same.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man­ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.

For details, see “Operating Modes” on page 12 (for hardware operation) or “Software Product
Identification Entry/Exit” on page 20. The manufacturer and device codes are the same for
both modes.

6

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

128-BIT PROTECTION REGISTER: The AT49BV/LV16X4A(T) contains a 128-bit register that

can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be repro­grammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the Command Definition table on
page 8. To lock out block B, the four-bus cycle Lock Protection Register command must be
used as shown in the Command Definition table. Data bit D1 must be zero during the fourth
bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Pro­tection Register Addressing Table” on page 9 for the address locations in the protection
register. To read the protection register, the Product ID Entry command is given followed by a
normal read operation from an address within the protection register. After reading the protec­tion register, the Product ID Exit command must be given prior to performing any other
operation.

DATA

POLLING: The AT49BV/LV16X4A(T) features Data Polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte/word loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been completed,
true data is valid on all outputs and the next cycle may begin. During a chip or sector erase
operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device. Data
time during the program cycle. Please see “Status Bit Table” on page 21 for more details.

Polling may begin at any

TOGGLE BIT: In addition to Data

Polling, the AT49BV/LV16X4A(T) provides another method
for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the same memory plane will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling and
valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle
bit that is available on I/O6. While a sector is erase suspended, a read or a program operation
from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on
page 21 for more details.

RDY/BUSY

another method of detecting the end of a program or erase operation. RDY/BUSY

: For the AT49BV/LV1614A(T), an open-drain Ready/Busy output pin provides

is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY

line.

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the AT49BV/LV16X4A(T) in the following ways: (a) V
is below 1.8V (typical), the program function is inhibited. (b) VCCpower-on delay: once V

sense: if V

CC

CC

CC

has reached the VCCsense level, the device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
gram cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE

low, CE high or WE high inhibits pro-

or CE inputs will not

initiate a program cycle.

INPUT LEVELS: While operating with a 2.65V to 3.3V power supply, the address inputs and
control inputs (OE
operation of the device. The I/O lines can only be driven from 0 to V

OUTPUT LEVELS: For the AT49BV1604A(T), output high levels (V

0.2V (not V

CC

put levels, V

,CEand WE) may be driven from 0 to 5.5V without adversely affecting the

+0.6V.

CC

) are equal to V

). For 2.65V - 3.3V output levels, V

must be regulated to 2.0V ± 10%, while VCCmust be regulated to 2.65V - 3.0V

CCQ

must be tied to VCC. For 1.8V - 2.2V out-

CCQ

OH

CCQ

(for minimum power).

-

1411F–FLASH–03/02

7

OUT

30

(1)

2nd Bus

Cycle

(2)

55 555 80 555 AA AAA 55 555 10

IN

3rd Bus

Cycle

4th Bus

Cycle

OUT

5th Bus

Cycle

IN

IN

(7)

6th Bus

Cycle

(3)(4)

(3)(4)

30

60

CommandDefinitioninHex

1st Bus

Command
Sequence

Read 1 Addr D

Chip Erase 6 555 AA AAA

Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA

Byte/Word Program 4 555 AA AAA 55 555 A0 Addr D

Enter Single Pulse
Program Mode

Single Pulse
Byte/Word Program

Sector Lockdown 6 555 AA AAA 55 555 80 555 AA AAA 55 SA

Erase Suspend 1 XXX B0

Erase Resume 1 PA

Product ID Entry 3 555 AA AAA 55 555 90

Product ID Exit

Product ID Exit

Program Protection
Register

Lock Protection
Register - Block B

Status of Block B
Protection

(6)

(6)

Bus

Cycles

6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0

1AddrD

3 555 AA AAA 55 555 F0

1 XXX F0

4 555 AA AAA 55 555 C0 Addr D

4 555 AA AAA 55 555 C0 080 X0

4 555 AA AAA 55 555 90 80 D

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

(5)

Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’tCare.

The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’tCare
in the word mode. Address A19 through A11 and A-1 are Don’t Care in the byte mode.

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 10 and
11 for details).

4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.

5. PA is the plane address (A19-A18).

6. Either one of the Product ID Exit commands can be used.

7. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

Voltage on OE

and V

PP

with Respect to Ground ...................................-0.6V to +13.0V

8

AT49BV1604A(T)/1614A(T)

CC

+0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

Protection Register Addressing Table

Word Use Block A7 A6 A5 A4 A3 A2 A1 A0

0 Factory A 10000001

1 Factory A 10000010

2 Factory A 10000011

3 Factory A 10000100

4 User B 10000101

5 User B 10000110

6 User B 10000111

7 User B 10001000

Note: 1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A19 - A8 = 0.

1411F–FLASH–03/02

9

AT49BV/LV1604A/1614A – Sector Address Table

x8

Plane Sector Size (Bytes/Words)

A SA0 8K/4K 000000 - 001FFF 00000 - 00FFF

A SA1 8K/4K 002000 - 003FFF 01000 - 01FFF

A SA2 8K/4K 004000 - 005FFF 02000 - 02FFF

A SA3 8K/4K 006000 - 007FFF 03000 - 03FFF

A SA4 8K/4K 008000 - 009FFF 04000 - 04FFF

A SA5 8K/4K 00A000 - 00BFFF 05000 - 05FFF

A SA6 8K/4K 00C000 - 00DFFF 06000 - 06FFF

A SA7 8K/4K 00E000 - 00FFFF 07000 - 07FFF

A SA8 64K/32K 010000 - 01FFFF 08000 - 0FFFF

A SA9 64K/32K 020000 - 02FFFF 10000 - 17FFF

A SA10 64K/32K 030000 - 03FFFF 18000 - 1FFFF

A SA11 64K/32K 040000 - 04FFFF 20000 - 27FFF

A SA12 64K/32K 050000 - 05FFFF 28000 - 2FFFF

A SA13 64K/32K 060000 - 06FFFF 30000 - 37FFF

A SA14 64K/32K 070000 - 07FFFF 38000 - 3FFFF

B SA15 64K/32K 080000 - 08FFFF 40000 - 47FFF

B SA16 64K/32K 090000 - 09FFFF 48000 - 4FFFF

B SA17 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF

B SA18 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF

B SA19 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF

B SA20 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF

B SA21 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF

B SA22 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF

B SA23 64K/32K 100000 - 10FFFF 80000 - 87FFF

B SA24 64K/32K 110000 - 11FFFF 88000 - 8FFFF

B SA25 64K/32K 120000 - 12FFFF 90000 - 97FFF

B SA26 64K/32K 130000 - 13FFFF 98000 - 9FFFF

B SA27 64K/32K 140000 - 14FFFF A0000 - A7FFF

B SA28 64K/32K 150000 - 15FFFF A8000 - AFFFF

B SA29 64K/32K 160000 - 16FFFF B0000 - B7FFF

B SA30 64K/32K 170000 - 1EFFFF B8000 - F7FFF

B SA31 64K/32K 180000 - 18FFFF C0000 - C7FFF

B SA32 64K/32K 190000 - 19FFFF C8000 - CFFFF

B SA33 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF

B SA34 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF

B SA35 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF

B SA36 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF

B SA37 64K/32K 1E0000 - 1EFFFF F0000 - F7FFF

B SA38 64K/32K 1F0000 - 1FFFFF F8000 - FFFFF

Address Range (A19 - A-1)

Address Range (A19 - A0)

x16

10

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

AT49BV/LV1604AT/1614AT – Sector Address Table

x8

Plane Sector Size (Bytes/Words)

B SA0 64K/32K 000000 - 00FFFF 00000 - 07FFF

B SA1 64K/32K 010000 - 01FFFF 08000 - 0FFFF

B SA2 64K/32K 020000 - 02FFFF 10000 - 17FFF

B SA3 64K/32K 030000 - 03FFFF 18000 - 1FFFF

B SA4 64K/32K 040000 - 04FFFF 20000 - 27FFF

B SA5 64K/32K 050000 - 05FFFF 28000 - 2FFFF

B SA6 64K/32K 060000 - 06FFFF 30000 - 37FFF

B SA7 64K/32K 070000 - 07FFFF 38000 - 3FFFF

B SA8 64K/32K 080000 - 08FFFF 40000 - 47FFF

B SA9 64K/32K 090000 - 09FFFF 48000 - 4FFFF

B SA10 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF

B SA11 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF

B SA12 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF

B SA13 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF

B SA14 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF

B SA15 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF

B SA16 64K/32K 100000 - 10FFFF 80000 - 87FFF

B SA17 64K/32K 110000 - 11FFFF 88000 - 8FFFF

B SA18 64K/32K 120000 - 12FFFF 90000 - 97FFF

B SA19 64K/32K 130000 - 13FFFF 98000 - 9FFFF

B SA20 64K/32K 140000 - 14FFFF A0000 - A7FFF

B SA21 64K/32K 150000 - 15FFFF A8000 - AFFFF

B SA22 64K/32K 160000 - 16FFFF B0000 - B7FFF

B SA23 64K/32K 170000 - 17FFFF B8000 - BFFFF

A SA24 64K/32K 180000 - 18FFFF C0000 - C7FFF

A SA25 64K/32K 190000 - 19FFFF C8000 - CFFFF

A SA26 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF

A SA27 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF

A SA28 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF

A SA29 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF

A SA30 64K/32K 1E0000 - 1EFFFF F0000 - F7FFF

A SA31 8K/4K 1F0000 - 1F1FFF F8000 - F8FFF

A SA32 8K/4K 1F2000 - 1F3FFF F9000 - F9FFF

A SA33 8K/4K 1F4000 - 1F5FFF FA000 - FAFFF

A SA34 8K/4K 1F6000 - 1F7FFF FB000 - FBFFF

A SA35 8K/4K 1F8000 - 1F9FFF FC000 - FCFFF

A SA36 8K/4K 1FA000 - 1FBFFF FD000 - FDFFF

A SA37 8K/4K 1FC000 - 1FDFFF FE000 - FEFFF

A SA38 8K/4K 1FE000 - 1FFFFF FF000 - FFFFF

Address Range (A19 - A-1)

Address Range (A19 - A0)

x16

1411F–FLASH–03/02

11

DC and AC Operating Range

AT49BV/LV16X4A(T)-70 AT49BV/LV16X4A(T)-90

Operating Temperature (Case) Ind. -40°C-85°C-40°C-85°C

V

Power Supply 2.65V to 3.3V/3.0V to 3.6V 2.65V to 3.3V/3.0V to 3.6V

CC

Operating Modes

Mode CE OE WE RESET V

Read V

Program/Erase

(2)

V

Standby/Program Inhibit V

Program Inhibit

Output Disable X V

Reset X X X V

V

IL

V

IL

X

IH

XXV

XV

V

IL

IH

(1)

IL

IH

IH

V

IL

XVIHXXHigh-Z

IH

XVIHX

XVIHXHigh-Z

V

IH

V

IH

V

IH

IL

Product Identification

Hardware V

Software

(5)

V

IL

V

IL

V

IH

IH

V

IH

Notes: 1. X can be VILor VIH.

2. Refer to AC programming waveforms on page 19.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV/LV16X4A; 00C0H (x16)-AT49BV/LV16X4A;
C2H (x8)-AT49BV/LV16X4AT; 00C2H (x16)-AT49BV/LV16X4T.

5. See details under “Software Product Identification Entry/Exit” on page 20.

6. V

can be left unconnected or 0V ≤ VPP≤ 3.3V. For faster erase/program operations, VPPcan be set to 5.0V ± 0.5V or

PP

12V ± 0.5V.

PP

XAiD

(6)

V

PP

Ai I/O

Ai D

OUT

IN

X

XXHigh-Z

A1 - A19 = VIL,A9=V

A1 - A19 = VIL,A9=V

A0 = VIL,A1-A19=V

A0 = VIH,A1-A19=V

(3)

,A0=V

H

(3)

,A0=V

H

Manufacturer Code

IL

Device Code

IH

IL

IL

Manufacturer Code

Device Code

(4)

(4)

(4)

(4)

12

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

SB3

(1)(2)

I

CC

I

CC1

I

PP1

I

CC2

I

PP2

I

CC3

I

PP3

V

IL

V

IH

V

OL1

V

OL2

V

OH1

V

OH2

Note: 1. In the erase mode, ICCis 50 mA.

Input Load Current VIN=0VtoV

Output Leakage Current V

=0VtoV

I/O

CC

CC

VCCStandby Current CMOS CE =VCC-0.3VtoV

VCCStandby Current TTL CE =2.0VtoV

CC

CC

10 µA

10 µA

10 µA

1mA

VCCStandby Current TTL CE =2.0VtoVCC,VCC= 2.85V 10 µA

VCCActive Read Current f = 5 MHz; I

=0mA,3.3V≤ V

OUT

CC

30 mA

VCCProgramming Current (VPP=VCC) 45 mA

=0V,VCC=3.0V 10 µA

V

VPPInput Load Current

PP

V

PP=VCC

=3.0V 10 µA

VCCProgramming Current (VPP= 5.0V ± 0.5V) 40 mA

VPPProgramming Current (VPP= 5.0V ± 0.5V) 5mA

VCCProgramming Current (VPP= 12.0V ± 0.5V) 40 mA

VPPProgramming Current (VPP= 12.0V ± 0.5V) 6mA

Input Low Voltage 0.6 V

Input High Voltage 2.0 V

Output Low Voltage IOL=2.1mA 0.45 V

Output Low Voltage IOL=1.0mA 0.20 V

V

<2.6V

CCQ

V

≥ 2.6V

CCQ

- 0.2 [AT49BV1604A(T)]

V

CCQ

2.4 [AT49BV1604A(T)]

2.4 [AT49BV/LV1614A(T)]

V

<2.6V

CCQ

V

≥ 2.6V

CCQ

- 0.1 [AT49BV1604A(T)]

V

CCQ

2.5 [AT49BV1604A(T)]

2.5 [AT49BV/LV1614A(T)]

Output High Voltage

Output High Voltage

2. For 3.3V < V

<3.6V,ICC(max) = 35 mA.

CC

=-400µA

I

OH

I

=-400µA

OH

I

=-400µA

OH

=-100µA

I

OH

I

=-100µA

OH

I

=-100µA

OH

V

V

V

V

V

V

1411F–FLASH–03/02

13

AC Read Characteristics

Symbol Parameter

t

t

t

t

t

t

ACC

CE

OE

DF

OH

RO

(1)

(2)

(3)(4)

Address to Output Delay 70 90 ns

CE to Output Delay 70 90 ns

OE to Output Delay 0 35 0 40 ns

CE or OE to Output Float 0 25 0 25 ns

Output Hold from OE,CEor Address, whichever occurred first 0 0 ns

RESET to Output Delay 100 100 ns

AT49BV/LV16X4A(T)-70 AT49BV/LV16X4A(T)-90

UnitsMin Max Min Max

AC Read Waveforms

1. CE may be delayed up to t

2. OE

may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t

without impact on t

3. t

is specified from OE or CE, whichever occurs first (CL = 5 pF).

DF

4. This parameter is characterized and is not 100% tested.

ACC

(1)(2)(3)(4)

ADDRESS

CE

OE

RESET

OUTPUT

ACC-tCE

.

ADDRESS VALID

tCE

tOE

tDF

tOH

VALID

HIGH Z

tACC

tRO

OUTPUT

after the address transition without impact on t

ACC

.

ACC-tOE

after an address change

14

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

Input Test Waveforms and Measurement Level

tR,tF<5ns

Output Test Load

AT49BV1604A(T)/1614A(T)

Pin Capacitance

f=1MHz,T=25°C

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

(1)

46pFV

812pFV

IN

OUT

=0V

=0V

1411F–FLASH–03/02

15

AC Byte/Word Load Characteristics

Symbol Parameter Min Max Units

t

AS,tOES

t

AH

t

CS

t

CH

t

WP

t

DS

t

DH,tOEH

t

WPH

Address, OE Setup Time 0 ns

Address Hold Time 40 ns

Chip Select Setup Time 0 ns

Chip Select Hold Time 0 ns

Write Pulse Width (WE or CE)40ns

Data Setup Time 30 ns

Data, OE Hold Time 0 ns

Write Pulse Width High 30 ns

AC Byte/Word Load Waveforms

WE Controlled

Controlled

CE

16

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

t

BP

t

BPVPP

t

AS

t

AH

t

DS

t

DH

t

WP

t

WPH

t

WC

t

SR/W

t

RP

t

RH

t

EC

t

ECVPP

t

SEC

t

EPS

Byte/Word Programming Time (0V < VPP< 4.5V) 20 50 µs

Byte/Word Programming Time (VPP> 4.5V) 10 25 µs

Address Setup Time 0ns

Address Hold Time 40 ns

Data Setup Time 30 ns

Data Hold Time 0ns

Write Pulse Width 40 ns

Write Pulse Width High 30 ns

Write Cycle Time 70 ns

Latency between Read a nd Write Operations 50 ns

Reset Pulse Wi dth 500 ns

Reset High Time before Read 50 ns

Chip Erase Cyc le Time (VPP<4.5V) 12 seconds

Chip Erase Cyc le Time (VPP> 4.5V) 6 seconds

Sector Erase Cycle Time (VPP<4.5V) 300 400 ms

Erase or Program Suspen d Time 15 µs

Program Cycle Waveforms

OE

CE

WE

A0- A20

DA

TA

t

AS

555

t

WC

t

AH

AA

PROGRAM CYCLE

t

WP

t

DH

AAA

t

DS

55

555

t

WPH

t

SR/W

ADDRESS

A0

INPUT DATA

t

BP

VALID

READ ADDRESS

t

ACC

OUTPUT
DATA

1411F–FLASH–03/02

17

Sector or Chip Erase Cycle Waveforms

(1)

OE

CE

WE

t

WP

t

AS

t

AH

t

DH

t

WPH

t

SR/W

t

t

EC

A0 - A20

DATA

555

t

WC

WORD 0

AA

AAA AAA

t

DS

55 55

WORD 1 WORD 2

555

80

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

555

WORD 3

AA

WORD 4

Note 2

Note 3

WORD 5

ADDRESS
VALID

OUTPUT
VALID

t

ACC

18

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Data Hold Time 10 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t

spec in “AC Read Characteristics” on page 14.

OE

Data Polling Waveforms

ns

Toggle Bit Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Data Hold Time 10 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

OE High Pulse 50 ns

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t

Toggle Bit Waveforms

spec in “AC Read Characteristics” on page 14.

OE

(1)(2)(3)

ns

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The t

specification must be met by the toggling input(s).

OEHP

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

1411F–FLASH–03/02

19

Software Product Identification Entry

LOAD DATA AA

TO

ADDRESS 555

(1)

Sector Lockdown Enable Algorithm

LOAD DATA AA

TO

ADDRESS 555

(1)

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA 90

TO

ADDRESS 555

ENTER PRODUCT

IDENTIFICATION

(2)(3)(5)

MODE

Software Product Identification Exit

LOAD DATA AA

TO

ADDRESS 555

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA F0

TO

ADDRESS 555

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

OR

LOAD DATA F0

TO

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

(1)(6)

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA 80

TO

ADDRESS 555

LOAD DATA AA

TO

ADDRESS 555

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA 60

TO

SECTOR ADDRESS

PAUSE 200 µs

(2)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t
Care).

2. Sector Lockdown feature enabled.

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t
Care).

2. A1 - A19 = V

Code is read for A0 = V

. Manufacturer Code is read for A0 = VIL;Device

IL

.

IH

Additional Device Code is read for address 0003H

3. The device does not remain in identification mode if

powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH(x8); 001FH(x16)

Device Code: C0H (x8) - AT49BV/LV16X4A;

00C0H (x16) - AT49BV/LV16X4A;
C2H (x8) - AT49BV/LV16X4AT;
00C2H (x16) - AT49BV/LV16X4AT.

Additional Device Code: C8H (x8) - AT49BV/LV16X4A(T)

00C8H (x16) - AT49BV/LV16X4A(T)

6. Either one of the Product ID Exit commands can be used.

20

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

Status Bit Table

Status Bit

I/O7 I/O6 I/O2

Read Address In Plane A Plane B Plane A Plane B Plane A Plane B

While

Programming in Plane A I/O7

Programming in Plane B DATA I/O7

Erasing in Plane A 0 DATA TOGGLE DATA TOGGLE DATA

Erasing in Plane B DATA 0 DATA TOGGLE DATA TOGGLE

Erase Suspended & Read
Erasing Sector

Erase Suspended & Read
Non-erasing Sector

Erase Suspended &
ProgramNon-erasing Sector
in Plane A

Erase Suspended &
ProgramNon-erasing Sector
in Plane B

1 1 1 1 TOGGLE TO GGLE

DATA DATA DATA DATA DATA DATA

I/O7

DATA I/O7

DATA TOGGLE DATA 1 DATA

DATA TOGGLE DATA 1

DATA TOGGLE DATA TOGGLE DATA

DATA TOGGLE DATA TOGGLE

1411F–FLASH–03/02

21

AT49BV1604A(T)/1614A(T) Ordering Information

(mA)

I

t

ACC

(ns)

CC

Ordering Code Package Operation RangeActive Standby

70 25 0.01 AT49BV1604A-70CI

AT49BV1604A-70TI

90 25 0.01 AT49BV1604A-90CI

AT49BV1604A-90TI

70 25 0.01 AT49BV1604AT-70CI

AT49BV1604AT-70TI

90 25 0.01 AT49BV1604AT-90CI

AT49BV1604AT-90TI

70 25 0.01 AT49BV1614A-70CI

AT49BV1614A-70TI

90 25 0.01 AT49BV1614A-90CI

AT49BV1614A-90TI

70 25 0.01 AT49BV1614AT-70CI

AT49BV1614AT-70TI

90 25 0.01 AT49BV1614AT-90CI

AT49BV1614AT-90TI

AT49LV1614A(T) Ordering Information

I

(mA)

t

ACC

(ns)

70 25 0.01 AT49LV1614A-70CI

70 25 0.01 AT49LV1614AT-70CI

CC

Ordering Code Package Operation RangeActive Standby

AT49LV1614A-70TI

AT49LV1614AT-70TI

45C1

48T

45C1

48T

45C1

48T

45C1

48T

48C5

48T

48C5

48T

48C5

48T

48C5

48T

48C5

48T

48C5

48T

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Industrial

(-40° to 85°C)

Package Type

45C1 45-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

48C5 48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

48T 48-lead, Plastic Thin Small Outline Package (TSOP)

22

AT49BV1604A(T)/1614A(T)

1411F–FLASH–03/02

Packaging Information

45C1 – CBGA

Dimensions in Millimeters and (Inches).
Controlling dimension: millimeters.

AT49BV1604A(T)/1614A(T)

6.60 (0.260)

6.40 (0.252)

A1 ID

7.60 (0.299)

7.40 (0.291)

NON-ACCUMULATIVE

2325 Orchard Parkway

R

San Jose, CA 95131

1.20 (0.047) MAX

0.625 (0.025) REF

0.75 (0.0295) BSC

A

B

C

D

E

F

0.75 (0.0295) BSC

NON-ACCUMULATIVE

5.25 (0.207)

6587 4321

3.75 (0.148)

TITLE

45C1, 45-ball (8 x 6 Array), 0.75 mm Pitch, 6.5 x 7.5 x 1.2 mm

Chip-scale Ball Grid Array Package (CBGA)

1.875(0.074) REF

0.30 (0.014)
DIA BALL TYP

0.15 (0.006)MIN

DRAWING NO.

45C1

4/11/01

REV.

A

1411F–FLASH–03/02

23

48C5 – CBGA

Dimensions in Millimeters and (Inches).
Controlling dimension: millimeters.

6.10 (0.240)

5.90 (0.232)

A1 ID

8.10 (0.319)

7.90 (0.311)

1.00(0.039) REF

0.80 (0.0315) BSC

NON-ACCUMULATIVE

NON-ACCUMULATIVE

A

B

C

D

E

F

G

H

0.80 (0.0315) BSC

TOP VIEW

4.00(0.157)

6 54321

BOTTOM VIEW

1.20 (0.047) MAX

1.20 (0.047) REF

5.60 (0.220)

0.40 (0.016)
DIA BALL TYP

0.25 (0.010)MIN

SIDE VIEW

24

2325 Orchard Parkway

R

San Jose, CA 95131

48C5, 48-ball (6 x 8 Array), 0.80 mm Pitch, 6 x 8 x 1.2 mm
Chip-scale Ball Grid Array Package (CBGA)

AT49BV1604A(T)/1614A(T)

TITLE

DRAWING NO.

48C5

1411F–FLASH–03/02

10/18/01

REV.

A

48T – TSOP

AT49BV1604A(T)/1614A(T)

PIN 1

Pin 1 Identifier

D1

D

e

E

b

A2

A

SEATING PLANE

A1

Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 8º

L

COMMON DIMENSIONS

SYMBOL

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 19.80 20.00 20.20

D1 18.30 18.40 18.50 Note 2

E 11.90 12.00 12.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

MIN

c

L1

GAGE PLANE

(Unit of Measure = mm)

NOM

MAX

NOTE

2325 Orchard Parkway

R

San Jose, CA 95131

1411F–FLASH–03/02

TITLE

48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

DRAWING NO.

48T

10/18/01

REV.

B

25

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway
San Jose, CA 95131
TEL [phone]
FAX [phone]

Europe

Atmel SarL
Route des Arsenaux 41
Casa Postale 80
CH-1705 Fribourg
Switzerland
TEL [phone]
FAX [phone]

Asia

Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL [phone]
FAX [phone]

Japan

Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL [phone]
FAX [phone]

Memory

Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL [phone]
FAX [phone]

Microcontrollers

Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL [phone]
FAX [phone]

Atmel Nantes
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL [phone]
FAX [phone]

ASIC/ASSP/Smart Cards

Atmel Rousset
Zone Industrielle
13106 Rousset Cedex, France
TEL [phone]
FAX [phone]

Atmel Colorado Springs
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL [phone]
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RF/Automotive

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Colorado Springs, CO 80906
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Biometrics/Imaging/Hi-Rel MPU/
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Atmel Grenoble
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Atmel Smart Card ICs
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
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whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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