Datasheet AT28C256 Datasheet
Industrial Grade 256-Kbit (32,768 x 8)
Paged Parallel EEPROM
Features
• Fast Read Access Time: 150 ns
• Automatic Page Write Operation:
– Internally organized as 32,768 x 8 (256K)
– Internal address and data latches for 64 bytes
– Internal control timer
• Fast Write Cycle Time:
– Page Write cycle time: 3 ms or 10 ms maximum
– 1 to 64-byte Page Write operation
• Low-Power Dissipation:
– 50 mA active current
– 200 µA CMOS standby current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology:
– Endurance: 10,000 or 100,000 cycles
– Data retention: 10 years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC® Approved Byte-Wide Pinout
• Industrial Temperature Range
AT28C256
Packages
• 32-Lead PLCC, 28-Lead PDIP, 28-Lead SOIC, 28-Lead TSOP
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 1
AT28C256
Table of Contents
Features......................................................................................................................................................... 1
Packages........................................................................................................................................................1
1. Package Types (Not to Scale).................................................................................................................4
2. Pin Descriptions...................................................................................................................................... 5
3. Description.............................................................................................................................................. 6
3.1. Block Diagram.............................................................................................................................. 6
4. Electrical Characteristics.........................................................................................................................7
4.1. Absolute Maximum Ratings..........................................................................................................7
4.2. DC and AC Operating Range.......................................................................................................7
4.3. DC Characteristics....................................................................................................................... 7
4.4. Pin Capacitance........................................................................................................................... 8
5. Normalized ICC Graphs........................................................................................................................... 9
6. Device Operation.................................................................................................................................. 10
6.1. Operating Modes........................................................................................................................ 11
6.2. AC Read Characteristics............................................................................................................ 11
6.3. AC Read Waveforms
(1, 2, 3, 4)
.....................................................................................................12
6.4. Input Test Waveforms and Measurement Level.........................................................................12
6.5. Output Test Load........................................................................................................................12
6.6. AC Write Characteristics............................................................................................................ 13
6.7. AC Write Waveforms..................................................................................................................13
6.8. Page Mode Characteristics........................................................................................................ 14
6.9. Page Mode Write Waveforms
(1,2)
............................................................................................... 15
6.10. Chip Erase Waveforms...............................................................................................................15
6.11. Software Data Protection Enable Algorithm
6.12. Software Data Protection Disable Algorithm
6.13. Software Protected Program Cycle Waveform
6.14. Data Polling Characteristics
(1)
....................................................................................................18
(1)
............................................................................16
(1)
...........................................................................17
(1,2)
..................................................................... 18
6.15. Data Polling Waveforms.............................................................................................................19
6.16. Toggle Bit Characteristics
(1)
....................................................................................................... 19
6.17. Toggle Bit Waveforms.................................................................................................................19
7. Packaging Information.......................................................................................................................... 21
7.1. Package Marking Information.....................................................................................................21
8. Revision History.................................................................................................................................... 28
The Microchip Website.................................................................................................................................29
Product Change Notification Service............................................................................................................29
Customer Support........................................................................................................................................ 29
Product Identification System.......................................................................................................................30
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 2
AT28C256
Microchip Devices Code Protection Feature................................................................................................ 31
Legal Notice................................................................................................................................................. 31
Trademarks.................................................................................................................................................. 31
Quality Management System....................................................................................................................... 32
Worldwide Sales and Service.......................................................................................................................33
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 3
1. Package Types (Not to Scale)
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1
323130
14151617181920
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
A14DCV
CC
WE
A13
32-Lead P
LCC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
28-Lead PDIP/SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
A13
WE
V
CC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
28-Lead TSOP
Top View
AT28C256
Package Types (Not to Scale)
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 4
2. Pin Descriptions
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name 32-Lead PLCC 32-Lead TSOP 28‑Lead PDIP Function
DC 1 — — Don’t Connect
A14 2 8 1 Address
A12 3 9 2 Address
A7 4 10 3 Address
A6 5 11 4 Address
A5 6 12 5 Address
A4 7 13 6 Address
A3 8 14 7 Address
A2 9 15 8 Address
A1 10 16 9 Address
A0 11 17 10 Address
NC 12 — — No Connect
I/O0 13 18 11 Data Input/Output
I/O1 14 19 12 Data Input/Output
I/O2 15 20 13 Data Input/Output
GND 16 21 14 Ground
DC 17 — — Don’t Connect
I/O3 18 22 15 Data Input/Output
I/O4 19 23 16 Data Input/Output
I/O5 20 24 17 Data Input/Output
I/O6 21 25 18 Data Input/Output
I/O7 22 26 19 Data Input/Output
CE 23 27 20 Chip Enable
A10 24 28 21 Address
OE 25 1 22 Output Enable
NC 26 — — No Connect
A11 27 2 23 Address
A9 28 3 24 Address
A8 29 4 25 Address
A13 30 5 26 Address
WE 31 6 27 Write Enable
V
CC
AT28C256
Pin Descriptions
(1)
(2)
(1)
(2)
32 7 28 Device Power Supply
Notes:
1. The user cannot connect anything to this terminal.
2. No internal wire bonded from die to this terminal.
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 5
3. Description
V
CC
Y Decoder
Address
Inputs
X Decoder
Data Inputs/Outputs
Data Latch
Input/Output Buffers
Y-Gating
Cell Matrix
Identification
OE, CE and WE Logic
GND
OE
WE
CE
I/O0-I/O7
The AT28C256 is a high‑performance Electrically Erasable and Programmable Read‑Only Memory (EEPROM).
Its 256‑Kb memory is organized as 32,768 words by 8 bits. Manufactured with Microchip’s advanced nonvolatile
CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device
is deselected, the CMOS standby current is less than 200 µA.
The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components.
The device contains a 64‑byte page register to allow for writing up to 64 bytes simultaneously. During a write cycle,
the address and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations.
Following the initiation of a write cycle, the device will automatically write the latched data using an internal control
timer. The end of a write cycle can be detected by
detected, a new access for a read or write can begin.
The AT28C256 has additional features to ensure high quality and manufacturability. The device utilizes internal error
correction for extended endurance and improved data retention characteristics. An optional software data protection
mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM
for device identification or tracking.
3.1 Block Diagram
AT28C256
Description
DATA Polling of I/O7. Once the end of a write cycle has been
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 6
4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Temperature under bias -55°C to +125°C
Storage temperature -65°C to +150°C
All input voltages (including NC pins) with respect to ground -0.6V to +6.25V
All output voltages with respect to ground -0.6V to VCC + 0.6V
Voltage on OE and A9 with respect to ground -0.6V to +13.5V
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4.2 DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT28C256
Electrical Characteristics
Operating Temperature (Case) Industrial -40°C to +85°C
VCC Power Supply 5V ± 10%
4.3 DC Characteristics
Table 4-2. DC Characteristics
Parameter Symbol Minimum Maximum Units Test Conditions
Input Load Current I
Output Leakage Current I
VCC Standby Current CMOS I
VCC Standby Current TTL I
VCC Active Current I
Input Low Voltage V
Input High Voltage V
Output Low Voltage V
Output High Voltage V
LI
LO
SB1
SB2
CC
OL
OH1
AT28C256‑15
— 10 μA VIN = 0V to VCC + 1V
— 10 μA V
= 0V to V
I/O
CC
— 200 μA CE = VCC - 0.3V to VCC + 1V
— 3 mA CE = 2.0V to VCC + 1V
— 50 mA f = 5 MHz; I
IL
IH
— 0.8 V
2.0 — V
OUT
= 0 mA
— 0.45 V IOL = 2.1 mA
2.4 — V IOH = -400 μA
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 7
4.4 Pin Capacitance
Table 4-3. Pin Capacitance
Symbol Typical Maximum Units Conditions
AT28C256
Electrical Characteristics
(1,2)
C
IN
C
OUT
Notes:
1. This parameter is characterized but is not 100% tested in production.
2. f = 1 MHz, TA = 25°C
4 6 pF VIN = 0V
8 12 pF V
OUT
= 0V
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 8
5. Normalized ICC Graphs
12595
65
355-25-55
0.8
0.9
1.0
1.1
1.2
1.3
Temperature (°C)
Normalized ICC
5
4
3
2
0
0.6
0.7
0.8
0.9
1.0
1.1
Normalized ICC
Frequency (MHz)
1
VCC = 5V
T = 25°C
1.4
1.2
1.0
0.8
0.6
4.50
4.75
5.00 5.25 5.25
Normalized I
CC
Supply Voltage(V)
Figure 5-1. Normalized Supply Current vs. Temperature
Figure 5-2. Normalized Supply Current vs. Address Frequency
AT28C256
Normalized ICC Graphs
Figure 5-3. Normalized Supply Current vs. Supply Voltage
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 9
6. Device Operation
READ: The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at
the memory location determined by the address pins is asserted on the outputs. The outputs are put in the highimpedance state when either CE or OE is high. This dual-line control offers designers flexibility in preventing bus
contention in their system.
BYTE WRITE: A low pulse on the
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write is started, it will automatically time itself to completion. Once a
programming operation is initiated and for the duration of tWC, a read operation will effectively be a polling operation.
PAGE WRITE: The page write operation of the AT28C256 allows 1 to 64 bytes of data to be written into the device
during a single internal programming period. A page write operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within
150 µs (t
commence the internal programming operation. All bytes during a page write operation must reside on the same
page as defined by the state of the A6‑A14 inputs. For each WE high‑to‑low transition during the page write
operation, A6‑A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be
written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes that are
specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
DATA POLLING: The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page
write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true data is valid on all outputs and the next write cycle may
begin. DATA Polling may begin at any time during the write cycle.
TOGGLE BIT: In addition to
cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the write is completed, I/O6 will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Microchip incorporated both hardware and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C256 in the following
ways:
• VCC sense – if VCC is below 3.8V (typical), the write function is inhibited
• VCC power‑on delay – once VCC has reached 3.8V, the device will automatically time out 5 ms (typical) before
• Write inhibit – holding any one of
• Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle
SOFTWARE DATA PROTECTION: A software-controlled data protection feature has been implemented on the
AT28C256. When enabled, the software data protection (SDP) will prevent inadvertent writes. The SDP feature may
be enabled or disabled by the user; the AT28C256 is shipped with SDP disabled.
SDP is enabled by the host system issuing a series of three write commands while three specific bytes of data are
written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3‑byte command
sequence and after tWC, the entire AT28C256 will be protected against inadvertent write operations. Note that, once
protected, the host may still perform a byte or page write to the AT28C256. This is done by preceding the data to be
written by the same 3‑byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable
SDP and SDP will protect the AT28C256 during power‑up and power‑down conditions. All command sequences must
conform to the page write timing specifications. The data in the enable and disable command sequences is not
written to the device and the memory addresses used in the sequence may be written with data in either a byte or
page write operation.
) of the previous byte. If the t
BLC
allowing a write
AT28C256
Device Operation
WE or CE input with CE or WE low (respectively) and OE high initiates a write
limit is exceeded, the AT28C256 will cease accepting data and
BLC
DATA Polling, the AT28C256 provides another method for determining the end of a write
OE low, CE high or WE high inhibits write cycles
© 2020 Microchip Technology Inc.
Datasheet
DS20006386A-page 10
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