Datasheet AT25P1024W1-10SI-2.7, AT25P1024W1-10SI-1.8, AT25P1024W1-10SI, AT25P1024W1-10SC-2.7, AT25P1024W1-10SC-1.8 Datasheet (ATMEL)

Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

•

2.1 MHz Clock Rate

•

128-Byte Page Mode Only for Write Operations

•

Low Voltage and Standard Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)

•

Block Write Protection

– Protect 1/4, 1/2, or Entire Array

•

Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection

•

Self-Timed Write Cycle (5 ms Typical)

•

High Reliability

– Endurance: 100,000 Write Cycles
– Data Retention: >40 Years
– ESD Protection: >3000V

•

20-Pin JEDEC SOIC and 8-Pin Leadless Array Package

SPI Serial
EEPROMs

1M (131,072 x 8)

AT25P1024

Description

The AT25P1024 provi des 1,048 ,576 bits of s erial ele ctrically erasabl e program mable
read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device
is optimized for u se in m any ind ustri al and comm erci al a pplic atio ns w here low pow er
and low voltage operatio n are ess ential. The AT25P 1024 is av ailab le in spac e savin g
20-pin JEDEC SOIC and 8-pin leadless array (LAP) packages.

(continued)

Pin Configurations

Pin Name Function

CS

Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP

Write Protect
HOLD Suspends Serial Input
NC No Connect

CS
SO
NC
NC
NC
NC
NC
NC

WP

GND

VCC

HOLD

SCK

SI

20-Lead SOIC

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

8-Pin LAP

8
7
6
5

1
2
3
4

VCC
HOLD
NC
NC
NC
NC
NC
NC
SCK
SI

CS
SO
WP
GND

Preliminary

Bottom View

Rev. 1082C–08/98

1

The AT25P1024 is enabled through the Chip Select pin

) and accessed via a 3-wire interface consisting of

(CS
Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All progr amming cycle s are co mpletely s elf­timed, and no separate ERASE cycle is required before
WRITE.

BLOCK WRITE protection is enabled by programming the
status register with top ¼, top ½ or entire array of write pro­tection. Separate program enable and program disable
instructions are provided for additional data protection.
Hardware d ata protection is pr ovided via the WP
tect against inadvertent write attempts to the status regis­ter. The HOLD
communication without resetting the serial sequence.

pin may be used to suspend any serial

pin to pro-

Block Diagram

Absolute Maximum Ratings*

Operating Temperature..................................-55°C to +125°C

Storage Temperature .....................................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground.................................... -1.0V to +7.0V

Maximum Operating Voltage...........................................6.25V

DC Output Current........................................................5.0 mA

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” ma y cause permanent d amage to th e
device. This is a stress rating only and functional
operation of the device at these or any other condi­tions beyond those indicated in the operational sec­tions of this specif ic ati on is n ot im pl ie d. Ex pos ure to
absolute maximum rating conditions for extended
periods may affect device reliability.

131,072 x 8

2

AT25P1024

AT25P1024

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Test Conditions Max Units Conditions

C

OUT

C

IN

Output Capacitance (SO) 8 pF V
Input Capacitance (CS, SCK, SI, WP, HOLD)6pFV

OUT

IN

= 0V

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,

= 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).

T

AC

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

V

CC2

V

CC3

I

CC1

I

CC2

I

SB1

I

SB2

I

SB3

I

IL

I

OL

(1)

V

IL

(1)

V

IH

V

OL1

V

OH1

V

OL2

V

OH2

Note: 1. V

Supply Voltage 1.8 3.6 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V at 1 MHz, SO = Open Read 2.0 5.0 mA
Supply Current VCC = 5.0V at 2 MHz, SO = Open Write 4.0 7.0 mA
Standby Current VCC = 1.8V, CS = V
Standby Current VCC = 2.7V, CS = V
Standby Current VCC = 5.0V, CS = V
Input Leakage VIN = 0V to V

CC

CC

CC

CC

-3.0 3.0

0.1 3.0

0.2 3.0

2.0 7.0

Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C-3.0 3.0
Input Low Voltage -0.6 V

x 0.3 V

CC

Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage
Output High Voltage IOH = -1.6 mA VCC - 0.8 V

4.5V ≤ V

≤ 5.5V

CC

Output Low Voltage
Output High Voltage IOH = -100 µAVCC - 0.2 V

1.8V ≤ V

and VIH max are reference only and are not tested.

IL

≤ 3.6V

CC

I

= 3.0 mA 0.4 V

OL

I

= 0.15 mA 0.2 V

OL

µ

A

µ

A

µ

A

µ

A

µ

A

3

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,

= 1 TTL Gate and 100 pF (unless otherwise noted).

C

L

Symbol Parameter Voltage Min Max Units

f

SCK

SCK Clock Frequency

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

0
0
0

2.1

1.0

0.5

MHz

t

t

t

t

t

t

t

t

RI

FI

WH

WL

CS

CSS

CSH

SU

Input Rise Time

Input Fall Time

SCK High Time

SCK Low Time

CS High Time

CS Setup Time

CS Hold Time

Data In Setup Time

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

200
400
800

200
400
800

250
500

1000

100
250

1000

150
250

1000

30
50

100

2
2

s

µ

2
2

2

s

µ

2

ns

ns

ns

ns

ns

ns

4.5 - 5.5

t

H

Data In Hold Time

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

t

HD

Hold Setup Time

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

t

CD

Hold Hold Time

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

t

V

Output Valid

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

t

HO

Output Hold Time

2.7 - 5.5

1.8 - 3.6

4

AT25P1024

50
50

100
100

100
400

200
300
400

0
0
0

0
0
0

200
400
800

ns

ns

ns

ns

ns

AT25P1024

AC Characteristics (Continued)

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,

= 1 TTL Gate and 100 pF (unless otherwise noted).

C

L

Symbol Parameter Voltage Min Max Units

t

LZ

t

HZ

t

DIS

t

WC

Endurance

Note: 1. This parameter is characterized and is not 100% tested.

Hold to Output Low Z

Hold to Output High Z

Output Disable Time

Write Cycle Time

(1)

5.0V, 25°C, Page Mode

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

0
0
0

100K

100
200
300

100
200
300

200
250

1000

5
10
10

Write

Cycles

ns

ns

ns

ms

5

Serial Interface Description

MASTER:
SLAVE:

input, the AT25P1024 always operates as a slave.

TRANSMITTER/RECEIVER:

separate pins designated for data transmission (SO) and
reception (SI).

MSB:

transmitted and received.

SERIAL OP-CODE:

going low, the first byte will be receiv ed. This byte co ntains
the op-code that defines the operations to be performed.

INVALID OP-CODE:

data will be shifted into t he AT2 5P102 4, and the serial o ut­put pin (SO) will rema in in a h igh imped ance s tate un til th e
falling edge of CS
serial communication.

CHIP SELECT:

pin is low. When the devi ce is not s ele ct ed, d ata wi ll not b e
accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.

HOLD:

pin to select the AT25P1024. When the device is selected
and a serial sequence is underway, HOLD
pause the serial communication with the master device
without resetting the ser ial sequ ence. To pa use, the HOLD
pin must be brought lo w while the SCK pin is low. To
resume serial communication, the HOLD
high while the SCK pin is low (SCK may still toggle during
HOLD
is in the high impedance state.

WRITE PROTECT:

normal read/ write opera tions when he ld high. Wh en the

pin is brought low an d WPEN bit is “ 1”, all wr ite oper a-

WP
tions to the status registe r are inhibited. WP
while CS
ter. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the

The device that generates the serial clock.

Because t he Serial Clock pin (SCK) is always an

The AT25P1024 has

The Most Significant Bit (MSB) is the first bit

After the device is selected with CS

If an invalid op-c ode i s recei ved, n o

is detected again. This will reinitialize the

The AT25P1024 is selected when the CS

The HOLD

pin is us ed in conju nctio n wit h the CS

can be used to

pin is brought

). Inputs to the SI pin will be ignored while the SO pin

The write protect pin (WP

) will allow

going low

is still low will interrupt a write to the status regis-

status register. The WP

pin function is blocked when the
WPEN bit in the statu s register is “0”. This wil l allow the
user to install the AT25P1024 in a system with the WP

pin
tied to ground and still be able to write to the status regis­ter. All WP

pin functions are enabled when the WPEN bit is

set to “1”.

SPI Serial Interface

MASTER:

MICROCONTROLLER

DATA OUT (MOSI)

DATA IN (MISO)

SERIAL CLOCK (SPI CK)

SS0

SS1

SS2

SS3

SLAVE:

AT25P1024

SI

SO

SCK

CS

SI

SO

SCK

CS

SI

SO

SCK

CS

SI

SO

SCK

CS

6

AT25P1024

Functional Description

The AT25P1024 is designed to interface directly with the
synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.

The AT25P1024 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are trans­ferred with the MSB first and start with a hi gh-to-l ow transi­tion.

Table 1.

Instruction
Name

WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array

WRITE ENABLE (WREN):

write disable state when V
instructions mus t t here fo re be p reced ed b y a Wr ite Enab le
instruction.

WRITE DISABLE (WRDI):

inadvertent writes, the Wr it e Dis able i nst ru cti on disabl es all
programming modes. The WRDI ins tructio n is ind ependen t
of the status of the WP

READ STATUS REGISTER (RDSR):

Register instruction provides access to the status register.
The READY/BUSY an d Write Enable sta tus of th e devic e
can be determined by the RDSR instruction. Similarly, the
Block Write Pr otec tion bits i ndic ate th e exten t o f prote ctio n
employed. These bits are set by using the WRSR instru c­tion.

Table 2.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Instruction Set for the AT25P1024

Instruction
Format Operation

The device will power u p in th e

is applied. All programming

CC

To protect the device against

pin.

The Read Status

Status Register Format

AT25P1024

Table 3.

Bit Definition

Bit 0 (RDY

Bit 1 (WEN) Bit 1= 0 indicates the device

Bit 2 (BP0) See Table 4.
Bit 3 (BP1) See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.

WRITE STATUS REGISTER (WRSR):

tion allows the user to select one of four levels of protec­tion. The AT25P1024 is div ided into four array se gments.
Top quarter (1/4), top half (1/2), or all of the memory seg­ments can be protected. Any of the data within any
selected segment wil l therefore be READ only. The block
write protection levels and corre sponding status register
control bits are shown in Table 4.

The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same pro perties and functi ons as the regul ar
memory cells (e.g. WREN, t

Table 4.

Level

000 None
1(1/4) 0 1 01800 - 01FFFF
2(1/2) 1 0 010000 - 01FFFF
3(All) 1 1 0000 - 01FFFF

The WRSR instruction also allows the user to enable or
disable the write protect (WP
Write Protect Enable (WPEN) bit. Hardware write protec­tion is ena bl e d wh en t h e W P
“1”. Hardware write protection is disabled when
WP
hardware write protected, writes to the Status Register,
including the Bloc k Protec t bits and the WPEN bi t, and the
block-protected sec tions in the memor y arra y are disab led.

Read Status Register Bit Definition

) Bit 0 = 0 (RDY) indicates the device is

READ Y. Bit 0 = 1 indicates the write cycle is in
progress.

is not

WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.

The WRSR instruc-

, RDSR).

WC

Block Write Protect Bits

Status Register Bits Array Addresses Protected

BP1 BP0 AT25P1024

) pin through the use of the

pin is low and the WPEN bit is

either

the

pin is high or the WPEN bit is “0.” When the device is

7

Writes are only allowed to sections of the memory which
are not block-protected.

Note: When the WPEN bit is hardware write protected, it can-

not be changed bac k to “0”, as long a s the WP
low.

Table 5.

WPEN WP WEN

READ SEQUENCE (READ):

WPEN Operation

Protected

Blocks

0 X 0 Protected Protected Prot e cted
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Prot e cted
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable

Unprotected

Blocks

Reading the AT25P1024

pin is held

Status

Register

via the SO (Serial Output) p in requires the following
sequence. After the CS

line is pulled low to select a device,
the READ op-code is transmitted via the SI line followed by
the byte address to be rea d (Refer to Tab le 6). Upon com­pletion, any data on the SI line will be ignored. The data
(D7-D0) at the specified address is then shifted out onto
the SO line. If only one byte is to be read, the CS

line
should be driven hig h after the da ta come s out. The READ
sequence can be continued since the byte address is auto­matically incremented a nd data will continue to be shifted
out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the
entire memory to be read in one continuous READ cycle.

WRITE SEQUENCE (WRITE):

In order to program the
AT25P1024, two separate instruc tions must be executed.
First, the device

must be write enabled

via the Write
Enable (WREN) Instruction. Then a Write (WRITE) Instruc­tion may be executed. Also, the address of the memory
location(s) to be programmed must be outside the pro­tected address field location selected by the Block Write

Protection Level. During an internal write c ycle, all com­mands will be ignored except the RDSR instruction.

A Write Instruc tion r equires the foll owing s equence. After
the CS

line is pulled lo w to select the device , the W RITE
op-code is transmitted via the S I line follo wed by the byte
address and the data (D7- D0) to be programme d (Refer to
Table 6). Programming will s tar t aft er the CS
high. (The LOW to High transition of the CS

pin is brought

pin must occur
during the SCK low ti me immedi ately after c locking in th e
D0 (LSB) data bit.

The READY/BUSY status of the devic e can be determine d
by initiating a READ STATUS REGISTER (RDSR) Instruc­tion. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0
= 0, the WRITE cycle has ended. Only the READ STATUS
REGISTER instruction is enabled during the WRITE pro­gramming cycle.

The AT25P1024 is capable o f a 128-byte PAGE WRI TE
operation ONLY. Conte nt of the page in the arra y will not
be guaranteed if less than 12 8 bytes of data is recei ved
(byte operation is not s upp orted ). A fte r eac h by te o f dat a is
received, the seven low order address bits are inter nally
incremented by one; the high order bits of the address will
remain constant. If more than 128 bytes of data are trans­mitted, the address c ou nter wi ll roll ov er an d th e prev i ous ly
written data will be overwritten. The AT25P1024 is auto­matically returned to the write disable state at the comple­tion of a WRITE cycle.

NOTE:

If the device is not Write enabl ed (WREN), the
device will igno re the Wr it e instruction and wil l r etu rn to th e
standby state, when CS

is brought high. A new CS falli ng

edge is required to re-initiate the serial communication.

Table 6.

Address Key

Address AT25P1024

A

N

Don’t Care Bits A

A16 - A

23

- A

0

17

8

AT25P1024

Timing Diagrams (for SPI Mode 0 (0, 0))

Synchronous Data Timing

V

IH

CS

V

IL

t

CSS

V

WREN Timing

SCK

SO

IH

V

IL

t

SU

V

IH

SI

V

IL

V

OH

HI-Z

V

OL

VALID IN

t

WH

t

H

AT25P1024

t

CS

t

CSH

t

WL

t

V

t

HO

t

DIS

HI-Z

WRDI Timing

9

RDSR Timing

CS

01234567891011121314

SCK

WRSR Timing

SO

SI

INSTRUCTION

HIGH IMPEDANCE

DATA OUT

76543210

MSB

READ Timing

10

CS

SCK

SI

SO

0123445566778 9 10 11 28

3-BYTE ADDRESS

INSTRUCTION

HIGH IMPEDANCE

23 22 21 3

AT25P1024

29 30 31 32 33 34 35 36 37 38

...

21

32100

WRITE Timing

CS

AT25P1024

SCK

SI

SO

HOLD Timing

HOLD

0123456789101128

3-BYTE ADDRESS

INSTRUCTION

232221 3 10 654321072

HIGH IMPEDANCE

CS

t

CD

SCK

t

HD

t

SO

29 30 31 32 33 34

1st BYTE DATA-IN

t

HD

HZ

1051

t

t

1052

CD

LZ

1053

1054

1055

128th BYTE DATA-IN

11

Ordering Information

tWC (max)

(ms)

5 7000 7.0 2100 AT25P1024C1-10CC

10 2000 3.0 1400 AT25P1024C1-10CC-2.7

10 1000 3.0 500 AT25P1024C1-10CC-1.8

ICC (max)

(µµµµA)

7000 7.0 2100 AT25P1024C1-10CI

2000 3.0 1000 AT25P1024C1-10CI-2.7

1000 3.0 500 AT25P1024C1-10CI-1.8

ISB (max)

(µµµµA)

f

MAX

(kHz) Ordering Code Package Operation Range

AT25P1024W1-10SC

AT25P1024W1-10SI

AT25P1024W1-10SC-2.7

AT25P1024W1-10SI-2.7

AT25P1024W1-10SC-1.8

AT25P1024W1-10SI-1.8

8C1
20S

8C1
20S

8C1
20S

8C1
20S

8C1
20S

8C1
20S

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

8C1 8-Lead, 0.300" Wide, Leadless Array Package (LAP)
20S 20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

Options

Blank Standard Device (4.5V to 5.5V)

-2.7 Low Voltage (2.7V to 5.5V)

-1.8 Low Voltage (1.8V to 3.6V)

12

AT25P1024

Packaging Information

AT25P1024

8C1

, 8-Lead, 0.300" Wide, Leadless Array Package
(LAP)
Dimensions in Inches and (Millimeters)

SIDE

5.15 (0.203)

4.85 (0.191)

1.27 (0.050) TYP

TOP VIEW

8.15 (0.321)

7.85 (0.309)

BOTTOM VIEW

8

7

6

5

0.64 (0.025) TYP

1

2

3

4

VIEW

0.41 (0.016) TYP

1.30 (0.051)

1.00 (0.039)

0.42 (0.017)

0.34 (0.013)

20S

, 20-Lead, 0.300" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)

0.020 (0.508)

0.013 (0.330)

0.420 (10.7)

0.299 (7.60)

0.393 (9.98)

PIN 1

0

REF

8

.050 (1.27) BSC

0.513 (13.0)

0.497 (12.6)

0.035 (0.889)

0.015 (0.381)

0.012 (0.305)

0.003 (0.076)

0.291 (7.39)

0.013 (0.330)

0.009 (0.229)

0.105 (2.67)

0.092 (2.34)

13