Datasheet AT25HP512-10PC, AT25HP256W-10SI-2.7, AT25HP256W-10SI-1.8, AT25HP256W-10SI, AT25HP256W-10SC-2.7 Datasheet (ATMEL)

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Page 1

Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

•

10 MHz Clock Rate

•

128-Byte Page Mode Only for Write Operations

•

Low-Volta ge and Standard-Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V)

•

Block Write Protection

– Protect 1/4, 1/2, or Entire Array

•

Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection

•

High Reliability

– Endurance: 100K Write Cycles – Data Retention: > 40 Years – ESD Protection: > 3000V

•

8-Pin PDIP, 8-Pin EIAJ SOIC, and 8-Pin Leadless Array Package

Description

The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits each. The device is o ptimi zed f or u se i n man y in dustria l and com merc ial app lic ations where high-speed, low- power, and low-voltage operation are essent ial. The AT25HP256/512 is available in a space saving 8-pin PDIP (AT25HP256/512), 8-pin EIAJ SOIC (AT25HP256), and 8-pin Leadless Array (AT25HP256/512) packages. In

(continued)

SPI Serial EEPROMs

256K (32,768 x 8) 512K (65,536 x 8)

AT25HP256 AT25HP512 Preliminary

Pin Configurations

Pin Name Function

CS SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP HOLD Suspends Serial Input

CS SO

GND

Chip Select

Write Protect

8-Pin PDIP

2 3

VCC HOLD

SCK SI

CS SO

GND

8-Pin SOIC

2 3

VCC HOLD

SCK SI

8-Pin Leadless Array

VCC

HOLD

SCK

8 7 6

GND

Bottom View

Rev. 1113B–07/98

Page 2

addition, the entire family is available in 5.0V (4.5V to

5.5V), 2.7V (2.7V to 5.5V), and 1.8V (1 .8V to 3.6V) versions.

The AT25HP256/512 is enabled through the Chip Select pin (CS Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All progr amming cycle s are co mpletely s elftimed, and no separate ERASE cycle is required before WRITE.

BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware d ata protection is pr ovided via the WP tect against inadvertent write attempts to the status register. The HOLD communication without resetting the serial sequence.

) and accessed via a 3-wire interface consisting of

pin to pro-

pin may be used to suspend any serial

Block Diagram

Absolute Maximum Ratings*

Operating Temperature..................................-55°C to +125°C

Storage Temperature .....................................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground.................................... -1.0V to +7.0V

Maximum Operating Voltage................................... ...... ..6.25V

DC Output Current........................................................5.0 mA

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” ma y cause permanent d amage to th e device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specif ic ati on is n ot im pl ie d. Ex pos ure to absolute maximum rating conditions for extended periods may affect device reliability.

32,768/65,536 x 8

AT25HP256/512

Page 3

AT25HP256/512

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Test Conditions Max Units Conditions

OUT

Output Capacitance (SO) 8 pF V Input Capacitance (CS, SCK, SI, WP, HOLD)6pFV

OUT

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,

= 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

CC1

CC2

CC3

CC1

CC2

SB1

SB2

SB3

(1)

OL1

OH1

OL2

OH2

Note: 1. V

Supply Voltage 1.8 3.6 V Supply Voltage 2.7 5.5 V Supply Voltage 4.5 5.5 V Supply Current VCC = 5.0V at 5 MHz, SO = Open Read 6.0 10.0 mA Supply Current VCC = 5.0V at 5 MHz, SO = Open Write 4.0 7.0 mA Standby Current VCC = 1.8V, CS = V Standby Current VCC = 2.7V, CS = V Standby Current VCC = 5.0V, CS = V Input Leakage VIN = 0V to V

-3.0 3.0

0.1 2.0

0.2 2.0

2.0 5.0

Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C-3.0 3.0 Input Low Voltage -0.6 V

x 0.3 V

Input High Voltage VCC x 0.7 VCC + 0.5 V Output Low Voltage Output High Voltage IOH = -1.6 mA VCC - 0.8 V

4.5V ≤ V

≤ 5.5V

Output Low Voltage Output High Voltage IOH = -100 µAV

1.8V ≤ V

and VIH max are reference only and are not tested.

≤ 3.6V

= 3.0 mA 0.4 V

= 0.15 mA 0.2 V

- 0.2 V

Page 4

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,

= 1 TTL Gate and 30 pF (unless otherwise noted).

Symbol Parameter Voltage Min Max Units

SCK

SCK Clock Frequency

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

0 0 0

TBD

MHz

CSS

CSH

Input Rise Time

Input Fall Time

SCK High Time

SCK Low Time

CS High Time

CS Setup Time

CS Hold Time

Data In Setup Time

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

40 80

TBD

40 80

TBD

100

TBD

100

TBD

100

TBD

12 20

TBD

2 2

TBD

2 2

TBD

4.5 - 5.5

Data In Hold Time

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

Hold Setup Time

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

Hold Hold Time

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

Output Valid

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

Output Hold Time

2.7 - 5.5

1.8 - 3.6

AT25HP256/512

10 20

TBD

25 50

TBD

25 50

TBD

0 0 0

40 80

TBD

Page 5

AT25HP256/512

AC Characteristics (Continued)

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,

= 1 TTL Gate and 30 pF (unless otherwise noted).

Symbol Parameter Voltage Min Max Units

DIS

Endurance

Note: 1. This parameter is characterized and is not 100% tested.

Hold to Output Low Z

Hold to Output High Z

Output Disable Time

Write Cycle Time

(1)

5.0V, 25°C, Page Mode

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

0 0 0

100K

100 200

TBD

100 200

TBD

100 100

TBD

Write

Cycles

Page 6

Serial Interface Description

MASTER: SLAVE:

input, the AT25HP256/512 always operates as a slave.

TRANSMITTER/RECEIVER:

separate pins designated for data transmission (SO) and reception (SI).

MSB:

transmitted and received.

SERIAL OP-CODE:

going low, the first byte will be receiv ed. This byte co ntains the op-code that defines the operations to be performed.

INVALID OP-CODE:

data will be shifted in to th e A T25HP 256 /512, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS the serial communication.

CHIP SELECT:

pin is low. When the device is not selected, data will not

CS be accepted via the SI pin, and the seria l output pin (SO) will remain in a high impedance state.

HOLD:

pin to select the AT25HP256/512. When the device is selected and a serial sequence is underway, HOLD used to pause the se rial communica tion with the master device without resetting the serial sequence. To pause, the HOLD resume serial communication, the HOLD high while the SCK pin is low (SCK may still toggle during HOLD is in the high impedance state.

WRITE PROTECT:

normal read/ write opera tions when he ld high. Wh en the WP tions to the status registe r are inhibited. WP while CS ter. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the

The device that generates the serial clock.

Because the Serial Clock pin (SCK) is always an

The AT25HP256/512 has

The Most Significant Bit (MSB) is the first bit

After the device is selected with CS

If an invalid op-code is received, no

is detected again. This will reinitialize

The AT25HP256/512 is sele cted whe n the

The HOLD

pin must be brought low while the SCK pin is low. To

). Inputs to the SI pin will be ignored while the SO pin

pin is brought low an d WPEN bit is “ 1”, all wr ite oper a-

is still low will interrupt a write to the status regis-

pin is us ed in conju nctio n wit h the CS

can be

pin is brought

The write protect pin (WP

) will allow

going low

status register. The WP WPEN bit in the statu s register is “0”. This wil l allow the user to install the AT25HP256/512 in a system with the WP pin tied to ground and still be able to write to the status register. All WP is set to “1”.

pin functions ar e enab led wh en the WPE N bit

pin function is blocked when the

SPI Serial Interface

AT25HP256/512

Page 7

Functional Description

The AT25HP256/512 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers.

The AT25HP256/512 utilizes an 8-bit instruction register. The list of i nstruction s and th eir ope ration c odes ar e contained in Ta ble 1. All i nst ructi ons , add ress es, and dat a ar e transferred with the MSB first and start with a hi gh-to-low

transition.

Table 1.

Instruction Name

WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Re ad Status Regi ste r WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array

WRITE ENABLE (WREN):

write disable state when V instructions mus t t here fo re be p reced ed b y a Wr ite Enab le instruction.

WRITE DISABLE (WRDI):

inadvertent writes, the Wr it e Dis able i nst ru cti on disabl es all programming modes. The WRDI ins tructio n is ind ependen t of the status of the WP

READ STATUS REGISTER (RDSR):

Register instruction provides access to the status register. The READY/BUSY an d Write Enable sta tus of th e devic e can be determined by the RDSR instruction. Similarly, the Block Write Pr otec tion bits i ndic ate th e exten t o f prote ctio n employed. These bits are set by using the WRSR instru ction.

Table 2.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Instruction Set for the AT25HP256/512

Instruction Format Operation

The device will power u p in th e

is applied. All programming

To protect the device against

pin.

The Read Status

Status Register Format

AT25HP256/512

Table 3.

Bit Definition

Bit 0 (RDY

Bit 1 (WEN) Bit 1= 0 indicates the device

Bit 2 (BP0) See Table 4. Bit 3 (BP1) See Table 4. Bits 4-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5. Bits 0-7 are 1s during an internal write cycle.

WRITE STATUS REGISTER (WRSR):

tion allows the user to select one of four levels of protection. The AT25HP256/512 is div ided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write prot ection le vels and corr espondi ng stat us register control bits are shown in Table 4.

The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same pro perties and functi ons as the regul ar memory cells (e.g. WREN, t

Table 4.

Level

000 None 1(1/4) 0 1 6000 - 7FFF/C000 - FFFF 2(1/2) 1 0 4000 - 7FFF/8000 - FFFF 3(All) 1 1 0000 - 7FFF/0000 - FFFF

The WRSR instruction also allows the user to enable or disable the write protect (WP Write Protect Enable (WPEN) bit. Hardware write protection is ena bl e d wh en t h e W P “1”. Hardware write protection is disabled when WP hardware write protected, writes to the Status Register, including the Bloc k Protec t bits and the WPEN bi t, and the block-protected sec tions in the memor y arra y are disab led.

Read Status Register Bit Definition

) Bit 0 = 0 (RDY) indicates the device is

READ Y. Bit 0 = 1 indica tes the write cycle is in progress.

is not

WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED.

The WRSR instruc-

, RDSR).

Block Write Protect Bits

Status Register Bits Array Addresses Protected

BP1 BP0 AT25HP256/512

) pin through the use of the

pin is low and the WPEN bit is

either

the

pin is high or the WPEN bit is “0.” When the device is

Page 8

Writes are only allowed to sections of the memory which are not block-protected.

NOTE:

cannot be changed back to “0”, as long as the WP

When the WPEN bit is hardware write protected, it

pin is

held low.

Table 5.

WPEN WP WEN

READ SEQUENCE (READ):

WPEN Operation

Protected

Blocks

0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Pr otected Protected X High 1 Protected Writable Writable

Unprotected

Blocks

Status

Reading the AT25HP256/512 via the SO (Serial Output) pin requires the following sequence. After the CS

line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte a ddres s to be r ead (R efer to Tab le 6) . Upon completion, any data on the SI line will be ignored. The data (D7-D0 ) at the speci fied addres s is then sh ifted out onto the SO line . If only on e byte is to be read, th e CS line should be driven high after the data comes out. T he READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be rea d in one continuous REA D cycle.

WRITE SEQUENCE ( WRITE):

In order to program the AT25HP256/512, two separate instructions must be executed. First, the device

must be write enabled

via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the memory location(s) t o be pr og r amm ed mu st b e out si de th e protected address field location selected by the Block Write

Protection Level. During an internal write c ycle, all commands will be ignored except the RDSR instruction.

A Write Instruc tion r equires the foll owing s equence. After the CS

line is pulled low to select the device, the WRITE op-code is transmitted via the S I line follo wed by the byte address and the data (D7- D0) to be programme d (Refer to Table 6). Programming will s tar t aft er the CS high. (The LOW to High transition of the CS

pin is brought

pin must occur during the SCK low ti me immedi ately after c locking in th e D0 (LSB) data bit.

The READY/BUSY status of the devic e can be determine d by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle.

The AT25HP256/512 is capable of a 128-byte PAGE WRITE operation. After each by te of data is receiv ed, the seven low order address bits are intern ally incr emented by one; the high order bits of the address will remain constant. If more than 128-bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25 HP256/5 12 is automa tically returne d to the write disable state at the completion of a WRITE cycle.

NOTE:

If the device is not Write enabl ed (WREN), the device will igno re the Wr it e instruction and wil l return to the standby state, when CS

is brought high. A new CS falli ng

edge is required to re-initiate the serial communication.

Table 6.

NOTE:

Address Key

Address AT25HP256/512

Don’t Care Bits A15 / none

A14 - A0 / A15 - A

128-byte PAGE WRITE operation only

. Content of the page in the array will not be guaranteed if less than 128 bytes of data is received (byte write is not supported).

AT25HP256/512

Page 9

Timing Diagrams (for SPI Mode 0 (0, 0))

Synchronous Data Timing

CSS

SKC

WREN Timing

HI- Z

VALID IN

AT25HP256/512

CSH

DIS

HI- Z

SCK

WRDI Timing

SCK

WRDI OP-CODE

HI-Z

Page 10

RDSR Timing

01234567891011121314

SCK

WRSR Timing

HIGH IMPED

INSTRUCTION

ANCE

A OUT

DA T

76543210

MSB

READ Timing

AT25HP256/512

Page 11

WRITE Timing (AT25HP256)

AT25HP256/512

SCK

0123456789101120212223242526

BYTE ADDRESS

...

INSTRUCTION

HIGH IMPEDANCE

65432

27 28 29 30 31

1ST BYTE DATA IN

Page 12

PAGE WRITE Timing (AT25HP512)

SCK

HOLD Timing

HOLD

0123456789101120212223242526

INSTRUCTION

HIGH IMPEDANCE

BYTE ADDRESS

1st BYTE DATA IN

SCK

10431044 1045 1046 1047

128

65432

BYTE DATA IN

AT25HP256/512

Page 13

AT25HP256 Ordering Information

tWC (max)

(ms)

TBD

ICC (max)

(µµµµA)

8000 7.0 10000

4000 3.0 5000

TBD TBD TBD

ISB (max)

(µµµµA)

MAX

(kHz) Ordering Code Package Operation Range

AT25HP256-10CC AT25HP256C1-10CC AT25HP256-10PC AT25HP256W-10SC

AT25HP256-10CI AT25HP256C1-10CI AT25HP256-10PI AT25HP256W-10SI

AT25HP256-10CC-2.7 AT25HP256C1-10CC-2.7 AT25HP256-10PC-2.7 AT25HP256W-10SC-2.7

AT25HP256-10CI-2.7 AT25HP256C1-10CI-2.7 AT25HP256-10PI-2.7 AT25HP256W-10SI-2.7

AT25HP256-10CC-1.8 AT25HP256C1-10CC-1.8 AT25HP256-10PC-1.8 AT25HP256W-10SC-1.8

AT25HP256-10CI-1.8 AT25HP256C1-10CI-1.8 AT25HP256-10PI-1.8 AT25HP256W-10SI-1.8

AT25HP256/512

8C 8C1 8P3 8S2

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

8C 8-Lead, 0.230" Wide, Leadless Array Package (LAP) 8C1 8-Lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S2 8-Lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

Options

Blank Standard Device (4.5V to 5.5V)

-2.7 Low Voltage (2.7V to 5.5V)

-1.8 Low Voltage (1.8V to 3.6V)

Page 14

AT25HP512 Ordering Information

tWC (max)

(ms)

TBD

ICC (max)

(µµµµA)

8000 7.0 10000

4000 3.0 5000

TBD TBD TBD

ISB (max)

(µµµµA)

MAX

(kHz) Ordering Code Package Operation Range

AT25HP512C1-10CC AT25HP512-10PC

AT25HP512C1-10CI AT25HP512-10PI

AT25HP512C1-10CC-2.7 AT25HP512-10PC-2.7

AT25HP512C1-10CI-2.7 AT25HP512-10PI-2.7

AT25HP512C1-10CC-1.8 AT25HP512-10PC-1.8

AT25HP512C1-10CI-1.8 AT25HP512-10PI-1.8

8C1 8P3

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

8C1 8-Lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)

Blank Standard Device (4.5V to 5.5V)

-2.7 Low Voltage (2.7V to 5.5V)

-1.8 Low Voltage (1.8V to 3.6V)

AT25HP256/512

Options

Page 15

Packaging Information

AT25HP256/512

, 8-Lead, 0.230" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters)

SIDE

5.15 (0.203)

4.85 (0.191)

1.27 (0.050) TYP

TOP VIEW

6.15 (0.242)

5.85 (0.230)

BOTTOM VIEW

0.64 (0.025) TYP

VIEW

0.41 (0.016) TYP

1.30 (0.051)

1.00 (0.039)

0.42 (0.017)

0.34 (0.013)

8C1

, 8-Lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters)

SIDE

5.15 (0.203)

4.85 (0.191)

1.27 (0.050) TYP

TOP VIEW

8.15 (0.321)

7.85 (0.309)

BOTTOM VIEW

0.64 (0.025) TYP

VIEW

0.41 (0.016) TYP

1.30 (0.051)

1.00 (0.039)

0.42 (0.017)

0.34 (0.013)

8P3

, 8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) Dimensions in Inches and (Millimeters)

JEDEC STA NDARD MS-001 BA

.400 (10.16) .355 (9.02)

.037 (.940)

.300 (7.62) REF

.210 (5.33) MAX

SEATING

PLANE

.150 (3.81) .115 (2.92)

.012 (.305) .008 (.203)

.070 (1.78) .045 (1.14)

.027 (.690)

.100 (2.54) BSC

.015 (.380) MIN

.022 (.559) .014 (.356)

.325 (8.26) .300 (7.62)

REF

.430 (10.9) MAX

.280 (7.11) .240 (6.10)

8S2

, 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters)

.020 (.508) .012 (.305)

PIN 1

0 8

.213 (5.41) .205 (5.21)

.050 (1.27) BSC

.212 (5.38) .203 (5.16)

.013 (.330) .004 (.102)

REF

.035 (.889) .020 (.508)

.330 (8.38) .300 (7.62)

.080 (2.03) .070 (1.78)

.010 (.254) .007 (.178)