Datasheet AT25128B, AT25256B Datasheet

AT25128B/AT25256B

SPI Serial EEPROM 128 Kbits (16,384 x 8)

and 256 Kbits (32,768 x 8)

Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1):

– Data sheet describes mode 0 operation

• Low-Voltage Operation:

– 1.8V (VCC = 1.8V to 5.5V)

• Industrial Temperature Range: -40°C to +85°C

• 20 MHz Clock Rate (5V)

• 64‑Byte Page Mode

• Block Write Protection:

– Protect 1/4, 1/2 or entire array

• Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data
Protection

• Self-Timed Write Cycle within 5 ms Maximum

• ESD Protection > 4,000V

• High Reliability:

– Endurance: 1,000,000 write cycles

– Data retention: 100 years

• Green (Lead-free/Halide-free/RoHS Compliant) Package Options

• Die Sale Options: Wafer Form and Bumped Wafers

Packages

• 8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN and 8-Ball VFBGA

© 2019 Microchip Technology Inc.

DS20006193A-page 1

AT25128B/AT25256B

Table of Contents

Features.......................................................................................................................... 1

Packages.........................................................................................................................1

1. Package Types (not to scale).................................................................................... 4

2. Pin Description.......................................................................................................... 5

2.1. Chip Select (CS)...........................................................................................................................5

2.2. Serial Data Output (SO)............................................................................................................... 5

2.3. Write-Protect (WP)....................................................................................................................... 5

2.4. Ground (GND).............................................................................................................................. 5

2.5. Serial Data Input (SI)....................................................................................................................6

2.6. Serial Data Clock (SCK)...............................................................................................................6

2.7. Suspend Serial Input (HOLD).......................................................................................................6

2.8. Device Power Supply (VCC)......................................................................................................... 6

3. Description.................................................................................................................7

3.1. SPI Bus Master Connections to Serial EEPROMs.......................................................................7

3.2. Block Diagram.............................................................................................................................. 8

4. Electrical Characteristics........................................................................................... 9

4.1. Absolute Maximum Ratings..........................................................................................................9

4.2. DC and AC Operating Range.......................................................................................................9

4.3. DC Characteristics....................................................................................................................... 9

4.4. AC Characteristics......................................................................................................................10

4.5. SPI Synchronous Data Timimg.................................................................................................. 13

4.6. Electrical Specifications..............................................................................................................13

5. Device Operation.....................................................................................................15

5.1. Interfacing the AT25128B/AT25256B on the SPI Bus................................................................ 15

5.2. Device Opcodes......................................................................................................................... 16

5.3. Hold Function............................................................................................................................. 16

5.4. Write Protection..........................................................................................................................17

6. Device Commands and Addressing........................................................................ 18

6.1. STATUS Register Bit Definition and Function............................................................................ 18

6.2.

Read STATUS Register (RDSR).................................................................................................19

6.3.

Write Enable (WREN) and Write Disable (WRDI)........................................................................19

6.4.

Write STATUS Register (WRSR).................................................................................................20

7. Read Sequence.......................................................................................................23

8. Write Sequence....................................................................................................... 24

8.1. Byte Write...................................................................................................................................24

8.2. Page Write..................................................................................................................................25

© 2019 Microchip Technology Inc.

DS20006193A-page 2

AT25128B/AT25256B

8.3. Polling Routine........................................................................................................................... 25

9. Packaging Information.............................................................................................27

9.1. Package Marking Information.....................................................................................................27

10. Revision History.......................................................................................................37

The Microchip Web Site................................................................................................ 38

Customer Change Notification Service..........................................................................38

Customer Support......................................................................................................... 38

Product Identification System........................................................................................39

Microchip Devices Code Protection Feature................................................................. 39

Legal Notice...................................................................................................................40

Trademarks................................................................................................................... 40

Quality Management System Certified by DNV.............................................................41

Worldwide Sales and Service........................................................................................42

© 2019 Microchip Technology Inc.

DS20006193A-page 3

1. Package Types (not to scale)

8-Lead SOIC/TSSOP

(Top View)

CS 1

2

3

4

8

7

6

5

SO

WP

GND

Vcc

HOLD

SCK

SI

CS

SO

WP

GND

Vcc

HOLD

SCK

SI

8-Pad UDFN

(Top View)

1

2

3

4 5

6

7

8

1

2

3

4

8

7

6

5

CS

SO

WP

GND

Vcc

HOLD

SCK

SI

8-Ball VFBGA

(Top View)

AT25128B/AT25256B

Package Types (not to scale)

© 2019 Microchip Technology Inc.

DS20006193A-page 4

2. Pin Description

The descriptions of the pins are listed in Table 2-1.

Table 2-1. Pin Function Table

Name 8-Lead SOIC 8-Lead TSSOP 8-Pad UDFN

CS 1 1 1 1 Chip Select

SO 2 2 2 2 Serial Data Output

(2)

WP

GND 4 4 4 4 Ground

SI 5 5 5 5 Serial Data Input

SCK 6 6 6 6 Serial Data Clock

(2)

HOLD

V

CC

Note: 

1. The exposed pad on this package can be connected to GND or left floating.

2. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.

3 3 3 3 Write-Protect

7 7 7 7 Suspends Serial Input

8 8 8 8 Device Power Supply

AT25128B/AT25256B

(1)

8-Ball VFBGA Function

Pin Description

2.1 Chip Select (CS)

The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will
remain in a high-impedance state.

To ensure robust operation, the CS pin should follow VCC upon power-up. It is therefore recommended to
connect CS to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on
CS is required prior to any sequence being initiated.

2.2 Serial Data Output (SO)

The Serial Data Output (SO) pin is used to transfer data out of the AT25128B/AT25256B. During a read
sequence, data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK).

2.3 Write-Protect (WP)

The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is
brought low and WPEN bit is set to a logic ‘1’, all write operations to the STATUS register are inhibited.
WP going low while CS is still low will interrupt a write operation to the STATUS register. If the internal
write cycle has already been initiated, WP going low will have no effect on any write operation to the
STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is set to a
logic ‘0’. This will allow the user to install the AT25128B/AT25256B in a system with the WP pin tied to
ground and still be able to write to the STATUS register. All WP pin functions are enabled when the
WPEN bit is set to a logic ‘1’.

2.4 Ground (GND)

The ground reference for the Device Power Supply (VCC). The Ground (GND) pin should be connected to
the system ground.

© 2019 Microchip Technology Inc.

DS20006193A-page 5

2.5 Serial Data Input (SI)

The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses
and data. Data is latched on the rising edge of the Serial Data Clock (SCK).

2.6 Serial Data Clock (SCK)

The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the
AT25128B/AT25256B. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched
in on the rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling
edge of SCK.

2.7 Suspend Serial Input (HOLD)

The Suspend Serial Input (HOLD) pin is used in conjunction with the Chip Select (CS) pin to pause the
AT25128B/AT25256B. When the device is selected and a serial sequence is underway, HOLD can be
used to pause the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the Serial Data Clock (SCK) pin is low. To resume serial
communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the Serial Data Input (SI) pin will be ignored while the Serial Data Output (SO) pin will
be in the high‑impedance state.

AT25128B/AT25256B

Pin Description

2.8 Device Power Supply (VCC)

The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at
invalid VCC voltages may produce spurious results and should not be attempted.

© 2019 Microchip Technology Inc.

DS20006193A-page 6

3. Description

SPI Master:

Microcontroller

Slave 0

AT25XXX

Data Clock (SCK)

Data Output (SO)

Data Input (SI)

CS3 CS2 CS1 CS0

SI SO SCK

CS

Slave 1

AT25XXX

SI SO SCK

Slave 2

AT25XXX

SI SO SCK

Slave 3

AT25XXX

SI SO SCK

CS

CSCS

The AT25128B/AT25256B provides 131,072/262,144 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 16,384/32,768 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where low‑power and
low‑voltage operation are essential. The device is available in space-saving 8‑lead SOIC, 8‑lead TSSOP,
8‑pad UDFN and 8‑ball VFBGA packages. All packages operate from 1.8V to 5.5V.

3.1 SPI Bus Master Connections to Serial EEPROMs

AT25128B/AT25256B

Description

© 2019 Microchip Technology Inc.

DS20006193A-page 7

3.2 Block Diagram

GND

Memory

System Control

Module

High-Voltage

Generation

Circuit

Address Register

and Counter

Write Protection

Control

VCC

SCK

SI

Power-on

Reset

Generator

Row Decoder

Data Register

SO

Pause

Operation

Control

Register Bank:

STATUS Register

Data Output

Buffer

CS

WP

HOLD

1 page

EEPROM Array

Column Decoder

AT25128B/AT25256B

Description

© 2019 Microchip Technology Inc.

DS20006193A-page 8

4. Electrical Characteristics

4.1 Absolute Maximum Ratings

Operating temperature -55°C to +125°C

Storage temperature -65°C to +150°C

Voltage on any pin with respect to ground -1.0V to +7.0V

AT25128B/AT25256B

Electrical Characteristics

V

CC

DC output current 5.0 mA

ESD protection > 4 kV

Note:  Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

4.2 DC and AC Operating Range

Table 4-1. DC and AC Operating Range

AT25128B/AT25256B

Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C

VCC Power Supply Low-Voltage Grade 1.8V to 5.5V

4.3 DC Characteristics

Table 4-2. DC Characteristics

(1)

6.25V

Parameter Symbol Minimum Typical Maximum Units Conditions

Supply Voltage V

Supply Voltage V

Supply Voltage V

Supply Current I

CC1

CC2

CC3

CC1

1.8 — 5.5 V

2.5 — 5.5 V

4.5 — 5.5 V

— 9.0 10.0 mA VCC = 5.0V at 20 MHz,

SO = Open, Read

Supply Current I

CC2

— 5.0 7.0 mA VCC = 5.0V at 10 MHz,

SO = Open, Read, Write

Supply Current I

CC3

— 2.2 3.5 mA VCC = 5.0V at 1 MHz,

SO = Open, Read, Write

Standby Current I

© 2019 Microchip Technology Inc.

SB1

— 0.2 3.0 µA VCC = 1.8V, CS = V

CC

DS20006193A-page 9

AT25128B/AT25256B

Electrical Characteristics

...........continued

Parameter Symbol Minimum Typical Maximum Units Conditions

Standby Current I

Standby Current I

Input Leakage I

Output Leakage I

Input

V

Low-Voltage

Input

V

High-Voltage

Output

V

Low-Voltage

Output

V

High-Voltage

Output

V

Low-Voltage

Output

V

High-Voltage

SB2

SB3

IL

OL

IL

IH

OL1

OH1

OL2

OH2

— 0.5 3.0 µA VCC = 2.5V, CS = V

— 2.0 5.0 µA VCC = 5.0V, CS = V

-3.0 — 3.0 µA VIN = 0V to V

CC

CC

CC

-3.0 — 3.0 µA VIN = 0V to VCC,
TAC = 0°C to +70°C

(2)

(2)

-1.0 — VCC x 0.3 V

VCC x 0.7 — VCC + 0.5 V

— — 0.4 V 3.6V ≤ VCC ≤ 5.5V IOL = 3.0 mA

VCC - 0.8 — — V 3.6V ≤ VCC ≤ 5.5V IOH = -1.6 mA

— — 0.2 V 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA

VCC - 0.2 — — V 1.8V ≤ VCC ≤ 3.6V IOH = -100 µA

Note: 

1. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.8V to 5.5V
(unless otherwise noted).

2. VIL min and VIH max are reference only and are not tested.

4.4 AC Characteristics

Table 4-3. AC Characteristics

Parameter Symbol Minimum Maximum Units Conditions

SCK Clock Frequency f

Input Rise Time t

(1)

SCK

RI

0 20 MHz VCC = 4.5V to 5.5V

0 10 MHz VCC = 2.5V to 5.5V

0 5 MHz VCC = 1.8V to 5.5V

— 2000 ns VCC = 4.5V to 5.5V

— 2000 ns VCC = 2.5V to 5.5V

— 2000 ns VCC = 1.8V to 5.5V

© 2019 Microchip Technology Inc.

DS20006193A-page 10

AT25128B/AT25256B

Electrical Characteristics

...........continued

Parameter Symbol Minimum Maximum Units Conditions

Input Fall Time t

SCK High Time t

SCK Low Time t

CS High Time t

CS Setup Time t

FI

WH

WL

CS

CSS

— 2000 ns VCC = 4.5V to 5.5V

— 2000 ns VCC = 2.5V to 5.5V

— 2000 ns VCC = 1.8V to 5.5V

20 — ns VCC = 4.5V to 5.5V

40 — ns VCC = 2.5V to 5.5V

80 — ns VCC = 1.8V to 5.5V

20 — ns VCC = 4.5V to 5.5V

40 — ns VCC = 2.5V to 5.5V

80 — ns VCC = 1.8V to 5.5V

100 — ns VCC = 4.5V to 5.5V

100 — ns VCC = 2.5V to 5.5V

200 — ns VCC = 1.8V to 5.5V

100 — ns VCC = 4.5V to 5.5V

100 — ns VCC = 2.5V to 5.5V

200 — ns VCC = 1.8V to 5.5V

CS Hold Time t

Data In Setup Time t

Data In Hold Time t

HOLD Setup Time t

HOLD Hold Time t

CSH

SU

H

HD

CD

100 — ns VCC = 4.5V to 5.5V

100 — ns VCC = 2.5V to 5.5V

200 — ns VCC = 1.8V to 5.5V

5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

© 2019 Microchip Technology Inc.

DS20006193A-page 11

AT25128B/AT25256B

Electrical Characteristics

...........continued

Parameter Symbol Minimum Maximum Units Conditions

Output Valid t

Output Hold Time t

HOLD to Output Low Z t

HOLD to Output High Z t

Output Disable Time t

V

HO

LZ

HZ

DIS

0 20 ns VCC = 4.5V to 5.5V

0 40 ns VCC = 2.5V to 5.5V

0 80 ns VCC = 1.8V to 5.5V

0 — ns VCC = 4.5V to 5.5V

0 — ns VCC = 2.5V to 5.5V

0 — ns VCC = 1.8V to 5.5V

0 25 ns VCC = 4.5V to 5.5V

0 50 ns VCC = 2.5V to 5.5V

0 100 ns VCC = 1.8V to 5.5V

— 25 ns VCC = 4.5V to 5.5V

— 50 ns VCC = 2.5V to 5.5V

— 100 ns VCC = 1.8V to 5.5V

— 25 ns VCC = 4.5V to 5.5V

— 50 ns VCC = 2.5V to 5.5V

— 100 ns VCC = 1.8V to 5.5V

Write Cycle Time t

WC

— 5 ms VCC = 4.5V to 5.5V

— 5 ms VCC = 2.5V to 5.5V

— 5 ms VCC = 1.8V to 5.5V

Note: 

1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).

© 2019 Microchip Technology Inc.

DS20006193A-page 12

4.5 SPI Synchronous Data Timimg

t

DIS

t

HO

t

CSH

t

CS

t

V

t

H

V

OH

V

OL

High

Impedance

Valid Data In

t

WH

V

IH

V

IH

V

IL

t

CSS

t

WL

SCK

SI

SO

CS

V

IL

V

IH

V

IL

t

SU

High

Impedance

AT25128B/AT25256B

Electrical Characteristics

4.6 Electrical Specifications

4.6.1 Power-Up Requirements and Reset Behavior

During a power-up sequence, the VCC supplied to the AT25128B/AT25256B should monotonically rise
from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.

4.6.1.1 Device Reset

To prevent inadvertent write operations or any other spurious events from occurring during a power-up
sequence, the AT25128B/AT25256B includes a Power-on Reset (POR) circuit. Upon power-up, the
device will not respond to any instructions until the VCC level crosses the internal voltage threshold (V
that brings the device out of Reset and into Standby mode.

The system designer must ensure the instructions are not sent to the device until the VCC supply has
reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is
greater than or equal to the minimum VCC level, the bus master must wait at least t
first instruction to the device. See Table 4-4 for the values associated with these power-up parameters.

(1)

Table 4-4. Power-Up Conditions

Symbol Parameter Min. Max. Units

t

PUP

V

POR

t

POFF

Note: 

Time required after VCC is stable before the device can accept instructions 100 － µs

Power-on Reset Threshold Voltage － 1.5 V

Minimum time at VCC = 0V between power cycles 0.03 － ms

1. These parameters are characterized but they are not 100% tested in production.

If an event occurs in the system where the VCC level supplied to the AT25128B/AT25256B drops below
the maximum V
first driving the VCC pin to GND in less than 1 ms, waiting at least the minimum t

POR

level specified, it is recommended that a full-power cycle sequence be performed by

performing a new power-up sequence in compliance with the requirements defined in this section.

© 2019 Microchip Technology Inc.

)

POR

before sending the

PUP

time and then

POFF

DS20006193A-page 13

4.6.2 Pin Capacitance

Table 4-5. Pin Capacitance

Symbol Test Condition Max. Units Conditions

AT25128B/AT25256B

Electrical Characteristics

(1,2)

C

OUT

C

IN

Output Capacitance (SO) 8 pF V

Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V

Note: 

1. This parameter is characterized but is not 100% tested in production.

2. Applicable over recommended operating range from: TA = 25°C, f
(unless otherwise noted).

4.6.3 EEPROM Cell Performance Characteristics

Table 4-6. EEPROM Cell Performance Characteristics

Operation Test Condition Min. Max. Units

Write Endurance

(1)

TA = 25°C, VCC = 3.3V,
Page Write mode

Data Retention

(1)

TA = 55°C 100 — Years

Note: 

1. Performance is determined through characterization and the qualification process.

4.6.4 Software Reset

The SPI interface of the AT25128B/AT25256B can be reset by toggling the CS input. If the CS line is
already in the active state, it must complete a transition from the inactive state (≥VIH) to the active state
(≤VIL) and then back to the inactive state (≥VIH) without sending clocks on the SCK line. Upon completion
of this sequence, the device will be ready to receive a new opcode on the SI line.

= 0V

OUT

= 1.0 MHz, VCC = 5.0V

SCK

1,000,000 — Write Cycles

4.6.5 Device Default State at Power-Up

The AT25128B/AT25256B default state upon power-up consists of:

• Standby Power mode

• A high-to-low-level transition on CS is required to enter active state

• Write Enable Latch (WEL) bit in the STATUS register = 0

• Ready/Busy bit in the STATUS register = 0, indicating the device is ready to accept a new command

• Device is not selected

• Not in Hold condition

• WPEN, BP1 and BP0 bits in the STATUS register are unchanged from their previous state due to the

fact that they are nonvolatile values

4.6.6 Device Default Condition

The AT25128B/AT25256B is shipped from Microchip to the customer with the EEPROM array set to an all
FFh data pattern (logic ‘1’ state). The Write-Protect Enable bit in the STATUS register is set to logic ‘0’
(the ability of the EEPROM array to write is dictated by the values of the Block Write‑Protect bits while the
STATUS register’s ability to write is controlled by the WEL bit). The Block Write Protection bits in the
STATUS register are set to logic ‘0’ (no write protection selected).

© 2019 Microchip Technology Inc.

DS20006193A-page 14

5. Device Operation

SO

SI

SCK

CS

MSB LSB

MSB LSB

Mode 0

Mode 3

Mode 0

Mode 3

The AT25128B/AT25256B is controlled by a set of instructions that are sent from a host controller,
commonly referred to as the SPI Master. The SPI Master communicates with the AT25128B/AT25256B
via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial
Data Input (SI), and Serial Data Output (SO).

The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI
bus. The AT25128B/AT25256B supports the two most common modes, SPI Modes 0 and 3. With SPI
Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the
inactive state (when the SPI Master is in Standby mode and not transferring any data). SPI Mode 0 is
defined as a low SCK while CS is not asserted (at VCC) and SPI Mode 3 has SCK high in the inactive
state. The SCK Idle state must match when the CS is deasserted both before and after the
communication sequence in SPI Mode 0 and 3. The figures in this document depict Mode 0 with a solid
line on SCK while CS is inactive and Mode 3 with a dotted line.

Figure 5-1. SPI Mode 0 and Mode 3

AT25128B/AT25256B

Device Operation

5.1 Interfacing the AT25128B/AT25256B on the SPI Bus

Communication to and from the AT25128B/AT25256B must be initiated by the SPI Master device, such
as a microcontroller. The SPI Master device must generate the serial clock for the AT25128B/AT25256B
on the Serial Data Clock (SCK) pin. The AT25128B/AT25256B always operates as a slave due to the fact
that the SCK is always an input.

5.1.1 Selecting the Device

The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Data Output (SO) pin
will remain in a high‑impedance state.

5.1.2 Sending Data to the Device

The AT25128B/AT25256B uses the SI pin to receive information. All instructions, addresses and data
input bytes are clocked into the device with the Most Significant bit (MSb) first. The SI pin samples on the
first rising edge of the SCK line after the CS has been asserted.

© 2019 Microchip Technology Inc.

DS20006193A-page 15

5.1.3 Receiving Data from the Device

Data output from the device is transmitted on the SO pin, with the MSb output first. The SO data is
latched on the first falling edge of SCK after the instruction has been clocked into the device, such as the
Read from Memory Array (READ) and Read STATUS Register (RDSR) instructions. See Read Sequence
for more details.

5.2 Device Opcodes

5.2.1 Serial Opcode

After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte
contains the opcode that defines the operation to be performed. Refer to Table 6-1 for a list of all opcodes
that the AT25128B/AT25256B will respond to.

5.2.2 Invalid Opcode

If an invalid opcode is received, no data will be shifted into AT25128B/AT25256B and the SO pin will
remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the
serial communication.

AT25128B/AT25256B

Device Operation

5.3 Hold Function

The Suspend Serial Input (HOLD) pin is used to pause the serial communication with the device without
having to stop or reset the clock sequence. The Hold mode, however, does not have an effect on the
internal write cycle. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the
operation and the write cycle will continue to completion.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by
asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse,
then the Hold mode will not be started until the beginning of the next SCK low pulse. The device will
remain in the Hold mode as long as the HOLD pin and CS pin are asserted.

While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the
SCK pin will be ignored. The Write-Protect (WP) pin, however, can still be asserted or deasserted while in
the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the
SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end
until the beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been
started will be aborted and the device will reset the WEL bit in the STATUS register back to the logic ‘0’
state.

© 2019 Microchip Technology Inc.

DS20006193A-page 16

Figure 5-2. Hold Mode

HOLD

SCK

CS

Hold HoldHold

HOLD

SO

SCK

CS

t

CD

t

CD

t

HD

t

HD

t

LZ

t

HZ

Figure 5-3. Hold Timing

AT25128B/AT25256B

Device Operation

5.4 Write Protection

The Write-Protect (WP) pin will allow normal read and write operations when held high. When the WP pin
is brought low and WPEN bit is a logic ‘1’, all write operations to the STATUS register are inhibited. The
WP pin going low while CS is still low will interrupt a Write STATUS Register (WRSR). If the internal write
cycle has already been initiated, WP going low will have no effect on any write operation to the STATUS
register. The WP pin function is blocked when the WPEN bit in the STATUS register is a logic ‘0’. This will
allow the user to install the AT25128B/AT25256B device in a system with the
still be able to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to
a logic ‘1’.

© 2019 Microchip Technology Inc.

WP pin tied to ground and

DS20006193A-page 17

6. Device Commands and Addressing

The AT25128B/AT25256B is designed to interface directly with the synchronous Serial Peripheral
Interface (SPI). The AT25128B/AT25256B utilizes an 8‑bit instruction register. The list of instructions and
their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with
the MSb first and start with a high‑to‑low CS transition.

Table 6-1. Instruction Set for the AT25128B/AT25256B

Instruction Name Instruction Format Operates On Operation Description

AT25128B/AT25256B

Device Commands and Addressing

WREN 0000 X110

WRDI 0000 X100

RDSR 0000 X101

WRSR 0000 X001

READ 0000 X011

WRITE 0000 X010

STATUS Register Set Write Enable Latch (WEL)

STATUS Register Reset Write Enable Latch (WEL)

STATUS Register Read STATUS Register

STATUS Register Write STATUS Register

Memory Array Read from Memory Array

Memory Array Write to Memory Array

6.1 STATUS Register Bit Definition and Function

The AT25128B/AT25256B includes an 8‑bit STATUS register. The STATUS register bits modulate various
features of the device as shown in Table 6-2 and Table 6-3. These bits can be changed by specific
instructions that are detailed in the following sections.

Table 6-2. STATUS Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEL RDY/BSY

Table 6-3. STATUS Register Bit Definition

Bit Name Type Description

7 WPEN Write-Protect Enable R/W

6:4 RFU Reserved for Future Use R

3:2 BP1

BP0

1 WEL Write Enable Latch R/W

© 2019 Microchip Technology Inc.

Block Write Protection R/W

0

See Table 6-5 (Factory Default)

1

See Table 6-5 (Factory Default)

0

Reads as zeros when the device is not in a write
cycle

1

Reads as ones when the device is in a write cycle

00

No array write protection (Factory Default)

01

Quarter array write protection (see Table 6-4)

10

Half array write protection (see Table 6-4)

11

Entire array write protection (see Table 6-4)

0

Device is not write enabled (Power-up Default)

1

Device is write enabled

DS20006193A-page 18

SO

SCK

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

STATUS Register Data Out

High-Impedance

SI

MSB

RDSR Opcode (05h)

0 0 0 0 0 1 0 1

MSB

D7 D6 D5 D4 D3 D2 D1 D0

AT25128B/AT25256B

Device Commands and Addressing

...........continued

Bit Name Type Description

0 RDY/BSY Ready/Busy Status R

6.2 Read STATUS Register (RDSR)

The Read STATUS Register (RDSR) instruction provides access to the STATUS register. The ready/busy
and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block
Write Protection (BP<1:0>) bits indicate the extent of memory array protection employed. The STATUS
register is read by asserting the
completion of the opcode, the device will return the 8‑bit STATUS register value on the SO pin.

Figure 6-1. RDSR Waveform

CS pin, followed by sending in a 05h opcode on the SI pin. Upon

0

Device is ready for a new sequence

1

Device is busy with an internal operation

6.3 Write Enable (WREN) and Write Disable (WRDI)

Enabling and disabling writing to the STATUS register and EEPROM array is accomplished through the
Write Enable (WREN) instruction and the Write Disable (WRDI) instruction. These functions change the
status of the WEL bit in the STATUS register.

6.3.1 Write Enable Instruction (WREN)

The Write Enable Latch (WEL) bit of the STATUS register must be set to a logic ‘1’ prior to each Write
STATUS Register (WRSR) and Write to Memory Array (WRITE) instructions. This is accomplished by
sending a WREN (06h) instruction to the AT25128B/AT25256B. First, the
device and then a WREN instruction is clocked in on the SI pin. Then the CS pin can be driven high and
the WEL bit will be updated in the STATUS register to a logic ‘1’. The device will power‑up in the write
disable state (WEL = 0).

© 2019 Microchip Technology Inc.

CS pin is driven low to select the

DS20006193A-page 19

Figure 6-2. WREN Timing

SO

SCK

CS

High-Impedance

SI

MSB

WREN Opcode (06h)

0 0 0 0 0 1 1 0

0 1 2 3 4 5 6 7

SO

SCK

CS

High-Impedance

SI

MSB

WRDI Opcode (04h)

0 0 0 0 0 1 0 0

0 1 2 3 4 5 6 7

6.3.2 Write Disable Instruction (WRDI)

To protect the device against inadvertent writes, the Write Disable (WRDI) instruction (opcode 04h)
disables all programming modes by setting the WEL bit to a logic ‘0’. The WRDI instruction is independent
of the status of the WP pin.

Figure 6-3. WRDI Timing

AT25128B/AT25256B

Device Commands and Addressing

6.4 Write STATUS Register (WRSR)

The Write STATUS Register (WRSR) instruction enables the SPI Master to change selected bits of the
STATUS register. Before a WRSR instruction can be initiated, a WREN instruction must be executed to set
the WEL to logic ‘1’. Upon completion of a WREN instruction, a WRSR instruction can be executed.
Note:  The WRSR instruction has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS register. Only
bit 7, bit 3 and bit 2 can be changed via the WRSR instruction. These modifiable bits are the Write Protect
Enable (WPEN) and Block Protect (BP<1:0>) bits. These three bits are nonvolatile bits that have the
same properties and functions as regular EEPROM cells. Their values are retained while power is
removed from the device.

© 2019 Microchip Technology Inc.

DS20006193A-page 20

SCK

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

STATUS Register Data In

High-Impedance

MSB

WRSR Opcode (01h)

0 0 0 0 0 0 0 1

MSB

D7 X X X D3 D2 X

X

SO

SI

t

WC

(1)

AT25128B/AT25256B

Device Commands and Addressing

The AT25128B/AT25256B will not respond to commands other than a RDSR after a WRSR instruction until
the self-timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the
STATUS register is reset to logic ‘0’.

Figure 6-4. WRSR Waveform

Note: 

1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.

6.4.1 Block Write-Protect Function

The WRSR instruction allows the user to select one of four possible combinations as to how the memory
array will be inhibited from writing through changing the Block Write-Protect bits (BP<1:0>). The four
levels of array protection are:

• None of the memory array is protected.

• Upper quarter (¼) address range is write-protected meaning the highest order address bits are read-

only.

• Upper half (½) address range is write-protected meaning the highest order address bits are read-

only.

• All of the memory array is write-protected meaning all address bits are read-only.

The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4.

Table 6-4. Block Write-Protect Bits

Level STATUS Register Bits Write-Protected/Read‑Only Address Range

BP1 BP0 AT25128B AT25256B

0

1(1/4)

2(1/2)

3(All)

0 0

0 1

1 0

1 1

None None

3000h-3FFFh 6000h-7FFFh

2000h-3FFFh 4000h – 7FFFh

0000h-3FFFh 0000h – 7FFFh

© 2019 Microchip Technology Inc.

DS20006193A-page 21

6.4.2 Write-Protect Enable Function

The WRSR instruction also allows the user to enable or disable the Write-Protect (WP) pin through the use
of the Write-Protect Enable (WPEN) bit. When the WPEN bit is set to logic ‘0’, the ability to write the
EEPROM array is dictated by the values of the Block Write-Protect (BP<1:0>) bits. The ability to write the
STATUS register is controlled by the WEL bit. When the WPEN bit is set to logic ‘1’, the STATUS register
is read-only.

AT25128B/AT25256B

Device Commands and Addressing

Hardware Write Protection is enabled when both the
logic ‘1’. When the device is Hardware Write‑Protected, writes to the STATUS register, including the Block
Write‑Protect , WEL and WPEN bits, and to the sections in the memory array selected by the Block
Write‑Protect bits are disabled. When Hardware Write Protection is enabled, writes are only allowed to
sections of the memory that are not block‑protected.

Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is a logic ‘0’. When
Hardware Write Protection is disabled, writes are only allowed to sections of the memory that are not
block‑protected. Refer to Table 6-5 for additional information.
Note:  When the WPEN bit is Hardware Write‑Protected, it cannot be set back to a logic ‘0’ as long as

WP pin is held low.

the

Table 6-5. WPEN Operation

WPEN WP

Pin

0 x 0

0 x 1

1

1

x

Low

Low

High

WEL Protected Blocks Unprotected Blocks STATUS Register

Protected Protected Protected

Protected Writable Writable

0

1

0

Protected Protected Protected

Protected Writable Protected

Protected Protected Protected

WP pin is low and the WPEN bit has been set to a

x

High

1

Protected Writable Writable

© 2019 Microchip Technology Inc.

DS20006193A-page 22

7. Read Sequence

SO

SI

SCK

MSB MSB

2 310

0 0 0 0 0 0 1 1

6 754 10 1198 12 27 2823 26252421 2219 20 29 30 31

READ Opcode (03h)

A A A A A A AA A

MSB MSB

D D D D D D D DDD

Address Bits A15-A0

Data Byte 1

High-Impedance

CS

Reading the AT25128B/AT25256B via the SO pin requires the following sequence. After the CS line is
pulled low to select a device, the READ (03h) instruction is transmitted via the SI line followed by the
16‑bit address to be read. Refer to Table 7-1 for the address bits for AT25128B/AT25256B.

Table 7-1. AT25128B/AT25256B Address Bits

Address AT25128B AT25256B

AT25128B/AT25256B

Read Sequence

A

N

Don’t Care Bits A15–A

A13–A

14

0

A14–A

A

15

0

Upon completion of the 16‑bit address, any data on the SI line will be ignored. The data (D7‑D0) at the
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest‑order address bit is
reached, the address counter will rollover to the lowest‑order address bit allowing the entire memory to be
read in one continuous read cycle regardless of the starting address.

Figure 7-1. Read Waveform

© 2019 Microchip Technology Inc.

DS20006193A-page 23

8. Write Sequence

SO

SI

SCK

CS

MSB MSB

2 310

0 0 0 0 0 0 1 0

6 754 10 1198 12 3129 3025 28272623 2421 22

WRITE Opcode (02h)

High-Impedance

A A A A A A AA A

MSB

D7 D6 D5 D4 D3 D2 D1 D0

Address Bits A15-A0 Data In

t

WC

(1)

In order to program the AT25128B/AT25256B, two separate instructions must be executed. First, the
device must be write enabled via the Write Enable (WREN) instruction. Then, one of the two possible write
sequences described in this section may be executed.
Note:  If the device is not Write Enabled (WREN), the device will ignore the WRITE instruction and will
return to the standby state when CS is brought high. A new CS assertion is required to re‑initiate
communication.

The address of the memory location(s) to be programmed must be outside the protected address field
location selected by the block write protection level. During an internal write cycle, all commands will be
ignored except the RDSR instruction. Refer to Table 8-1 for the address bits for AT25128B/AT25256B.

Table 8-1. AT25128B/AT25256B Address Bits

Address AT25128B AT25256B

AT25128B/AT25256B

Write Sequence

Don’t Care Bits A15–A

8.1 Byte Write

A Byte Write requires the following sequence and is depicted in Figure 8-1. After the CS line is pulled low
to select the device, the WRITE (02h) instruction is transmitted via the SI line followed by the 16‑bit
address and the data (D7‑D0) to be programmed. Programming will start after the CS pin is brought high.
The low‑to‑high transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time
(Mode 3) immediately after clocking in the D0 (LSB) data bit. The AT25128B/AT25256B is automatically
returned to the Write Disable state (STATUS register bit WEL = 0) at the completion of a write cycle.

Figure 8-1. Byte Write

A

N

A13–A

14

0

A14–A

A

15

0

Note: 

1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.

© 2019 Microchip Technology Inc.

DS20006193A-page 24

8.2 Page Write

SO

SI

SCK

MSB MSB

2 310

0 0 0 0 0 0 1 0

6 754 98 3129 3025 28272623 2421 22

WRITE Opcode (02h)

High-Impedance

A A A A AA

MSB

D D D D D D D D

Address Bits A15-A0 Data In Byte 1

MSB

D D D D D D D D

Data In Byte 64

CS

t

WC

(1)

A Page Write sequence allows up to 64 bytes to be written in the same write cycle, provided that all bytes
are in the same row of the memory array. Partial Page Writes of less than 64 bytes are allowed. After
each byte of data is received, the six lowest order address bits are internally incremented following the
receipt of each data byte. The higher order address bits are not incremented and retain the memory array
page location. If more bytes of data are transmitted that what will fit to the end of that memory row, the
address counter will rollover to the beginning of the same row. Nevertheless, creating a rollover event
should be avoided as previously loaded data in the page could become unintentionally altered. The
AT25128B/AT25256B is automatically returned to the Write Disable state (WEL = 0) at the completion of
a write cycle.

Figure 8-2. Page Write

AT25128B/AT25256B

Write Sequence

Note: 

1. This instruction initiates a self‑timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.

8.3 Polling Routine

A polling routine can be implemented to optimize time‑sensitive applications that would not prefer to wait
the fixed maximum write cycle time (tWC). This method allows the application to know immediately when
the write cycle has completed to start a subsequent operation.

Once the internally-timed write cycle has started, a polling routine can be initiated. This involves
repeatedly sending Read STATUS Register (RDSR) instruction to determine if the device has completed
its self-timed internal write cycle. If the RDY/BSY bit (bit 0 of STATUS register) = 1, the write cycle is still
in progress. If bit 0 = 0, the write cycle has ended. If the RDY/BSY bit = 1, repeated RDSR commands can
be executed until the RDY/BSY bit = 0, signaling that the device is ready to execute a new instruction.
Only the Read STATUS Register (RDSR) instruction is enabled during the write cycle.

© 2019 Microchip Technology Inc.

DS20006193A-page 25

Figure 8-3. Polling Flowchart

Send Valid

Write

Protocol

Deassert

CS to V

CC

to

Initiate a

Write Cycle

Send RDSR

Instruction

to the Device

Continue to

Next Operation

NO

YES

Does

RDY/BSY

= 0?

AT25128B/AT25256B

Write Sequence

© 2019 Microchip Technology Inc.

DS20006193A-page 26

9. Packaging Information

AT25128B and AT25256B: Package Marking Information

Catalog Number Truncation

AT25128B Truncation Code ###: 5DB

AT25256B Truncation Code ###: 5EB

Date Codes Voltages

YY = Year Y = Year WW = Work Week of Assembly % = Minimum Voltage
16: 2016 20: 2020 6: 2016 0: 2020 02: Week 2 L: 1.8V min
17: 2017 21: 2021 7: 2017 1: 2021 04: Week 4
18: 2018 22: 2022 8: 2018 2: 2022 ...
19: 2019 23: 2023 9: 2019 3: 2023 52: Week 52

Country of Origin Device Grade Atmel Truncation

CO = Country of Origin H or U: Industrial Grade AT: Atmel
ATM: Atmel
ATML: Atmel

Lot Number or Trace Code

NNN = Alphanumeric Trace Code (2 Characters for Small Packages)

8-Lead SOIC

YYWWNNN

###% CO

ATMLHYWW

8-Lead TSSOP

YYWWNNN

###%CO

ATHYWW

8-Pad UDFN

###
H%
NNN

2.0 x 3.0 mm Body

2.35 x 3.73 mm Body

8-Ball VFBGA

Note 2: Package drawings are not to scale

Note 1: designates pin 1

###U
WWNNN

9.1 Package Marking Information

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 27

0.25 C A–B D

C

SEATING

PLANE

TOP VIEW

SIDE VIEW

VIEW A–A

0.10

C

0.10

C

Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2

8X

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

R

1

2

N

h

h

A1

A2

A

A

B

e

D

E

E

2

E1

2

E1

NOTE 5

NOTE 5

NX b

0.10

C A–B

2X

H 0.23

(L1)

L

R0.13

R0.13

VIEW C

SEE VIEW C

NOTE 1

D

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 28

Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

R

Foot Angle 0° - 8°

15°-5°

Mold Draft Angle Bottom

15°-5°

Mold Draft Angle Top

0.51-0.31

b

Lead Width

0.25-0.17

c

Lead Thickness

1.27-0.40LFoot Length

0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10

A1

Standoff

--1.25A2Molded Package Thickness

1.75--AOverall Height

1.27 BSC

e

Pitch

8NNumber of Pins

MAXNOMMINDimension Limits

MILLIMETERSUnits

protrusions shall not exceed 0.15mm per side.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

4. Dimensioning and tolerancing per ASME Y14.5M

Notes:

§

Footprint

L1 1.04 REF

5. Datums A & B to be determined at Datum H.

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 29

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2057-SN Rev E

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

R

Dimension Limits

Units

CContact Pad Spacing

Contact Pitch

MILLIMETERS

1.27 BSC

MIN

E

MAX

5.40

Contact Pad Length (X8)

Contact Pad Width (X8)

Y1

X1

1.55

0.60

NOM

E

X1

C

Y1

SILK SCREEN

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 30

M

Packaging Diagrams and Parameters

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle

φ 0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

D

N

E

E1

NOTE 1

1 2

b

e

c

A

A1

A2

L1

L

φ

Microchip Technology Drawing C04-086B

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 31

M

Packaging Diagrams and Parameters

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 32

B

A

0.10 C

0.10 C

(DATUM B)

(DATUM A)

C

SEATING

PLANE

12

N

2X

TOP VIEW

SIDE VIEW

NOTE 1

12

N

0.10 C A B

0.10 C A B

0.10

C

0.08 C

Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2

2X

8X

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package

D

E

D2

E2

K

L

8X b

e

e
2

0.10 C A B

0.05 C

A

(A3)

A1

BOTTOM VIEW

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 33

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1.

2.

3.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated

Dimensioning and tolerancing per AS ME Y14.5M

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Terminal Width

Overall Width

Terminal Length

Exposed Pad Width

Terminal Thickness

Pitch

Standoff

Units

Dimension Limits

A1

A

b

E2

A3

e

L

E

N

0.50 BSC

0.152 REF

1.20

0.35

0.18

0.50

0.00

0.25

0.40

1.30

0.55

0.02

3.00 BSC

MILLIMETERS

MIN

NOM

8

1.40

0.45

0.30

0.60

0.05

MAX

K-0.20 -Terminal-to-Exposed-Pad

Overall Length
Exposed Pad Length

D

D2 1.40

2.00 BSC

1.50 1.60

Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 34

RECOMMENDED LAND PATTERN

Dimension Limits

Units

Optional Center Pad Width
Optional Center Pad Length

Contact Pitch

Y2

X2

1.40

1.60

MILLIMETERS

0.50 BSC

MIN

E

MAX

Contact Pad Length (X8)

Contact Pad Width (X8)

Y1

X1

0.85

0.30

NOM

12

8

CContact Pad Spacing 2.90

Contact Pad to Center Pad (X8) G1 0 .20

Thermal Via Diameter V
Thermal Via Pitch EV

0.30

1.00

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled or ten t e d to avoid solder loss during
reflow process

1.

2.

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

Microchip Technology Drawing C04-21355-Q4B Rev A

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package

X2

Y2

Y1

SILK SCREEN

X1

E

C

EV

G2

G1

ØV

Contact Pad to Contact Pad (X6) G2 0.33

AT25128B/AT25256B

Packaging Information

© 2019 Microchip Technology Inc.

DS20006193A-page 35

DRAWING NO. REV. TITLE GPC

8U2-1 G

6/11/13

8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package
(VFBGA)

GWW

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

A 0.81 0.91 1.00
A1 0.15 0.20 0.25
A2 0.40 0.45 0.50
b 0.25 0.30 0.35
D 2.35 BSC
E 3.73 BSC
e 0.75 BSC
e1 0.74 REF
d 0.75 BSC
d1 0.80 REF

2. Dimension 'b' is measured at the maximum solder ball diameter.

1. This drawing is for general

3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.

Notes:

A

d 0.08 C

C

f 0.10 C

A1

A2

Øb

j n 0.15 m C A B
j

n 0.08 m C

A

(4X)

d 0.10

B

A1 BALL
PAD
CORNER

D

E

SIDE VIEW

TOP VIEW

e

(e1)

d

2 1

D

C

B

A

A1 BALL PAD CORNER

(d1)

8 SOLDER BALLS

BOTTOM VIEW

AT25128B/AT25256B

Packaging Information

Note:  For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging.

© 2019 Microchip Technology Inc.

DS20006193A-page 36

10. Revision History

Revision A (May 2019)

Updated to the Microchip template. Microchip DS20006193 replaces Atmel document 8698. Updated Part
Marking Information. Added ESD rating. Removed lead finish designation. Added POR recommendations
section. Updated trace code format in package markings. Updated section content throughout for
clarification. Updated the SOIC, TSSOP, and UDFN package drawings to the Microchip equivalents.

Atmel Document 8698 Revision E (January 2015)

Added the UDFN Expanded Quantity Option and ordering information. Updated the 8MA2 package
outline drawing.

Atmel Document 8698 Revision D (July 2014)

Updated part markings, 8MA2 and 8U2-1 package drawings, package 8A2 to 8X, template, logos, and
disclaimer page. No change to functional specification.

Atmel Document 8698 Revision C (August 2011)

Updated 8A2 and 8S1 package drawings. Corrected page 13, Device Density from 156K to 256K.
Corrected page 9, table headings. Corrected cross references on pages 7, 8, and 9.

AT25128B/AT25256B

Revision History

Atmel Document 8698 Revision B (March 2010)

Updated Catalog Numbering Scheme. Updated Ordering Information and package types.

Atmel Document 8698 Revision A (December 2009)

Initial document release.

© 2019 Microchip Technology Inc.

DS20006193A-page 37

AT25128B/AT25256B

The Microchip Web Site

Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as
a means to make files and information easily available to customers. Accessible by using your favorite
Internet browser, the web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support documents, latest software releases and archived
software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online
discussion groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory
representatives

Customer Change Notification Service

Microchip’s customer notification service helps keep customers current on Microchip products.
Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata
related to a specified product family or development tool of interest.

To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on
“Customer Change Notification” and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included
in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

© 2019 Microchip Technology Inc.

DS20006193A-page 38

Product Family

25 = Standard SPI

Serial EEPROM

Device Density

Shipping Carrier Option

Device Grade or
Wafer/Die Thickness

Package Option

128 = 128-Kilobit
256 = 256-Kilobit

B = Bulk (Tubes)
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Extended Quantity Option

Operating Voltage

L = 1.8V to 5.5V

H or U = Industrial Temperature Range

(-40°C to +85°C)

11

= 11mil Wafer Thickness

SS = SOIC
X = TSSOP
MA = 2.0mm x 3.0mm UDFN

C = VFBGA
WWU = Wafer Unsawn
WDT = Die in Tape and Reel

AT25128B-SSHL-B

Device Revision

AT25128B/AT25256B

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

Device Package Package

Drawing

Package

Option

Shipping Carrier

Option

Device Grade

Code

AT25128B‑SSHL‑B SOIC SN SS Bulk (Tubes) Industrial

AT25128B‑SSHL‑T SOIC SN SS Tape and Reel

Temperature

(-40°C to 85°C)

AT25256B‑SSHL‑T SOIC SN SS Tape and Reel

AT25128B‑XHL‑B TSSOP ST X Bulk (Tubes)

AT25256B‑XHL‑T TSSOP ST X Tape and Reel

AT25128B‑MAHL‑E UDFN Q4B MA Tape and Reel

AT25256B‑MAHL‑T UDFN Q4B MA Tape and Reel

AT25256B‑MAHL‑E UDFN Q4B MA Tape and Reel

AT25256B‑CUL‑T VFBGA 8U2-1 C Tape and Reel

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

© 2019 Microchip Technology Inc.

DS20006193A-page 39

AT25128B/AT25256B

• Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the
operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the
code protection features of our products. Attempts to break Microchip’s code protection feature may be a
violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software
or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for
your convenience and may be superseded by updates. It is your responsibility to ensure that your
application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS
CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life
support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud,
chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST,
SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight
Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming,
ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total

© 2019 Microchip Technology Inc.

DS20006193A-page 40

AT25128B/AT25256B

Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

©

2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-5224-4457-2

Quality Management System Certified by DNV

ISO/TS 16949

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer
fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC
DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design and manufacture of development
systems is ISO 9001:2000 certified.

®

© 2019 Microchip Technology Inc.

DS20006193A-page 41

Worldwide Sales and Service

AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: [phone]

Fax: [phone]

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: [phone]

Fax: [phone]

Austin, TX

Tel: [phone]

Boston

Westborough, MA

Tel: [phone]

Fax: [phone]

Chicago

Itasca, IL

Tel: [phone]

Fax: [phone]

Dallas

Addison, TX

Tel: [phone]

Fax: [phone]

Detroit

Novi, MI

Tel: [phone]

Houston, TX

Tel: [phone]

Indianapolis

Noblesville, IN

Tel: [phone]

Fax: [phone]

Tel: [phone]

Los Angeles

Mission Viejo, CA

Tel: [phone]

Fax: [phone]

Tel: [phone]

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Tel: [phone]

New York, NY

Tel: [phone]

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Tel: [phone]

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Canada - Toronto

Tel: [phone]

Fax: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

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Tel: [phone]

India - Bangalore

Tel: [phone]

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Tel: [phone]

India - Pune

Tel: [phone]

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Tel: [phone]

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Tel: [phone]

Korea - Daegu

Tel: [phone]

Korea - Seoul

Tel: [phone]

Malaysia - Kuala Lumpur

Tel: [phone]

Malaysia - Penang

Tel: [phone]

Philippines - Manila

Tel: [phone]

Singapore

Tel: [phone]

Taiwan - Hsin Chu

Tel: [phone]

Taiwan - Kaohsiung

Tel: [phone]

Taiwan - Taipei

Tel: [phone]

Thailand - Bangkok

Tel: [phone]

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Tel: [phone]

Austria - Wels

Tel: [phone]

Fax: [phone]

Denmark - Copenhagen

Tel: [phone]

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Finland - Espoo

Tel: [phone]

France - Paris

Tel: [phone]

Fax: [phone]

Germany - Garching

Tel: [phone]

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Tel: [phone]

Germany - Heilbronn

Tel: [phone]

Germany - Karlsruhe

Tel: [phone]

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Tel: [phone]

Fax: [phone]

Germany - Rosenheim

Tel: [phone]

Israel - Ra’anana

Tel: [phone]

Italy - Milan

Tel: [phone]

Fax: [phone]

Italy - Padova

Tel: [phone]

Netherlands - Drunen

Tel: [phone]

Fax: [phone]

Norway - Trondheim

Tel: [phone]

Poland - Warsaw

Tel: [phone]

Romania - Bucharest

Tel: [phone]

Spain - Madrid

Tel: [phone]

Fax: [phone]

Sweden - Gothenberg

Tel: [phone]

Sweden - Stockholm

Tel: [phone]

UK - Wokingham

Tel: [phone]

Fax: [phone]

© 2019 Microchip Technology Inc.

DS20006193A-page 42