Datasheet AT25128B, AT25256B Datasheet
AT25128B/AT25256B
SPI Serial EEPROM 128 Kbits (16,384 x 8)
and 256 Kbits (32,768 x 8)
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1):
– Data sheet describes mode 0 operation
• Low-Voltage Operation:
– 1.8V (VCC = 1.8V to 5.5V)
• Industrial Temperature Range: -40°C to +85°C
• 20 MHz Clock Rate (5V)
• 64‑Byte Page Mode
• Block Write Protection:
– Protect 1/4, 1/2 or entire array
• Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data
Protection
• Self-Timed Write Cycle within 5 ms Maximum
• ESD Protection > 4,000V
• High Reliability:
– Endurance: 1,000,000 write cycles
– Data retention: 100 years
• Green (Lead-free/Halide-free/RoHS Compliant) Package Options
• Die Sale Options: Wafer Form and Bumped Wafers
Packages
• 8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN and 8-Ball VFBGA
© 2019 Microchip Technology Inc.
DS20006193A-page 1
AT25128B/AT25256B
Table of Contents
Features.......................................................................................................................... 1
Packages.........................................................................................................................1
1. Package Types (not to scale).................................................................................... 4
2. Pin Description.......................................................................................................... 5
2.1. Chip Select (CS)...........................................................................................................................5
2.2. Serial Data Output (SO)............................................................................................................... 5
2.3. Write-Protect (WP)....................................................................................................................... 5
2.4. Ground (GND).............................................................................................................................. 5
2.5. Serial Data Input (SI)....................................................................................................................6
2.6. Serial Data Clock (SCK)...............................................................................................................6
2.7. Suspend Serial Input (HOLD).......................................................................................................6
2.8. Device Power Supply (VCC)......................................................................................................... 6
3. Description.................................................................................................................7
3.1. SPI Bus Master Connections to Serial EEPROMs.......................................................................7
3.2. Block Diagram.............................................................................................................................. 8
4. Electrical Characteristics........................................................................................... 9
4.1. Absolute Maximum Ratings..........................................................................................................9
4.2. DC and AC Operating Range.......................................................................................................9
4.3. DC Characteristics....................................................................................................................... 9
4.4. AC Characteristics......................................................................................................................10
4.5. SPI Synchronous Data Timimg.................................................................................................. 13
4.6. Electrical Specifications..............................................................................................................13
5. Device Operation.....................................................................................................15
5.1. Interfacing the AT25128B/AT25256B on the SPI Bus................................................................ 15
5.2. Device Opcodes......................................................................................................................... 16
5.3. Hold Function............................................................................................................................. 16
5.4. Write Protection..........................................................................................................................17
6. Device Commands and Addressing........................................................................ 18
6.1. STATUS Register Bit Definition and Function............................................................................ 18
6.2.
Read STATUS Register (RDSR).................................................................................................19
6.3.
Write Enable (WREN) and Write Disable (WRDI)........................................................................19
6.4.
Write STATUS Register (WRSR).................................................................................................20
7. Read Sequence.......................................................................................................23
8. Write Sequence....................................................................................................... 24
8.1. Byte Write...................................................................................................................................24
8.2. Page Write..................................................................................................................................25
© 2019 Microchip Technology Inc.
DS20006193A-page 2
AT25128B/AT25256B
8.3. Polling Routine........................................................................................................................... 25
9. Packaging Information.............................................................................................27
9.1. Package Marking Information.....................................................................................................27
10. Revision History.......................................................................................................37
The Microchip Web Site................................................................................................ 38
Customer Change Notification Service..........................................................................38
Customer Support......................................................................................................... 38
Product Identification System........................................................................................39
Microchip Devices Code Protection Feature................................................................. 39
Legal Notice...................................................................................................................40
Trademarks................................................................................................................... 40
Quality Management System Certified by DNV.............................................................41
Worldwide Sales and Service........................................................................................42
© 2019 Microchip Technology Inc.
DS20006193A-page 3
1. Package Types (not to scale)
8-Lead SOIC/TSSOP
(Top View)
CS 1
2
3
4
8
7
6
5
SO
WP
GND
Vcc
HOLD
SCK
SI
CS
SO
WP
GND
Vcc
HOLD
SCK
SI
8-Pad UDFN
(Top View)
1
2
3
4 5
6
7
8
1
2
3
4
8
7
6
5
CS
SO
WP
GND
Vcc
HOLD
SCK
SI
8-Ball VFBGA
(Top View)
AT25128B/AT25256B
Package Types (not to scale)
© 2019 Microchip Technology Inc.
DS20006193A-page 4
2. Pin Description
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name 8-Lead SOIC 8-Lead TSSOP 8-Pad UDFN
CS 1 1 1 1 Chip Select
SO 2 2 2 2 Serial Data Output
(2)
WP
GND 4 4 4 4 Ground
SI 5 5 5 5 Serial Data Input
SCK 6 6 6 6 Serial Data Clock
(2)
HOLD
V
CC
Note:
1. The exposed pad on this package can be connected to GND or left floating.
2. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.
3 3 3 3 Write-Protect
7 7 7 7 Suspends Serial Input
8 8 8 8 Device Power Supply
AT25128B/AT25256B
(1)
8-Ball VFBGA Function
Pin Description
2.1 Chip Select (CS)
The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will
remain in a high-impedance state.
To ensure robust operation, the CS pin should follow VCC upon power-up. It is therefore recommended to
connect CS to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on
CS is required prior to any sequence being initiated.
2.2 Serial Data Output (SO)
The Serial Data Output (SO) pin is used to transfer data out of the AT25128B/AT25256B. During a read
sequence, data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK).
2.3 Write-Protect (WP)
The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is
brought low and WPEN bit is set to a logic ‘1’, all write operations to the STATUS register are inhibited.
WP going low while CS is still low will interrupt a write operation to the STATUS register. If the internal
write cycle has already been initiated, WP going low will have no effect on any write operation to the
STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is set to a
logic ‘0’. This will allow the user to install the AT25128B/AT25256B in a system with the WP pin tied to
ground and still be able to write to the STATUS register. All WP pin functions are enabled when the
WPEN bit is set to a logic ‘1’.
2.4 Ground (GND)
The ground reference for the Device Power Supply (VCC). The Ground (GND) pin should be connected to
the system ground.
© 2019 Microchip Technology Inc.
DS20006193A-page 5
2.5 Serial Data Input (SI)
The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses
and data. Data is latched on the rising edge of the Serial Data Clock (SCK).
2.6 Serial Data Clock (SCK)
The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the
AT25128B/AT25256B. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched
in on the rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling
edge of SCK.
2.7 Suspend Serial Input (HOLD)
The Suspend Serial Input (HOLD) pin is used in conjunction with the Chip Select (CS) pin to pause the
AT25128B/AT25256B. When the device is selected and a serial sequence is underway, HOLD can be
used to pause the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the Serial Data Clock (SCK) pin is low. To resume serial
communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the Serial Data Input (SI) pin will be ignored while the Serial Data Output (SO) pin will
be in the high‑impedance state.
AT25128B/AT25256B
Pin Description
2.8 Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at
invalid VCC voltages may produce spurious results and should not be attempted.
© 2019 Microchip Technology Inc.
DS20006193A-page 6
3. Description
SPI Master:
Microcontroller
Slave 0
AT25XXX
Data Clock (SCK)
Data Output (SO)
Data Input (SI)
CS3 CS2 CS1 CS0
SI SO SCK
CS
Slave 1
AT25XXX
SI SO SCK
Slave 2
AT25XXX
SI SO SCK
Slave 3
AT25XXX
SI SO SCK
CS
CSCS
The AT25128B/AT25256B provides 131,072/262,144 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 16,384/32,768 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where low‑power and
low‑voltage operation are essential. The device is available in space-saving 8‑lead SOIC, 8‑lead TSSOP,
8‑pad UDFN and 8‑ball VFBGA packages. All packages operate from 1.8V to 5.5V.
3.1 SPI Bus Master Connections to Serial EEPROMs
AT25128B/AT25256B
Description
© 2019 Microchip Technology Inc.
DS20006193A-page 7
3.2 Block Diagram
GND
Memory
System Control
Module
High-Voltage
Generation
Circuit
Address Register
and Counter
Write Protection
Control
VCC
SCK
SI
Power-on
Reset
Generator
Row Decoder
Data Register
SO
Pause
Operation
Control
Register Bank:
STATUS Register
Data Output
Buffer
CS
WP
HOLD
1 page
EEPROM Array
Column Decoder
AT25128B/AT25256B
Description
© 2019 Microchip Technology Inc.
DS20006193A-page 8
4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Operating temperature -55°C to +125°C
Storage temperature -65°C to +150°C
Voltage on any pin with respect to ground -1.0V to +7.0V
AT25128B/AT25256B
Electrical Characteristics
V
CC
DC output current 5.0 mA
ESD protection > 4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
4.2 DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT25128B/AT25256B
Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C
VCC Power Supply Low-Voltage Grade 1.8V to 5.5V
4.3 DC Characteristics
Table 4-2. DC Characteristics
(1)
6.25V
Parameter Symbol Minimum Typical Maximum Units Conditions
Supply Voltage V
Supply Voltage V
Supply Voltage V
Supply Current I
CC1
CC2
CC3
CC1
1.8 — 5.5 V
2.5 — 5.5 V
4.5 — 5.5 V
— 9.0 10.0 mA VCC = 5.0V at 20 MHz,
SO = Open, Read
Supply Current I
CC2
— 5.0 7.0 mA VCC = 5.0V at 10 MHz,
SO = Open, Read, Write
Supply Current I
CC3
— 2.2 3.5 mA VCC = 5.0V at 1 MHz,
SO = Open, Read, Write
Standby Current I
© 2019 Microchip Technology Inc.
SB1
— 0.2 3.0 µA VCC = 1.8V, CS = V
CC
DS20006193A-page 9
AT25128B/AT25256B
Electrical Characteristics
...........continued
Parameter Symbol Minimum Typical Maximum Units Conditions
Standby Current I
Standby Current I
Input Leakage I
Output Leakage I
Input
V
Low-Voltage
Input
V
High-Voltage
Output
V
Low-Voltage
Output
V
High-Voltage
Output
V
Low-Voltage
Output
V
High-Voltage
SB2
SB3
IL
OL
IL
IH
OL1
OH1
OL2
OH2
— 0.5 3.0 µA VCC = 2.5V, CS = V
— 2.0 5.0 µA VCC = 5.0V, CS = V
-3.0 — 3.0 µA VIN = 0V to V
CC
CC
CC
-3.0 — 3.0 µA VIN = 0V to VCC,
TAC = 0°C to +70°C
(2)
(2)
-1.0 — VCC x 0.3 V
VCC x 0.7 — VCC + 0.5 V
— — 0.4 V 3.6V ≤ VCC ≤ 5.5V IOL = 3.0 mA
VCC - 0.8 — — V 3.6V ≤ VCC ≤ 5.5V IOH = -1.6 mA
— — 0.2 V 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA
VCC - 0.2 — — V 1.8V ≤ VCC ≤ 3.6V IOH = -100 µA
Note:
1. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.8V to 5.5V
(unless otherwise noted).
2. VIL min and VIH max are reference only and are not tested.
4.4 AC Characteristics
Table 4-3. AC Characteristics
Parameter Symbol Minimum Maximum Units Conditions
SCK Clock Frequency f
Input Rise Time t
(1)
SCK
RI
0 20 MHz VCC = 4.5V to 5.5V
0 10 MHz VCC = 2.5V to 5.5V
0 5 MHz VCC = 1.8V to 5.5V
— 2000 ns VCC = 4.5V to 5.5V
— 2000 ns VCC = 2.5V to 5.5V
— 2000 ns VCC = 1.8V to 5.5V
© 2019 Microchip Technology Inc.
DS20006193A-page 10
AT25128B/AT25256B
Electrical Characteristics
...........continued
Parameter Symbol Minimum Maximum Units Conditions
Input Fall Time t
SCK High Time t
SCK Low Time t
CS High Time t
CS Setup Time t
FI
WH
WL
CS
CSS
— 2000 ns VCC = 4.5V to 5.5V
— 2000 ns VCC = 2.5V to 5.5V
— 2000 ns VCC = 1.8V to 5.5V
20 — ns VCC = 4.5V to 5.5V
40 — ns VCC = 2.5V to 5.5V
80 — ns VCC = 1.8V to 5.5V
20 — ns VCC = 4.5V to 5.5V
40 — ns VCC = 2.5V to 5.5V
80 — ns VCC = 1.8V to 5.5V
100 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 5.5V
200 — ns VCC = 1.8V to 5.5V
100 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 5.5V
200 — ns VCC = 1.8V to 5.5V
CS Hold Time t
Data In Setup Time t
Data In Hold Time t
HOLD Setup Time t
HOLD Hold Time t
CSH
SU
H
HD
CD
100 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 5.5V
200 — ns VCC = 1.8V to 5.5V
5 — ns VCC = 4.5V to 5.5V
10 — ns VCC = 2.5V to 5.5V
20 — ns VCC = 1.8V to 5.5V
5 — ns VCC = 4.5V to 5.5V
10 — ns VCC = 2.5V to 5.5V
20 — ns VCC = 1.8V to 5.5V
5 — ns VCC = 4.5V to 5.5V
10 — ns VCC = 2.5V to 5.5V
20 — ns VCC = 1.8V to 5.5V
5 — ns VCC = 4.5V to 5.5V
10 — ns VCC = 2.5V to 5.5V
20 — ns VCC = 1.8V to 5.5V
© 2019 Microchip Technology Inc.
DS20006193A-page 11
AT25128B/AT25256B
Electrical Characteristics
...........continued
Parameter Symbol Minimum Maximum Units Conditions
Output Valid t
Output Hold Time t
HOLD to Output Low Z t
HOLD to Output High Z t
Output Disable Time t
V
HO
LZ
HZ
DIS
0 20 ns VCC = 4.5V to 5.5V
0 40 ns VCC = 2.5V to 5.5V
0 80 ns VCC = 1.8V to 5.5V
0 — ns VCC = 4.5V to 5.5V
0 — ns VCC = 2.5V to 5.5V
0 — ns VCC = 1.8V to 5.5V
0 25 ns VCC = 4.5V to 5.5V
0 50 ns VCC = 2.5V to 5.5V
0 100 ns VCC = 1.8V to 5.5V
— 25 ns VCC = 4.5V to 5.5V
— 50 ns VCC = 2.5V to 5.5V
— 100 ns VCC = 1.8V to 5.5V
— 25 ns VCC = 4.5V to 5.5V
— 50 ns VCC = 2.5V to 5.5V
— 100 ns VCC = 1.8V to 5.5V
Write Cycle Time t
WC
— 5 ms VCC = 4.5V to 5.5V
— 5 ms VCC = 2.5V to 5.5V
— 5 ms VCC = 1.8V to 5.5V
Note:
1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
© 2019 Microchip Technology Inc.
DS20006193A-page 12
4.5 SPI Synchronous Data Timimg
t
DIS
t
HO
t
CSH
t
CS
t
V
t
H
V
OH
V
OL
High
Impedance
Valid Data In
t
WH
V
IH
V
IH
V
IL
t
CSS
t
WL
SCK
SI
SO
CS
V
IL
V
IH
V
IL
t
SU
High
Impedance
AT25128B/AT25256B
Electrical Characteristics
4.6 Electrical Specifications
4.6.1 Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT25128B/AT25256B should monotonically rise
from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.6.1.1 Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up
sequence, the AT25128B/AT25256B includes a Power-on Reset (POR) circuit. Upon power-up, the
device will not respond to any instructions until the VCC level crosses the internal voltage threshold (V
that brings the device out of Reset and into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has
reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is
greater than or equal to the minimum VCC level, the bus master must wait at least t
first instruction to the device. See Table 4-4 for the values associated with these power-up parameters.
(1)
Table 4-4. Power-Up Conditions
Symbol Parameter Min. Max. Units
t
PUP
V
POR
t
POFF
Note:
Time required after VCC is stable before the device can accept instructions 100 － µs
Power-on Reset Threshold Voltage － 1.5 V
Minimum time at VCC = 0V between power cycles 0.03 － ms
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT25128B/AT25256B drops below
the maximum V
first driving the VCC pin to GND in less than 1 ms, waiting at least the minimum t
POR
level specified, it is recommended that a full-power cycle sequence be performed by
performing a new power-up sequence in compliance with the requirements defined in this section.
© 2019 Microchip Technology Inc.
)
POR
before sending the
PUP
time and then
POFF
DS20006193A-page 13
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