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The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name8-Lead SOIC8-Lead TSSOP8-Pad UDFN
CS1111Chip Select
SO2222Serial Data Output
(2)
WP
GND4444Ground
SI5555Serial Data Input
SCK6666Serial Data Clock
(2)
HOLD
V
CC
Note:
1.The exposed pad on this package can be connected to GND or left floating.
2.The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.
3333Write-Protect
7777Suspends Serial Input
8888Device Power Supply
AT25010B/AT25020B/AT25040B
Pin Description
(1)
8-Ball VFBGAFunction
2.1 Chip Select (CS)
The AT25010B/AT25020B/AT25040B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will remain in
a high‑impedance state.
To ensure robust operation, the
to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on CS is required prior to any
sequence being initiated.
2.2 Serial Data Output (SO)
The Serial Data Output (SO) pin is used to transfer data out of the AT25010B/AT25020B/AT25040B. During a read
sequence, data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK).
2.3 Write-Protect (WP)
The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is brought low,
all write operations are inhibited. WP going low while CS is still low will interrupt a write operation. If the internal write
cycle has already been initiated, WP going low will have no effect on any write operation.
2.4 Ground (GND)
The ground reference for the Device Power Supply (VCC). The Ground (GND) pin should be connected to the system
ground.
CS pin should follow VCC upon power-up. It is therefore recommended to connect CS
2.5 Serial Data Input (SI)
The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses and data.
Data is latched on the rising edge of the Serial Data Clock (SCK).
The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the AT25010B/
AT25020B/AT25040B. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched in on the
rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling edge of SCK.
2.7 Suspend Serial Input (HOLD)
The Suspend Serial Input (HOLD) pin is used in conjunction with the Chip Select (CS) pin to pause the AT25010B/
AT25020B/AT25040B. When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must
be brought low while the Serial Data Clock (SCK) pin is low. To resume serial communication, the HOLD pin is
brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the Serial Data Input (SI) pin will
be ignored while the Serial Data Output (SO) pin will be in the high‑impedance state.
2.8 Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at invalid V
voltages may produce spurious results and should not be attempted.
The AT25010B/AT25020B/AT25040B provides 1,024/2,048/4,096 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 128/256/512 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low‑power and low‑voltage operation are
essential. The device is available in space-saving 8‑lead SOIC, 8‑lead TSSOP, 8‑pad UDFN and 8‑ball VFBGA
packages. All packages operate from 1.8V to 5.5V.
Voltage on any pin with respect to ground-1.0V to +7.0V
V
CC
DC output current5.0 mA
ESD protection> 4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
AT25010B/AT25020B/AT25040B
Electrical Characteristics
6.25V
4.2 DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT25010B/AT25020B/AT25040B
Operating Temperature (Case)Industrial Temperature Range-40°C to +85°C
1.Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL
Gate and 30 pF (unless otherwise noted).
4.5 SPI Synchronous Data Timimg
AT25010B/AT25020B/AT25040B
Electrical Characteristics
4.6 Electrical Specifications
4.6.1 Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT25010B/AT25020B/AT25040B should monotonically rise
from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.6.1.1 Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the
AT25010B/AT25020B/AT25040B includes a Power-on Reset (POR) circuit. Upon power-up, the device will not
respond to any instructions until the VCC level crosses the internal voltage threshold (V
of Reset and into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a
stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the
minimum VCC level, the bus master must wait at least t
4-4 for the values associated with these power-up parameters.
(1)
Table 4-4. Power-Up Conditions
SymbolParameterMin. Max. Units
t
PUP
V
POR
t
POFF
Note:
1.These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT25010B/AT25020B/AT25040B drops below
the maximum V