Datasheet AT24HC02C Datasheet

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AT24HC02C

I²C-Compatible (Two-Wire) Serial EEPROM 2-Kbit (256 x 8)

Features

• Low-Voltage Operation:

– VCC = 1.7V to 5.5V

• Internally Organized as 256 x 8 (2K)

• Industrial Temperature Range: -40°C to +85°C

• I2C-Compatible (Two-Wire) Serial Interface:

– 100 kHz Standard mode, 1.7V to 5.5V

– 400 kHz Fast mode, 1.7V to 5.5V

– 1 MHz Fast Mode Plus (FM+), 2.5V to 5.5V

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• Write-Protect Pin for Half Array Hardware Data Protection

• Ultra Low Active Current (3 mA maximum) and Standby Current (6 μA maximum)

• 8-Byte Page Write Mode:

– Partial page writes allowed

• Random and Sequential Read Modes

• Self-Timed Write Cycle within 5 ms Maximum

• ESD Protection > 4,000V

• High Reliability:

– Endurance: 1,000,000 write cycles

– Data retention: 100 years

• Green Package Options (Lead-free/Halide-free/RoHS compliant)

• Die Sale Options: Wafer Form and Tape and Reel Available

Packages

• 8-Lead PDIP, 8-Lead SOIC and 8-Lead TSSOP

Datasheet

20006123A-page 1

AT24HC02C

Features.......................................................................................................................... 1

Packages.........................................................................................................................1

1. Package Types (not to scale).................................................................................... 4

2. Pin Descriptions.........................................................................................................5

2.1. Device Address Inputs (A0, A1, A2).............................................................................................5

2.2. Ground......................................................................................................................................... 5

2.3. Serial Data (SDA).........................................................................................................................5

2.4. Serial Clock (SCL)........................................................................................................................6

2.5. Write-Protect (WP)....................................................................................................................... 6

2.6. Device Power Supply................................................................................................................... 6

3. Description.................................................................................................................7

3.1. System Configuration Using Two-Wire Serial EEPROMs ...........................................................7

3.2. Block Diagram.............................................................................................................................. 8

4. Electrical Characteristics........................................................................................... 9

4.1. Absolute Maximum Ratings..........................................................................................................9

4.2. DC and AC Operating Range.......................................................................................................9

4.3. DC Characteristics....................................................................................................................... 9

4.4. AC Characteristics......................................................................................................................10

4.5. Electrical Specifications..............................................................................................................11

5. Device Operation and Communication....................................................................13

5.1. Clock and Data Transition Requirements...................................................................................13

5.2. Start and Stop Conditions.......................................................................................................... 13

5.3. Acknowledge and No-Acknowledge...........................................................................................14

5.4. Standby Mode............................................................................................................................ 14

5.5. Software Reset...........................................................................................................................15

6. Memory Organization.............................................................................................. 16

6.1. Device Addressing..................................................................................................................... 16

7. Write Operations......................................................................................................17

7.1. Byte Write...................................................................................................................................17

7.2. Page Write..................................................................................................................................17

7.3. Acknowledge Polling.................................................................................................................. 18

7.4. Write Cycle Timing..................................................................................................................... 19

7.5. Write Protection..........................................................................................................................19

8. Read Operations..................................................................................................... 20

8.1. Current Address Read................................................................................................................20

8.2. Random Read............................................................................................................................ 20

Datasheet

20006123A-page 2

AT24HC02C

8.3. Sequential Read.........................................................................................................................21

9. Device Default Condition from Microchip................................................................ 22

10. Packaging Information.............................................................................................23

10.1. Package Marking Information.....................................................................................................23

11. Revision History.......................................................................................................31

The Microchip Web Site................................................................................................ 32

Customer Change Notification Service..........................................................................32

Customer Support......................................................................................................... 32

Product Identification System........................................................................................33

Microchip Devices Code Protection Feature................................................................. 33

Legal Notice...................................................................................................................34

Trademarks................................................................................................................... 34

Quality Management System Certified by DNV.............................................................35

Worldwide Sales and Service........................................................................................36

Datasheet

20006123A-page 3

1. Package Types (not to scale)

8-Lead PDIP/SOIC/TSSOP

(Top View)

A0 1

GND

Vcc

SCL

SDA

AT24HC02C

Package Types (not to scale)

Datasheet

20006123A-page 4

2. Pin Descriptions

The descriptions of the pins are listed in Table 2-1.

Table 2-1. Pin Function Table

Name 8-Lead PDIP 8-Lead SOIC 8-Lead TSSOP Function

(1)

GND 4 4 4 Ground

SDA 5 5 5 Serial Data

SCL 6 6 6 Serial Clock

(1)

Note:

1. If the A0, A1, A2 or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull‑down mechanism disengages. Microchip recommends connecting these pins to a known state whenever possible.

AT24HC02C

Pin Descriptions

1 1 1 Device Address Input

2 2 2 Device Address Input

3 3 3 Device Address Input

7 7 7 Write-Protect

8 8 8 Device Power Supply

2.1 Device Address Inputs (A0, A1, A2)

The A0, A1 and A2 pins are device address inputs that are hard-wired (directly to GND or to VCC) for compatibility with other two-wire Serial EEPROM devices. When the pins are hard-wired, as many as eight devices may be addressed on a single bus system. A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A0, A1 and A2 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear in customer applications, Microchip recommends always connecting the address pins to a known state. When using a pull‑up resistor, Microchip recommends using 10 kΩ or less.

2.2 Ground

The ground reference for the power supply. GND should be connected to the system ground.

2.3 Serial Data (SDA)

The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. The SDA pin must be pulled high using an external pull-up resistor (not to exceed 10 kΩ in value) and may be wire-ORed with any number of other open-drain or open-collector pins from other devices on the same bus.

Datasheet

20006123A-page 5

2.4 Serial Clock (SCL)

The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA pin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle or pulled high using an external pull-up resistor.

2.5 Write-Protect (WP)

The write-protect input, when connected to GND, allows normal write operations. When the WP pin is connected directly to VCC, all write operations to the protected memory are inhibited.

If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear in customer applications, Microchip recommends always connecting the WP pin to a known state. When using a pull‑up resistor, Microchip recommends using 10 kΩ or less.

Table 2-2. Write-Protect

WP Pin Status Part of the Array Protected

AT24HC02C

Pin Descriptions

At V

At GND Normal Write Operations

2.6 Device Power Supply

The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted.

Upper Half (1K) Array

Datasheet

20006123A-page 6

3. Description

I2C Bus Master:

Microcontroller

Slave 0

AT24HCXXX

SDA

SCL

GND

SCL

SDA

PUP(max) =

R(max)

0.8473 x C

PUP(min) =

VCC - V

OL(max)

Slave 1

AT24HCXXX

SDA

SCL

GND

Slave 7

AT24HCXXX

SDA

SCL

GND

The AT24HC02C provides 2,048 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 256 words of 8 bits each. The device's cascading feature allows up to eight devices to share a common two‑wire bus. This device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The device is available in space‑saving 8‑lead PDIP, 8‑lead SOIC and 8‑lead TSSOP packages. All packages operate from 1.7V to 5.5V.

3.1 System Configuration Using Two-Wire Serial EEPROMs

AT24HC02C

Description

Datasheet

20006123A-page 7

3.2 Block Diagram

1 page

Start Stop

Detector

GND

Memory

System Control

Module

High-Voltage

Generation Circuit

Data & ACK

Input/Output Control

Address Register

and Counter

Write

Protection

Control

OUT

Hardware

Address

Comparator

VCC

SCL

SDA

Power-on

Reset

Generator

EEPROM Array

Column Decoder

Row Decoder

Data Register

AT24HC02C

Description

Datasheet

20006123A-page 8

4. Electrical Characteristics

4.1 Absolute Maximum Ratings

Temperature under bias -55°C to +125°C

Storage temperature -65°C to +150°C

AT24HC02C

Electrical Characteristics

Voltage on any pin with respect to ground -1.0V to +7.0V

DC output current 5.0 mA

ESD protection >4 kV

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4.2 DC and AC Operating Range

Table 4-1. DC and AC Operating Range

AT24HC02C

Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C

VCC Power Supply Low Voltage Grade 1.7V to 5.5V

4.3 DC Characteristics

Table 4-2. DC Characteristics

6.25V

Parameter Symbol Minimum Typical

Supply Voltage

Supply Current

Standby Current

CC1

CC2

1.7 — 5.5 V

— 0.4 1.0 mA VCC = 5.0V, Read at

— 2.0 3.0 mA VCC = 5.0V, Write at

— — 1.0 μA VCC = 1.7V, VIN = VCC or

— — 2.0 μA VCC = 2.5V, VIN = VCC or

— — 6.0 μA VCC = 5.5V, VIN = VCC or

(1)

Maximum Units Test Conditions

400 kHz

GND

Datasheet

20006123A-page 9

...........continued

Parameter Symbol Minimum Typical

Electrical Characteristics

(1)

Maximum Units Test Conditions

AT24HC02C

Input

— 0.10 3.0 μA VIN = VCC or GND Leakage Current

Output

— 0.05 3.0 μA V Leakage Current

Input Low

-0.6 — VCC x 0.3 V Note 2

Level

Input High

VCC x 0.7 — VCC + 0.5 V Note 2

Level

Output Low

OL1

— — 0.2 V VCC = 1.7V, IOL = 0.15 mA Level

Output Low

OL2

— — 0.4 V VCC = 3.0V, IOL = 2.1 mA Level

Note:

1. Typical values characterized at TA = +25°C unless otherwise noted.

2. This parameter is characterized but is not 100% tested in production.

= VCC or GND

OUT

4.4 AC Characteristics

Table 4-3. AC Characteristics

Parameter Symbol Fast Mode Fast Mode Plus Units

Clock Frequency, SCL

Clock Pulse Width Low

Clock Pulse Width High

Noise Suppression Time

Clock Low to Data Out Valid

Bus Free Time between Stop and Start

Start Hold Time t

Start Set-Up Time t

Data In Hold Time t

SCL

LOW

HIGH

BUF

HD.STA

SU.STA

HD.DAT

(1)

VCC = 1.7V to 2.5V VCC = 2.5V to 5.5V

Min. Max. Min. Max.

— 400 — 1000 kHz

1,200 — 500 — ns

600 — 400 — ns

— 100 — 50 ns

100 900 50 450 ns

1,200 — 500 — ns

600 — 250 — ns

0 — 0 — ns

Datasheet

20006123A-page 10

SCL

SDA In

SDA Out

HIGH

LOW

BUF

SU.STO

SU.DAT

HD.DAT

HD.STA

SU.STA

AT24HC02C

Electrical Characteristics

...........continued

Parameter Symbol Fast Mode Fast Mode Plus Units

VCC = 1.7V to 2.5V VCC = 2.5V to 5.5V

Min. Max. Min. Max.

Data In Set-up Time

Inputs Rise Time

Inputs Fall Time

Stop Set-Up Time t

Data Out Hold Time

Write Cycle Time t

Note:

1. AC measurement conditions:

– CL: 100 pF

– R

PUP

10 kΩ (100 kHz)

– Input pulse voltages: 0.3 x VCC to 0.7 x V

– Input rise and fall times: ≤50 ns

– Input and output timing reference voltages: 0.5 x V

2. These parameters are determined through product characterization and are not 100% tested in production.

(2)

SU.DAT

SU.STO

100 — 100 — ns

— 300 — 300 ns

— 300 — 100 ns

600 — 250 — ns

50 — 50 — ns

— 5 — 5 ms

(SDA bus line pull-up resistor to VCC): 1.3 kΩ (1000 kHz), 4 kΩ (400 kHz),

Figure 4-1. Bus Timing

4.5 Electrical Specifications

4.5.1 Power-Up Requirements and Reset Behavior

During a power-up sequence, the VCC supplied to the AT24HC02C should monotonically rise from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.

Datasheet

20006123A-page 11

4.5.1.1 Device Reset

To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the AT24HC02C includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (V device out of Reset and into Standby mode.

The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the minimum VCC level, the bus master must wait at least t first command to the device. See Table 4-4 for the values associated with these power-up parameters.

Table 4-4. Power-up Conditions

Symbol Parameter Min. Max. Units

(1)

AT24HC02C

Electrical Characteristics

) that brings the

POR

before sending the

PUP

POFF

Time required after VCC is stable before the device can accept commands 100 － µs

Power-on Reset Threshold Voltage － 1.5 V

POR

Minimum time at VCC = 0V between power cycles 500 － ms

Note:

1. These parameters are characterized but they are not 100% tested in production.

If an event occurs in the system where the VCC level supplied to the AT24HC02C drops below the maximum V

level specified, it is recommended that a full power cycle sequence be performed by first

POR

driving the VCC pin to GND, waiting at least the minimum t sequence in compliance with the requirements defined in this section.

4.5.2 Pin Capacitance

Table 4-5. Pin Capacitance

Symbol Test Condition Max. Units Conditions

I/O

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Note:

1. This parameter is characterized but is not 100% tested in production.

(1)

time and then performing a new power-up

POFF

= 0V

I/O

4.5.3 EEPROM Cell Performance Characteristics

Table 4-6. EEPROM Cell Performance Characteristics

Operation Test Condition Min. Max. Units

Write Endurance

(1)

TA = 25°C, VCC = 3.3V, Page Write mode

Data Retention

(1)

TA = 55°C 100 — Years

Note:

1. Performance is determined through characterization and the qualification process.

Datasheet

1,000,000 — Write Cycles

20006123A-page 12

5. Device Operation and Communication

The AT24HC02C operates as a slave device and utilizes a simple I2C-compatible two-wire digital serial interface to communicate with a host controller, commonly referred to as the bus master. The master initiates and controls all read and write operations to the slave devices on the serial bus, and both the master and the slave devices can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is used to receive the clock signal from the master, while the bidirectional SDA pin is used to receive command and data information from the master as well as to send data back to the master. Data is always latched into the AT24HC02C on the rising edge of SCL and always output from the device on the falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus noise.

All command and data information is transferred with the Most Significant bit (MSb) first. During bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been transferred, the receiving device must respond with either an Acknowledge (ACK) or a No-Acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the master. Therefore, nine clock cycles are required for every one byte of data transferred. There are no unused clock cycles during any read or write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer and ACK or NACK clock cycle.

AT24HC02C

Device Operation and Communication

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. Start and Stop conditions are used to initiate and end all serial bus communication between the master and the slave devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is determined by the master. In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic-high state at the same time.

5.1 Clock and Data Transition Requirements

The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor. SCL is an input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop condition as defined below. The relationship of the AC timing parameters with respect to SCL and SDA for the AT24HC02C are shown in the timing waveform in Figure 4-1. The AC timing characteristics and specifications are outlined in AC Characteristics.

5.2 Start and Stop Conditions

5.2.1 Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable logic ‘1’ state and will bring the device out of Standby mode. The master uses a Start condition to initiate any data transfer sequence; therefore, every command must begin with a Start condition. The device will continuously monitor the SDA and SCL pins for a Start condition but will not respond unless one is detected. Refer to Figure 5-1 for more details.

5.2.2 Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the logic ‘1’ state.

Datasheet

20006123A-page 13

The master can use the Stop condition to end a data transfer sequence with the AT24HC02C, which will

SCL

SDA

Must Be

Stable

SDA Change Allowed

Acknowledge

Valid

Stop

Condition

Start

Condition

1 2 8 9

SDA

Must Be

Stable

Acknowledge Window

The transmitting device (Master or Slave)

must release the SDA line at this point to allow

the receiving device (Master or Slave) to drive the

SDA line low to ACK the previous 8-bit word.

The receiver (Master or Slave)

must release the SDA line at

this point to allow the transmitter

to continue sending new data.

subsequently return to Standby mode. The master can also utilize a repeated Start condition instead of a Stop condition to end the current data transfer if the master will perform another operation. Refer to

Figure 5-1 for more details.

5.3 Acknowledge and No-Acknowledge

After every byte of data is received, the receiving device must confirm to the transmitting device that it has successfully received the data byte by responding with what is known as an Acknowledge (ACK). An ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle followed by the receiving device responding with a logic ‘0’ during the entire high period of the ninth clock cycle.

When the AT24HC02C is transmitting data to the master, the master can indicate that it is done receiving data and wants to end the operation by sending a logic ‘1’ response to the AT24HC02C instead of an ACK response during the ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished by the master sending a logic ‘1’ during the ninth clock cycle, at which point the AT24HC02C will release the SDA line so the master can then generate a Stop condition.

The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA line at the falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’ to ACK the previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the transmitter to continue sending new data. A timing diagram has been provided in

Figure 5-1 to better illustrate these requirements.

AT24HC02C

Device Operation and Communication

Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge

5.4 Standby Mode

The AT24HC02C features a low-power Standby mode that is enabled when any one of the following occurs:

• A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).

• A Stop condition is received by the device unless it initiates an internal write cycle (see Write

• At the completion of an internal write cycle (see Write Operations).

Operations).

Datasheet

20006123A-page 14

5.5 Software Reset

SCL

Device is

8321

SDA

Dummy Clock Cycles

SDA Released

Software Reset

by EEPROM

After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset by clocking SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA is released by the EEPROM will vary. The software Reset sequence should not take more than nine dummy clock cycles. Once the software Reset sequence is complete, new protocol can be sent to the device by sending a Start condition followed by the protocol. Refer to Figure 5-2 for an illustration.

Figure 5-2. Software Reset

AT24HC02C

Device Operation and Communication

In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device (see Power-Up Requirements and Reset Behavior).

Datasheet

20006123A-page 15

6. Memory Organization

The AT24HC02C is internally organized as 32 pages of 8 bytes each.

6.1 Device Addressing

Accessing the device requires an 8-bit device address byte following a Start condition to enable the device for a read or write operation. Since multiple slave devices can reside on the serial bus, each slave device must have its own unique address so the master can access each device independently.

The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type identifier ‘1010’ (Ah) is required in bits 7 through 4 of the device address byte (see Table

6-1).

Following the 4-bit device type identifier are the hardware slave address bits, A2, A1 and A0. These bits can be used to expand the address space by allowing up to eight Serial EEPROM devices on the same bus. These hardware slave address bits must correlate with the voltage level on the corresponding hardwired device address input pins A0, A1 and A2. The A0, A1 and A2 pins use an internal proprietary circuit that automatically biases the pin to a logic ‘0’ state if the pin is allowed to float. In order to operate in a wide variety of application environments, the pull‑down mechanism is intentionally designed to be somewhat strong. Once the pin is biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull‑down mechanism disengages. Microchip recommends connecting the A0, A1 and A2 pins to a known state whenever possible.

AT24HC02C

Memory Organization

The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24HC02C will return an ACK. If a valid comparison is not made, the device will NACK.

Table 6-1. Device Address Byte

Package Device Type Identifier Hardware Slave Address Bits R/W Select

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All Package Types

For all operations except the current address read, a word address byte must be transmitted to the device immediately following the device address byte. The word address byte contains the 8-bit memory array word address, and is used to specify which byte location in the EEPROM to start reading or writing. Refer to Table 6-2 to review these bit positions.

Table 6-2. Word Address Byte

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

A7 A6 A5 A4 A3 A2 A1 A0

1 0 1 0

A2 A1 A0 R/W

Datasheet

20006123A-page 16

7. Write Operations

SCL

SDA

Device Address Byte Word Address Byte

Data Word

Start

Master

ACK from

Slave

MSB

Stop

Master

MSB

1 2 3 4 5 6 7 8 9

1 0 1 0 A

2 A1 A0

0 0

1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0 0

A7 A6 A5 A4 A3 A2 A1 A0 0

1 2 3 4 5 6 7 8 9

ACK from

Slave

ACK from

Slave

All write operations for the AT24HC02C begin with the master sending a Start condition, followed by a device address byte with the R/W bit set to logic ‘0’, and then by the word address byte. The data value(s) to be written to the device immediately follow the word address byte.

7.1 Byte Write

The AT24HC02C supports the writing of a single 8-bit byte. Selecting a data word in the AT24HC02C requires an 8-bit word address.

Upon receipt of the proper device address and the word address bytes, the EEPROM will send an Acknowledge. The device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit data word, the EEPROM will respond with an ACK. The addressing device, such as a bus master, must then terminate the write operation with a Stop condition. At that time, the EEPROM will enter an internally self-timed write cycle, which will be completed within tWR, while the data word is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete.

AT24HC02C

Write Operations

Figure 7-1. Byte Write

7.2 Page Write

A page write operation allows up to 8 bytes to be written in the same write cycle, provided all bytes are in the same row of the memory array (where address bits A7 to A3 are the same). Partial page writes of less than 8 bytes are also allowed.

A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus master can transmit up to seven additional data words. The EEPROM will respond with an ACK after each data word is received. Once all data to be written has been sent to the device, the bus master must issue a Stop condition (see Figure 7-2) at which time the internally self-timed write cycle will begin.

The lower three bits of the word address are internally incremented following the receipt of each data word. The higher order address bits are not incremented and retain the memory page row location. Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. When the incremented word address reaches the page boundary, the address counter will rollover to the beginning of the same page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become unintentionally altered.

Datasheet

20006123A-page 17

Figure 7-2. Page Write

SCL

SDA

Start

Master

ACK from

Slave

ACK from

Slave

Device Address Byte Word Address Byte

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A

2 A1 A0

0 0

ACK from

Slave

Stop

Master

ACK from

Slave

Data Word (n) Data Word (n+x), max of 8 without rollover

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

MSB MSB

A7 A6 A5 A4 A3 A2 A1 A0 0

D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0

Did

the device

ACK?

Send any

Write

protocol.

Send

Stop

condition

to initiate the

Write cycle.

Send Start

condition followed

by a valid

Device Address

byte with R/W = 0.

Proceed to

next Read or

Write operation.

YES

AT24HC02C

Write Operations

7.3 Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would prefer not to wait the fixed maximum write cycle time (tWR). This method allows the application to know immediately when the Serial EEPROM write cycle has completed, so a subsequent operation can be started.

Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves repeatedly sending a Start condition followed by a valid device address byte with the R/W bit set at logic ‘0’. The device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the EEPROM will respond with an ACK, allowing a new read or write operation to be immediately initiated. A flowchart has been included below in Figure 7-3 to better illustrate this technique.

Figure 7-3. Acknowledge Polling Flowchart

Datasheet

20006123A-page 18

7.4 Write Cycle Timing

Stop

Condition

Start

Condition

Data Word n

ACKD0

SDA

Stop

Condition

SCL

8 9

ACK

First Acknowledge from the device to a valid device address sequence after write cycle is initiated. The minimum t

can only be determined through

the use of an ACK Polling routine.

The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that begins the internal write cycle to the Start condition of the first device address byte sent to the AT24HC02C that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement. During the internally self-timed write cycle, any attempts to read from or write to the memory array will not be processed.

Figure 7-4. Write Cycle Timing

AT24HC02C

Write Operations

7.5 Write Protection

The AT24HC02C utilizes a hardware data protection scheme that allows the user to write-protect the upper half (1K) memory array contents when the WP pin is at V be set if the WP pin is at GND or left floating.

Table 7-1. AT24HC02C Write-Protect Behavior

WP Pin Voltage Part of the Array Protected

GND None － Write Protection Not Enabled

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the start of an internally self-timed write cycle. Changing the WP pin state after the Stop condition has been sent will not alter or interrupt the execution of the write cycle.

If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the device address, word address and data bytes, but no write cycle will occur when the Stop condition is issued. The device will immediately be ready to accept a new read or write command.

(or a valid VIH). No write protection will

Upper Half (1K) Array

Datasheet

20006123A-page 19

8. Read Operations

SCL

SDA

Device Address Byte

Data Word (n)

Start

Master

ACK from

Slave

NACK

from

Master

Stop

Master

MSB MSB

1 0 1 0 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

Read operations are initiated the same way as write operations with the exception that the Read/Write Select bit in the device address byte must be a logic ‘1’. There are three read operations:

• Current Address Read

• Random Address Read

• Sequential Read

8.1 Current Address Read

The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the VCC is maintained to the part. The address roll-over during a read is from the last byte of the last page to the first byte of the first page of the memory.

A current address read operation will output data according to the location of the internal data word address counter. This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence.

AT24HC02C

Read Operations

Figure 8-1. Current Address Read

8.2 Random Read

A random read begins in the same way as a byte write operation does to load in a new data word address. This is known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in and acknowledged by the EEPROM, the bus master must generate another Start condition. The bus master now initiates a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The EEPROM will ACK the device address and serially clock out the data word on the SDA line. All types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence.

Datasheet

20006123A-page 20

Figure 8-2. Random Read

SCL

SDA

Start

Master

Device Address Byte Word Address Byte

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A

2 A1 A0

0 0

Dummy Write

Start

Master

Device Address Byte

Data Word (n)

Stop

Master

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A

2 A1 A0

1 0 D7 D6 D5 D4 D3 D2 D1 D0 1

A7 A6 A5 A4 A3 A2 A1 A0 0

ACK from

Slave

ACK from

Slave

ACK from

Slave

NACK

from

Master

SCL

SDA

Start

Master

ACK from

Slave

ACK from

Master

Device Address Byte Data Word (n)

MSB MSB

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 1 0 A

2 A1

1 0 D7 D6 D5 D4 D3 D2 D1 D0 0

ACK from

Master

NACK

from

Master

Stop

Master

ACK from

Master

Data Word (n+1) Data Word (n+2) Data Word (n+x)

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1

MSB MSB MSB

AT24HC02C

Read Operations

8.3 Sequential Read

Sequential reads are initiated by either a current address read or a random read. After the bus master receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the word address and serially clock out sequential data words. When the maximum memory address is reached, the data word address will roll-over and the sequential read will continue from the beginning of the memory array. All types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence.

Figure 8-3. Sequential Read

Datasheet

20006123A-page 21

Device Default Condition from Microchip

9. Device Default Condition from Microchip

The AT24HC02C is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations.

AT24HC02C

Datasheet

20006123A-page 22

10. Packaging Information

AT24HC02C: Package Marking Information

Catalog Number Truncation

AT24HC02C Truncation Code ###: H2C

Date Codes Voltages

YY = Year Y = Year WW = Work Week of Assembly % = Minimum Voltage 16: 2016 20: 2020 6: 2016 0: 2020 02: Week 2 M: 1.7V min 17: 2017 21: 2021 7: 2017 1: 2021 04: Week 4 18: 2018 22: 2022 8: 2018 2: 2022 ... 19: 2019 23: 2023 9: 2019 3: 2023 52: Week 52

Country of Origin Device Grade Atmel Truncation

CO = Country of Origin H or U: Industrial Grade AT: Atmel

ATM: Atmel

ATML: Atmel

Trace Code

NNN = Alphanumeric Trace Code (2 Characters for Small Packages)

Note 2: Package drawings are not to scale

Note 1: designates pin 1

YYWWNNN

###% CO

ATMLHYWW

8-lead SOIC

8-lead TSSOP

YYWWNNN

###%CO

ATHYWW

8-lead PDIP

YYWWNNN

###% CO

ATMLUYWW

10.1 Package Marking Information

AT24HC02C

Packaging Information

Datasheet

20006123A-page 23

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

Microchip Technology Drawing No. C04-018D Sheet 1 of 2

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

8X b

8X b1

PLANE

.010 C

NOTE 1

TOP VIEW

END VIEWSIDE VIEW

AT24HC02C

Packaging Information

Datasheet

20006123A-page 24

Microchip Technology Drawing No. C04-018D Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Units INCHES

Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch

.100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness

.008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width

.014 .018 .022 Overall Row Spacing eB - - .430

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

protrusions shall not exceed .010" per side.

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

Pin 1 visual index feature may vary, but must be located within the hatched area.

§ Significant Characteristic

Dimensioning and tolerancing per ASME Y14.5M

DATUM A DATUM A

e 2

ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)

AT24HC02C

Packaging Information

Datasheet

20006123A-page 25

0.25 C A–B D

SEATING

PLANE

TOP VIEW

SIDE VIEW

VIEW A–A

0.10

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

E 2

NOTE 5

NX b

0.10

C A–B

H 0.23

(L1)

R0.13

VIEW C

SEE VIEW C

NOTE 1

AT24HC02C

Packaging Information

Datasheet

20006123A-page 26

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

Foot Angle 0° - 8°

15°-5°

Mold Draft Angle Bottom

15°-5°

Mold Draft Angle Top

0.51-0.31

Lead Width

0.25-0.17

Lead Thickness

1.27-0.40LFoot Length

0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10

Standoff

--1.25A2Molded Package Thickness

1.75--AOverall Height

1.27 BSC

Pitch

8NNumber of Pins

MAXNOMMINDimension Limits

MILLIMETERSUnits

protrusions shall not exceed 0.15mm per side.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

4. Dimensioning and tolerancing per ASME Y14.5M

Notes:

Footprint

L1 1.04 REF

5. Datums A & B to be determined at Datum H.

AT24HC02C

Packaging Information

Datasheet

20006123A-page 27

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2057-SN Rev B

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Note:

Dimension Limits

Units

CContact Pad Spacing

Contact Pitch

MILLIMETERS

1.27 BSC

MIN

MAX

5.40

Contact Pad Length (X8)

Contact Pad Width (X8)

1.55

0.60

NOM

SILK SCREEN

AT24HC02C

Packaging Information

Datasheet

20006123A-page 28

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2YHUDOO+HLJKW $ ± ± 

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/HDG:LGWK E  ± 

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AT24HC02C

Packaging Information

Datasheet

20006123A-page 29

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Packaging Information

AT24HC02C

Datasheet

20006123A-page 30

11. Revision History

Revision A (December 2018)

Updated to the Microchip template. Microchip DS20006123 replaces Atmel document 8779. Corrected t

typo from 400 ns to 500 ns. Corrected tAA typo from 550 ns to 450 ns. Updated Part Marking

LOW

Information. Updated the "Software Reset" section. Added ESD rating. Removed lead finish designation. Updated trace code format in package markings. Added a figure for “System Configuration Using Two‑Wire Serial EEPROMs”. Updated "Block Diagram" figure. Added POR recommendations section. Updated section content throughout for clarification. Updated the PDIP, SOIC and TSSOP package drawings to Microchip format.

Atmel Document 8779 Revision B (April 2013)

Corrected Write-Protect address range. Updated footers and disclaimer page.

Atmel Document 8779 Revision A (June 2012)

Initial release of this document.

AT24HC02C

Revision History

Datasheet

20006123A-page 31

AT24HC02C

The Microchip Web Site

Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

Customer Change Notification Service

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.

To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

Datasheet

20006123A-page 32

Product Family

24HC = Standard I2C-compatible

Serial EEPROM with Half-Array Protection

Device Density

Shipping Carrier Option

Device Grade or Wafer/Die Thickness

Package Option

02 = 2 Kilobit

T = Tape and Reel, Standard Quantity Option B or Blank = Bulk (Tubes)

H or U = Industrial Temperature Range

(-40°C to +85°C)

= 11mil Wafer Thickness

SS = SOIC X = TSSOP P = PDIP W = Wafer Unsawn

AT24HC02C-SSHM-T

Device Revision

Operating Voltage

M = 1.7V to 5.5V

AT24HC02C

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples

Device Package Package

AT24HC02C‑PUM PDIP P P Bulk (Tubes) Industrial

AT24HC02C‑SSHM‑B SOIC SN SS Bulk (Tubes)

AT24HC02C‑SSHM‑T SOIC SN SS Tape and Reel

AT24HC02C‑XHM‑B TSSOP ST X Bulk (Tubes)

AT24HC02C‑XHM‑T TSSOP ST X Tape and Reel

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Drawing

Code

Package

Shipping Carrier Option Device Grade

Option

Datasheet

Temperature

(-40°C to 85°C)

20006123A-page 33

AT24HC02C

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

Datasheet

20006123A-page 34

AT24HC02C

ISBN: 978-1-5224-3995-0

Quality Management System Certified by DNV

ISO/TS 16949

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

Datasheet

20006123A-page 35

Worldwide Sales and Service

AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE

Corporate Office

2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com

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Tel: 512-257-3370

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Tel: 281-894-5983

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Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380

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Tel: 86-25-8473-2460

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China - Shenyang

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China - Shenzhen

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China - Suzhou

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China - Wuhan

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China - Xian

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China - Xiamen

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China - Zhuhai

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India - Bangalore

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India - New Delhi

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India - Pune

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Japan - Osaka

Tel: 81-6-6152-7160

Japan - Tokyo

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Korea - Daegu

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Korea - Seoul

Tel: 82-2-554-7200

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Malaysia - Penang

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Philippines - Manila

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Singapore

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Taiwan - Hsin Chu

Tel: 886-3-577-8366

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

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Thailand - Bangkok

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Vietnam - Ho Chi Minh

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Austria - Wels

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Denmark - Copenhagen

Tel: 45-4450-2828 Fax: 45-4485-2829

Finland - Espoo

Tel: 358-9-4520-820

France - Paris

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany - Garching

Tel: 49-8931-9700

Germany - Haan

Tel: 49-2129-3766400

Germany - Heilbronn

Tel: 49-7131-67-3636

Germany - Karlsruhe

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Germany - Munich

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Germany - Rosenheim

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Israel - Ra’anana

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Italy - Milan

Tel: 39-0331-742611 Fax: 39-0331-466781

Italy - Padova

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399 Fax: 31-416-690340

Norway - Trondheim

Tel: 47-72884388

Poland - Warsaw

Tel: 48-22-3325737

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90 Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 44-118-921-5800 Fax: 44-118-921-5820

Datasheet

20006123A-page 36

Datasheet AT24HC02C Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Packages

Table of Contents

1. Package Types (not to scale)

2. Pin Descriptions

2.1 Device Address Inputs (A0, A1, A2)

2.2 Ground

2.3 Serial Data (SDA)

2.4 Serial Clock (SCL)

2.5 Write-Protect (WP)

2.6 Device Power Supply

3. Description

3.1 System Configuration Using Two-Wire Serial EEPROMs

3.2 Block Diagram

4. Electrical Characteristics

4.1 Absolute Maximum Ratings

4.2 DC and AC Operating Range

4.3 DC Characteristics

4.4 AC Characteristics

4.5 Electrical Specifications

4.5.1 Power-Up Requirements and Reset Behavior

4.5.1.1 Device Reset

4.5.2 Pin Capacitance

4.5.3 EEPROM Cell Performance Characteristics

5. Device Operation and Communication

5.1 Clock and Data Transition Requirements

5.2 Start and Stop Conditions

5.2.1 Start Condition

5.2.2 Stop Condition

5.3 Acknowledge and No-Acknowledge

5.4 Standby Mode

Software Reset

6. Memory Organization

6.1 Device Addressing

7. Write Operations

7.1 Byte Write

7.2 Page Write

7.3 Acknowledge Polling

7.4 Write Cycle Timing

7.5 Write Protection

8. Read Operations

8.1 Current Address Read

8.2 Random Read

8.3 Sequential Read

9. Device Default Condition from Microchip

10. Packaging Information

10.1 Package Marking Information

11. Revision History

The Microchip Web Site

Customer Change Notification Service

Customer Support

Product Identification System

Microchip Devices Code Protection Feature

Legal Notice

Trademarks

Quality Management System Certified by DNV

Worldwide Sales and Service