Datasheet ASM8412CB Datasheet (APLUS)

PLUS MAKE YOUR PRODUCTION A-PLUS

A

ASM8412CB

DATA SHEET

PLUS INTEGRATED CIRCUITS INC.

A

Address:

3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,

Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.

TEL: [phone]

FAX: [phone]

WEBSITE : http: //www.aplusinc.com.tw

Sales E-mail: Mr. Jason

[e-mail]

Technology E-mail: Mr. George

[e-mail]

ASM8412CB –

ASM8412CB

VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

1.0 General Description

The ASM8412CB is very low cost voice synthesizer with 4-bit microprocessor. It has various

features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog

timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS

technology and halt function can minimize power dissipation. Its architecture is similar to RISC,

with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,

except for program branches and data table read instructions (which need two instruction cycles).

1.1 Feature



Single power supply can operate from 2.4V through 5V



Internal Program ROM: 4K x 10-bit



1 sets of 18-bit DPR can access up to 256K x 10 bits data memory space



Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh



I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)

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On-chip clock generator: Resistive Clock Drive(RM)



Timer: 1

• Timer0: a 9-bit auto-reload timer/counter



Stack: 2-level subroutine nesting



HALT and Release from HALT function to reduce power consumption



Watch Dog Timer (WDT)



Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles



Number of instruction: 22



The Voice function can be implemented by microprocessor instruction

• One 8-bit COUT output for ASM8412CB

1

Rev 1.0

FIGURE 1.1 : Block Diagram of ASM8412CB

(12)

]

(4)

)

ASM8412CB

Data Bus[3:0]

(ADDR[17:12])

=0000b

COUT

PCLATCH(8)

PCH(8) PCL(4)

DPR3,2,1

DLATCH(10)

Data Bus[3:0

Accumlator

ALU(4)

Register(4)

One-Channel

( Voice synthesizer )

COUT

PC[11:0]

ADDR[17:0]

DPR[17:0]

P1,P2,P3,P4

enter test mode

Reset Chip

Reset Chip

ROM_Data[9:0]

Immediate(4

Stack

(2-Level)

ROM_ADDR[17:0]

Program

(Data)

ROM

SRAM

(96 x 4)

00h-1Fh
40h-7Fh

Clock Generator

Tes t s el ect

Power on Reset

RESET pin

Instruction Bus [9:0]

Instruction Bus [9:0]

Timer0(9)

OSC

VDD/GND

PRA0

ROM Latch

Instruction

Latch

Instruction

Decoder

Control Signal

Instruction Bus [9:0]

PRA(4)
PRB(4)
PRC(4)

weak or strong
pull-low for PRA,

PRB, PRC

PRASL(4)

2

Rev 1.0

FIGURE 1.2 : External ROM Map of ASM8412CB

g

ASM8412CB

PC[11:0]

12bit x 2 STACK

00000h-3FFFFh

18-bit Data Pointer

Reserved for Testing

ram and data ROM

Pro

Data ROM

Reset Vector

00000h

00080h

00080h-003FFh

00400h

00000h-00FFFh

00FFFh(4K)

3FFFFh(256Kx10-bits)

3

Rev 1.0

1.2 Pin-Out

ASM8412CB

ASM8412CB Pin-Out

PRC1

PRC0/RESET

PRA3-1

PRA0/RESET

OSC
VDD1
COUT
GND1
GND2
TEST
VDD2
PRB0-3
PRC2-3

ISTI

Std./O.D.

ISTI

Std./O.D.

I/O STI

Std./O.D.

I/O STI

Std./O.D.

I - RM mode Oscillator input
I - First Power supply during operation

O - Current Output of Audio

I - First Circuit Ground Potential
I - Second Circuit Ground Potential

O - Enter Test Mode. ( TEST = High )

I - Second Power supply during operation

O Std./O.D. Output type with standard or Open-Drain output

ISTI

Std./O.D.

Input port with programmable strong pull-low or weak pull-low or fix­input-floating capability
Input port with programmable strong pull-low or weak pull-low or fix­input-floating capability

Mask option selected as an external RESET pin with weak pull-low
capability

I/O port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Output type with standard or Open-Drain output
I/O port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Output type with standard or Open-Drain output

Mask option selected as an external RESET pin with weak pull-low
capability

Input port with programmable strong pull-low or weak pull-low or fix­input-floating capability

1.3 Application circuit

4

Rev 1.0

1.4 Bonding Diagram

ASM8412CB

X= 1540+80 (um)

Y=3380+80 (um)

19 18 17 16 15 14 13 12

RC3 RC2 RC1 RC0 GND2 VDD2 TEST OSC

( 256K x 10-bit ) Block ROM

ASM8412CB

RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 RB3

1 2 3 4 5 6 7 8 9 10 11

Substrate must be connected to GND.

ASM8412CB Pad Location Chip Size: X= 1540+80 (um), Y=3380+80 (um)
PAD # PAD Name X Y PAD # PAD Name X Y

1 RA3 -682.16 -1575.24 11 RB3 674.88 -1575.24
2 RA2 -559.84 -1575.24 12 OSC 633.56 1606.56
3 RA1 -437.52 -1575.24 13 TEST 432.48 1606.56
4 RA0 -315.2 -1575.24 14 VDD2 273.16 1606.56
5 VDD1 -191.28 -1575.24 15 GND2 134.68 1606.56
6 COUT 71.12 -1575.24 16 RC0 -51.76 1606.56
7 GND1 189.52 -1575.24 17 RC1 -248.4 1606.56
8 RB0 307.92 -1575.24 18 RC2 -454.24 1606.56
9 RB1 430.24 -1575.24 19 RC3 -650.88 1606.56

10 RB2 552.56 -1575.24

5

Rev 1.0

1.5 DC Characteristics for ASM8412CB

ASM8412CB

SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION

VDD OPERATING VOLTAGE 2.4 3 5.0 V depending on Freq.

Isb STANDBY

Iop

Iih

Ioh OUTPUT HIGH CURRENT

Iol OUTPUT LOW CURRENT

Cout

dF/F

dF/F Fosc VARIATION -20 20 %

SUPPLY

CURRENT

INPUT CURRENT

/Internal pull low

DA CURRENT OUT

(FULL SCALE)

FREQUENCY

OPERATING

STABILITY

31
51
32
57
33
59

5-5.2

3-3
5-8
37
520
34

55.2

-10 10 %

uA

mA

uA

mA 4MHz, RM

(IO Ports with weak

Rosc=180k, 4MHz

FIGURE 1.3 : Frequency Range for Rosc in RM mode

4MHz, RM

in HALT Mode

4MHz, RM

IO Floating

4MHz, RM

in HALT Mode

pull-high pull-low)

(IO ports)

Fosc(3v- 2.4v)

Fosc (3v)
VDD=3V,

Resistor(k ohm) 300 200 150 110

3v Freq.(MHz) 2.66 3.8 4.99 6.4

Rosc & Freq.

8

6

6.4

4.99

4

Freq. MHz

2

3.8

2.66

0

0 100 200 300 400

Rosc k ohm

6

Rev 1.0