Datasheet ASM6312C Datasheet (APLUS)

PLUS MAKE YOUR PRODUCTION A-PLUS

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ASM6312C

DATA SHEET

PLUS INTEGRATED CIRCUITS INC.

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Address:

3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,

Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.

TEL: [phone]

FAX: [phone]

WEBSITE : http: //www.aplusinc.com.tw

Sales E-mail: Mr. Jason

[e-mail]

Technology E-mail: Mr. George

[e-mail]

ASM6312C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

ASM6312C

1.0 General Description

The ASM6312C is very low cost voice synthesizer with 4-bit microprocessor. It has various features

including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice

synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function

can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction

pipeline. It allows all instructions to be executed in a single cycle, except for program branches and

data table read instructions (which need two instruction cycles).

1.1 Feature



Single power supply can operate from 2.4V through 5V



Internal Program ROM: 4K x 10-bit



1 sets of 18-bit DPR can access up to 192K x 10 bits data memory space



Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh



I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)



On-chip clock generator: Resistive Clock Drive(RM)



Timer: 1

• Timer0: a 9-bit auto-reload timer/counter



Stack: 2-level subroutine nesting



HALT and Release from HALT function to reduce power consumption



Watch Dog Timer (WDT)



Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles



Number of instruction: 22

1

Rev 1.0

FIGURE 1.1 : Block Diagram of ASM6312C

(12)

(4)

)

ASM6312C

Data Bus[3:0]

(ADDR[17:12])

=000000b

COUT

PCLATCH(8)

PCH(8) PCL(4)

DPR3,2,1

DLATCH(10)

Data Bus[3:0]

Accumlator

ALU(4)

Register(4)

One-Channel

( Voice synthesizer )

COUT

PC[11:0]

ADDR[17:0]

DPR[17:0]

P1,P2,P3,P4

enter test mode

Reset Chip

Reset Chip

0

1

ROM_Data[9:0]

Immediate(4

Stack

(2-Level)

ROM_ADDR[17:0]

Program

(Data)

ROM

SRAM

(96 x 4)

00h-1Fh
40h-7Fh

Clock Generator

Test select

Power on Reset

RESET pin

Instruction Bus [9:0]

Instruction Bus [9:0]

Timer0(9)

OSC

VDD/GND

PRA0

ROM Latch

Instruction

Latch

Instruction

Decoder

Control Signal

Instruction Bus [9:0]

PRA(4)
PRB(4)
PRC(4)

weak or strong
p ull-low for PR A,
PRB, PRC

PRASL(4)

2

Rev 1.0

FIGURE 1.2 : External ROM Map of ASM6312C

g

ASM6312C

PC[11:0]

12bit x 2 STACK

00000h-2FFFFh

18-bit Data Pointer

Reserved for Testing

ram and data ROM

Pro

Data ROM

Reset Vector

00000h

00080h

00080h-003FFh

00400h

00000h-00FFFh

00FFFh(4K)

2FFFFh(192Kx10-bits)

3

Rev 1.0

1.2 Pin-Out

ASM6312C

ASM6312C Pin-Out

PRC1

PRC0/RESET

PRA3-1

PRA0/RESET

OSC
VDD1
COUT
GND1
GND2
TEST
VDD2
PRB0-3
PRC2-3

ISTI

Std./O.D.

ISTI

Std./O.D.

I/O STI

Std./O.D.

I/O STI

Std./O.D.

I - RM mode Oscillator input
I - First Power supply during operation

O - Current Output of Audio

I - First Circuit Ground Potential
I - Second Circuit Ground Potential

O - Enter Test Mode. ( TEST = High )

I - Second Power supply during operation

O Std./O.D. Output type with standard or Open-Drain output

ISTI

Std./O.D.

Input port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Input port with programmable strong pull-low or weak pull-low or fix-input­floating capability

Mask option selected as an external RESET pin with weak pull-low capability

I/O port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Output type with standard or Open-Drain output
I/O port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Output type with standard or Open-Drain output

Mask option selected as an external RESET pin with weak pull-low capability

Input port with programmable strong pull-low or weak pull-low or fix-input­floating capability

1.3 Application circuit

4

Rev 1.0

1.4 Bonding Diagram

ASM6312C

X=1540+100 (um)

Y=2850+100 (um)

19 18 17 16 15 14 13 12

RC3 RC2 RC1 RC0 GND2 VDD2 TEST AOSC

( 192K x 10-bit ) Block ROM

ASM6312C

RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 RB3

1 2 3 4 5 6 7 8 9 10 11

ASM6312C Pad Location

PAD # PAD Name X Y PAD # PAD Name X Y

1RA3

2RA2

3RA1

4RA0

5 VDD1

6COUT

7GND1

8RB0

9RB1

10 RB2

-682.16 -1307.72

-559.84 -1307.72

-437.52 -1307.72

-315.2 -1307.72

-191.28 -1307.72

71.12 -1307.72

189.52 -1307.72

307.92 -1307.72

430.32 -1307.72

552.56 -1307.72

Chip Size: X=1540+100 (um), Y=2850+100 (um)

11 RB3

12 AOSC

13 TEST

14 VDD2

15 GND2

16 RC0

17 RC1

18 RC2

19 RC3

667.68 -1307.72

633.56 1339.04

432.48 1339.04

273.16 1339.04

134.68 1339.04

-51.76 1339.04

-248.4 1339.04

-454.24 1339.04

-650.88 1339.04

5

Rev 1.0

1.5 DC Characteristics for ASM6312C

ASM6312C

SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION

VDD

Isb

Iop

Iih

Ioh

Iol

dF/F

dF/F Fosc VARIATION -20 20 %

OPERATING

VOLTAGE

SUPPLY

CURREN

T

INPUT CURRENT

/Internal pull low

OUTPUT HIGH

CURRENT

OUTPUT LOW

CURRENT

FREQUENCY

STABILITY

STANDBY

OPERATING

2.4 3 5 V depending on Freq.

31
51
32
57
33
59

5 -5.2

3-3
5-8
37
520

-10 10 %

uA

mA

uA

mA

4MHz, RM

in HALT Mode

4MHz, RM
IO Floating

4MHz, RM

in HALT Mode

(IO Ports with

weak pull-high

4MHz, RM

(IO ports)

Fosc(3v)-

Fosc(2.4v)

VDD=3V,

Rosc=220k, 4MHz

pull-low)

Fosc (3v)

FIGURE 1.3 : Frequency Range for Rosc in RM mode

Resistor(k ohm) 330 220 200 150

3v Freq.(MHz)

8

6

4

Freq. MHz

2

0

0 100 200 300 400

2.63

3.91

Rosc & Freq.

5.93

Rosc k ohm

4.43

4.43 5.93

3.91

2.63

6

Rev 1.0