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6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C.
http://www.aplusinc.com.tw
台北市大安路一段75巷7號6F-3 TEL:886-2-27818277 FAX:886-2-27815779
ASM5206C/6306C
DATA SHEET
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ASM5206C/6306C –
ASM5206C/6306CASM5206C/6306CASM5206C/6306CASM5206C/6306CASM5206C/6306C
VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description
The ASM5206C/6306C is very low cost voice synthesizer with 4-bit microprocessor. It has various
features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog
timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS
technology and halt function can minimize power dissipation. Its architecture is similar to RISC,
with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,
except for program branches and data table read instructions (which need two instruction
cycles).
1.1 Feature
Single power supply can operate from 2.4V through 5.5V
Internal Program ROM: 4K x 10-bit
1 sets of 18-bit DPR can access up to 192K x 10 bits data memory space
Data Registers:
• 64 x 4-bit data RAM (00-1Fh plus 40h-5Fh)
• Unbanked special function registers (SFR) range: 20h-3Fh
I/O Ports:
• PRA: 4-bit I/O Port A (2Bh)
• PRB: 2-bit Output Port B (2Dh)
On-chip clock generator: Resistive Clock Drive(RM)
Timer: 1
• Timer0: a 9-bit auto-reload timer/counter
Stack: 2-level subroutine nesting
HALT and Release from HALT function to reduce power consumption
Watch Dog Timer (WDT)
Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
Number of instruction: 22
The Voice function can be implemented by microprocessor instruction
• One 8-bit COUT output for ASM5206C/6306C
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Rev 1.0
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FIGURE 1.1 : Block Diagram of ASM5206C/6306C
(12)
]
(4)
)
ASM5206C/6306C
Data Bus[3:0]
(ADDR[17:12])
=00000b
COUT
PCLATCH(8)
PCH(8) PCL(4)
DPR3,2,1
DLATCH(10)
Data Bus[3:0
Accumlator
ALU(4)
Register(4)
One-Channel
( Voice synthesizer )
COUT
PC[11:0]
ADDR[17:0]
DPR[17:0]
P1,P2,P3,P4
enter test mode
Reset Chip
Reset Chip
ROM_Data[9:0]
Immediate(4
Stack
(2-Level)
ROM_ADDR[17:0]
Program
(Data)
ROM
SRAM
(64 x 4)
00h-1Fh
40h-5Fh
Clock Generator
Tes t s el ect
Power on Reset
RESET pin
Instruction Bus [9:0]
Instruction Bus [9:0]
Timer0(9)
OSC
VDD/GND
PRA0
ROM Latch
Instruction
Latch
Instruction
Decoder
Control Signal
Instruction Bus [9:0]
PRA(4)
PRB(2)
weak or strong
pull-low for PRA,
PRB, PRC
PRASL(4)
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Rev 1.0
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FIGURE 1.2 : External ROM Map of ASM5206C/6306C
g
ASM5206C/6306C
00000h-2FFFFh
12bit x 2 STACK
17-bit Data Pointer
Reserved for Testing
ram and data ROM
Pro
PC[11:0]
Reset Vector
00000h
00080h
00080h-003FFh
00400h
00000h-00FFFh
00FFFh(4K)
Data ROM
2FFFFh(192Kx10-bits)
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1.2 Pin-Out
ASM5206C/6306C
ASM5206C/6306C Pin-Out
VDD
PRA3-1
PRA0/RESET
OSC
COUT
GND
TEST
PRB0-1
I - Power supply during operation
I/O STI
Std./O.D.
I/O STI
Std./O.D.
I - RM mode Oscillator input
O - Current Output of Audio
I - Circuit Ground Potential
O - Enter Test Mode. ( TEST = High )
O Std./O.D. Output type with standard or Open-Drain output
1.3 Application circuit
I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability
Output type with standard or Open-Drain output
I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability
Output type with standard or Open-Drain output
Mask option selected as an external RESET pin with weak pull-low capability
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Rev 1.0
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1.4 Bonding Diagram
ASM5206C/6306CASM5206C/6306C
192K x 10 bit ROM
1
2
3
ASM5206C/6306C
CHIP SIZE: X= 1550+80(um) , Y= 2700+80(um)
6 7 8 9 5 4
11
10
Substrate must be connected to GND.
ASM5206C/6306C Pad Location CHIP SIZE: X= 1550+80(um) , Y= 2700+80(um)
PAD # PAD Name X Y PAD # PAD Name X Y
1 RA3 -664.92 -944.32 7 TEST_PAD 105.44 -1269
2 RA2 -664.92 -1072.44 8 COUT 303.96 -1269
3 RA1 -662.64 -1269 9 VDD 683.04 -1269
4 RA0 -468.24 -1269 10 RB0 664.92 -1068
5 OSC -281.04 -1269 11 RB1 664.92 -949.6
6 GND -111.72 -1269
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1.5 DC Characteristics for ASM5206C/6306C
ASM5206C/6306C
SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION
VDD OPERATING VOLTAGE 2.4 3 5.5 V depending on Freq.
Isb STANDBY
Iop
Iih
Ioh OUTPUT HIGH CURRENT
Iol OUTPUT LOW CURRENT
Cout
dF/F
dF/F Fosc VARIATION -20 20 %
SUPPLY
CURRENT
INPUT CURRENT
/Internal pull low
DA CURRENT OUT
(FULL SCALE)
FREQUENCY
OPERATING
STABILITY
31
51
32
57
33
59
5-5.2
3-3
5-8
37
520
34
55.2
uA
mA
uA
mA 4MHz, RM
-10 10 %
4MHz, RM
in HALT Mode
4MHz, RM
IO Floating
4MHz, RM
in HALT Mode
(IO Ports with weak
pull-high pull-low)
(IO ports)
Fosc(3v- 2.4v)
Fosc (3v)
VDD=3V,
Rosc=820k, 4MHz
FIGURE 1.3 : Frequency Range for Rosc in RM mode
Resistor(k ohm) 1000 820 560 470
3v Freq.(MHz) 3.66 4 6.2 7.16
Rosc & Freq.
8
7.16
6
6.2
4
Freq. MHz
2
0
0 200 400 600 800 1000 1200
Rosc k ohm
4
3.66
6
Rev 1.0
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