Datasheet ASM34012CB Datasheet (APLUS)

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PLUS MAKE YOUR PRODUCTION A-PLUS

ASM34012C

DATA SHEET

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PLUS INTEGRATED CIRCUITS INC.

Address:

3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,

Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.

TEL: [phone]

FAX: [phone]

WEBSITE : http: //www.aplusinc.com.tw

Sales E-mail: Mr. Jason

[e-mail]

Technology E-mail: Mr. George

[e-mail]

ASM34012CB

–

VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

1.0 General Description

The ASM34012CB is very low cost voice synthesizer with 4-bit microprocessor. It has various

features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog

timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS

technology and halt function can minimize power dissipation. Its architecture is similar to RISC,

with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,

except for program branches and data table read instructions (which need two instruction

cycles).

1.1 Feature



Single power supply can operate from 2.4V through 5.5V



Internal Program ROM: 4K x 10-bit



1 sets of 20-bit DPR can access up to 1024K x 10 bits data memory space



Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh



I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)



On-chip clock generator: Resistive Clock Drive(RM)



Timer: 1

• Timer0: a 9-bit auto-reload timer/counter



Stack: 2-level subroutine nesting



HALT and Release from HALT function to reduce power consumption



Watch Dog Timer (WDT)



Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles



Number of instruction: 22



The Voice function can be implemented by microprocessor instruction

• One 8-bit COUT output for ASMxxxxx

FIGURE 1.1 : Block Diagram of ASM34012CB

COUT

OSC

VDD/GND

ROM

PC[11:0]

ROM Latch

Instruction

Latch

Instruction

Decoder

PCH(8) PCL(4)

PCLATCH(8)

DPR3,2,1

Program

DLATCH(10)

Clock Generator

Power on Reset

Tes t s el ect

P1,P2,P3,P4

enter test mode

Timer0(9)

Reset Chip

Stack

(12)

Data Bus[3:0

]

Instruction Bus [9:0]

ROM_ADDR[19:0]

ROM_Data[9:0]

Data Bus[3:0]

Control Signal

ADDR[19:0]

=00000000b

(ADDR[19:12])

PRASL(4)

weak or strong
pull-low for PRA,

(Data)

Instruction Bus [9:0]

Instruction Bus [9:0]

( Voice synthesizer )

One-Channel

SRAM

(96 x 4)

40h-7Fh

(2-Level)

ALU(4)

Register(4)

Accumlator

(4)

Immediate(4

)

DPR[19:0]

RESET pin

Reset Chip

PRA0

00h-1Fh

PRA(4)
PRB(4)
PRC(4)

PRB, PRC

COUT

FIGURE 1.2 : External ROM Map of ASM34012CB

Data ROM

12bit x 2 STACK

Reset Vector

PC[11:0]

FFFFFh(1024Kx10-bits)

00FFFh(4K)

00000h-00FFFh

Pro

g

ram and data ROM

20-bit Data Pointer

00000h

00400h

Reserved for Testing

00080h

00080h-003FFh

00000h-FFFFFh

1.2 Pin-Out

ASM34012CB Pin-Out

VDD3

I - Third Power supply during operation

PRC1

I STI

Std./O.D.

Input port with programmable strong pull-low or weak pull-low or
fix-input-floating capability

PRC0/RESET

I STI

Std./O.D.

Input port with programmable strong pull-low or weak pull-low or
fix-input-floating capability

Mask option selected as an external RESET pin with weak pull-low capability

PRA3-1

I/O

STI

Std./O.D.

I/O port with programmable strong pull-low or weak pull-low or
fix-input-floating capability
Output type with standard or Open-Drain output

PRA0/RESET

I/O STI

Std./O.D.

I/O port with programmable strong pull-low or weak pull-low or
fix-input-floating capability
Output type with standard or Open-Drain output

Mask option selected as an external RESET pin with weak pull-low capability

OSC

I - RM mode Oscillator input

VDD1

I - First Power supply during operation

COUT

O

-

Current Output of Audio

GND1

I - First Circuit Ground Potential

GND2

I

-

Second Circuit Ground Potential

TEST

O - Enter Test Mode. ( TEST = High )

VDD2

I - Second Power supply during operation

PRB0-3

O Std./O.D. Output type with standard or Open-Drain output

PRC2-3

I STI

Std./O.D.

Input port with programmable strong pull-low or weak pull-low or
fix-input-floating capability

GND3

I - Third Circuit Ground Potential

1.3 Application circuit

1.4 Bonding Diagram

Substrate must be connected to GND.

ASM34012CB Pad Location Chip Size: X= 3090 + 100 (um) , Y= 5540 + 80 (um)
PAD # PAD Name X Y PAD # PAD Name X Y

1 VDD3 -1445.96 -2656.48 12 GND2 118.72 -2650.96
2 PRC1 -1325.24 -2656.48 13 TEST 319.68 -2656.48
3 PRC0 -1202.92 -2656.48 14 VDD2 575.32 -2656.48
4 PRA3 -1080.6 -2656.48 15 PRB0 714.48 -2656.48
5 PRA2 -958.28 -2656.48 16 PRB1 836.8 -2656.48
6 PRA1 -835.96 -2656.48 17 PRB2 959.12 -2656.48
7 PRA0/RESET -713.64 -2656.48 18 PRB3 1081.44 -2656.48
8 OSC -591.32 -2656.48 19 PRC2 1203.76 -2656.48

9 VDD1 -414.36 -2656.48 20 PRC3 1326.08 -2656.48
10 COUT -162.24 -2656.48 21 GND3 1449.36 -2656.48
11 GND1 38.72 -2650.96

3

ASM34012CB

(256K x 10 bit) x 4-Block ROM

4 5 6 7 8 9 10

11 12

13 18 17 16 15 14 2 1 19 20 21

CHIP SIZE: X= 3090 + 100 (um), Y= 5540 + 80 (um)

1.5 DC Characteristics for ASMxxxxx

SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION

VDD OPERATING VOLTAGE 2.4 3 5.5 V depending on Freq.

3 1

Isb STANDBY

5 1

uA

4MHz, RM

in HALT Mode

3 2

Iop

SUPPLY

CURRENT

OPERATING

5 7

mA

4MHz, RM

IO Floating
3 3
5 9

Iih

INPUT CURRENT

/Internal pull low

5 -5.2

uA

4MHz, RM

in HALT Mode

(IO Ports with weak

pull-high pull-low)

3 -3

Ioh OUTPUT HIGH CURRENT

5 -8
3 7

Iol OUTPUT LOW CURRENT

5 20
3 4

Cout

DA CURRENT OUT

(FULL SCALE)

5 5.2

mA

4MHz, RM

(IO ports)

dF/F

FREQUENCY

STABILITY

-10 10 %

Fosc(3v- 2.4v)

Fosc (3v)

dF/F Fosc VARIATION -20 20 %

VDD=3V,

Rosc=760k, 4MHz

FIGURE 1.3 : Frequency Range for Rosc in RM mode

Resistor(k ohm) 1000 760 560 390

3v Freq.(MHz) 3.18 4.1 5.4 7.69

Rosc & Freq.

3.18

4.1

5.4

7.69

0

2

4

6

8

10

0 100 200 300 400 500 600 700 800 900 1000 1100

Rosc k ohm

Freq. MHz