Datasheet ASM2012C Datasheet (APLUS)

6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C.

http://www.aplusinc.com.tw

台北市大安路一段75巷7號6F-3 TEL:[phone] FAX:[phone]

ASM2012C

DATA SHEET

ASM2012C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

ASM2012C

1.0 General Description

The ASM2012C is very low cost voice synthesizer with 4-bit microprocessor. It has various features
including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice
synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function
can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction
pipeline. It allows all instructions to be executed in a single cycle, except for program branches and
data table read instructions (which need two instruction cycles).

1.1 Feature

u Single power supply can operate from 2.4V through 5V
u Internal Program ROM: 4K x 10-bit
u 1 sets of 16-bit DPR can access up to 64K x 10 bits data memory space
u Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh
u I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)

u On-chip clock generator: Resistive Clock Drive(RM)
u Timer: 1

• Timer0: a 9-bit auto-reload timer/counter

u Stack: 2-level subroutine nesting
u HALT and Release from HALT function to reduce power consumption
u Watch Dog Timer (WDT)
u Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
u Number of instruction: 22

1

Rev 1.0

FIGURE 1.1 : Block Diagram of ASM2012C

Instruction

Instruction

PCH(8)

PCL(4)

Clock Generator

Stack(12)

Data Bus[3:0]

Accumlator(4)

Immediate(4)

ASM2012C

Data Bus[3:0]

(ADDR[15:12])

=0000b

COUT

PCLATCH(8)

DPR3,2,1

DLATCH(10)

ALU(4)

Register(4)

One-Channel

( Voice synthesizer )

COUT

PC[11:0]

ADDR[15:0]

DPR[15:0]

P1,P2,P3,P4

enter test mode

Reset Chip
Reset Chip

(2-Level)

ROM_ADDR[15:0]

ROM_Data[9:0]

SRAM

(96 x 4)

00h-1Fh
40h-7Fh

Test select

Power on Reset

RESET pin

Program

(Data)

ROM

Instruction Bus [9:0]

Instruction Bus [9:0]

Timer0(9)

OSC

VDD/GND

PRA0

ROM Latch

Latch

Decoder

Control Signal

Instruction Bus [9:0]

PRA(4)
PRB(4)
PRC(4)

weak or strong
pull-low for PRA,

PRB, PRC

PRASL(4)

2

Rev 1.0

FIGURE 1.2 : External ROM Map of ASM2012C

ASM2012C

PC[11:0]

12bit x 2 STACK

00000h-0FFFFh

16-bit Data Pointer

Reserved for Testing

Program and data ROM

Data ROM

Reset Vector

00000h

00080h

00080h-003FFh

00400h

00000h-00FFFh

00FFFh(4K)

0FFFFh(64Kx10-bits)

3

Rev 1.0

1.2 Pin-Out

ASM2012C

ASM2012C Pin-Out

PRC1 I STI

Std./O.D.

PRC0/RESET

PRA3-1 I/O STI

PRA0/RESET

OSC I - RM mode Oscillator input
VDD1 I - First Power supply during operation
COUT O - Current Output of Audio
GND1 I - First Circuit Ground Potential
GND2 I - Second Circuit Ground Potential
TEST O - Enter Test Mode. ( TEST = High )
VDD2 I - Second Power supply during operation
PRB0-3 O Std./O.D. Output type with standard or Open-Drain output
PRC2-3 I STI

I STI

Std./O.D.

Std./O.D.

I/O STI

Std./O.D.

Std./O.D.

Input port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Input port with programmable strong pull-low or weak pull-low or fix-input­floating capability

Mask option selected as an external RESET pin with weak pull-low capability

I/O port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Output type with standard or Open-Drain output
I/O port with programmable strong pull-low or weak pull-low or fix-input­floating capability
Output type with standard or Open-Drain output

Mask option selected as an external RESET pin with weak pull-low capability

Input port with programmable strong pull-low or weak pull-low or fix-input­floating capability

1.3 Application circuit

4

Rev 1.0

1.4 Bonding Diagram

ASM2012C

19 18 17 16 15 14 13 12

RC3 RC2 RC1 RC0 GND2 VDD2 TEST AOSC

( 64K x 10-bit ) Block ROM

ASM2012C

RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 RB3

1 2 3 4 5 6 7 8 9 10 11

ASM2012C Pad Location Chip Size: X=1540+80 (um), Y=1780+80 (um)

PAD # PAD Name X Y PAD # PAD Name X Y

1 RA3
2 RA2
3 RA1
4 RA0
5 VDD1
6 COUT
7 GND1
8 RB0
9 RB1

10 RB2

-682.16 -772.68

-559.84 -772.68

-437.52 -772.68

-315.2 -772.68

-191.28 -772.68

71.12 -772.68

189.52 -772.68

307.92 -772.68

430.24 -772.68

552.56 -772.68

11 RB3
12 AOSC
13 TEST
14 VDD2
15 GND2
16 RC0
17 RC1
18 RC2
19 RC3

667.68 -772.68

633.56 804

432.48 804

273.16 804

134.68 804

-51.76 804

-248.4 804

-454.24 804

-650.88 804

5

Rev 1.0

1.5 DC Characteristics for ASM2012C

ASM2012C

SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION

VDD

Isb

Iop

Iih

Ioh

Iol

dF/F

dF/F Fosc VARIATION -20 20 %

OPERATING

VOLTAGE

SUPPLY

CURREN

T OPERATING

INPUT CURRENT

/Internal pull low

OUTPUT HIGH

CURRENT

OUTPUT LOW

CURRENT

FREQUENCY

STABILITY

STANDBY

2.4 3 5 V depending on Freq.

3 1

5 1

3 2

5 7

3 3

5 9

5 -5.2

3 -3

5 -8

3 7

5 20

-10 10 %

uA

mA

uA

mA

4MHz, RM

in HALT Mode

4MHz, RM
IO Floating

4MHz, RM

in HALT Mode

(IO Ports with

weak pull-high

4MHz, RM

Fosc(2.4v)

VDD=3V,

Rosc=220k, 4MHz

pull-low)

(IO ports)

Fosc(3v)-

Fosc (3v)

FIGURE 1.3 : Frequency Range for Rosc in RM mode

Resistor(k ohm) 330 220 200 150

3v Freq.(MHz) 2.68 4.11 4.7 5.94

Rosc & Freq.

8
6
4

Freq. MHz

2
0

0 100 200 300 400

5.94

Rosc k ohm

4.7

4.11

2.68

6

Rev 1.0