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PLUS MAKE YOUR PRODUCTION A-PLUS
A
ASM12712C
DATA SHEET
PLUS INTEGRATED CIRCUITS INC.
A
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
TEL: 886-2-2782-9266
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
Sales E-mail: Mr. Jason
sales@aplusinc.com.tw
Technology E-mail: Mr. George
service@aplusinc.com.tw
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ASM12712C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
ASM12712C
1.0 General Description
The ASM12712C is very low cost voice synthesizer with 4-bit microprocessor. It has various features
including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice
synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function
can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction
pipeline. It allows all instructions to be executed in a single cycle, except for program branches and
data table read instructions (which need two instruction cycles).
1.1 Feature
Single power supply can operate from 2.4V through 5V
Internal Program ROM: 4K x 10-bit
1 sets of 19-bit DPR can access up to 512K x 10 bits data memory space
Data Registers:
• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)
• Unbanked special function registers (SFR) range: 20h-3Fh
I/O Ports:
• PRA: 4-bit I/O Port A (2Bh)
• PRB: 4-bit Output Port B (2Dh)
• PRC: 4-bit Input Port C (2Fh)
On-chip clock generator: Resistive Clock Drive(RM)
Timer: 1
• Timer0: a 9-bit auto-reload timer/counter
Stack: 2-level subroutine nesting
HALT and Release from HALT function to reduce power consumption
Watch Dog Timer (WDT)
Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
Number of instruction: 22
The Voice function can be implemented by microprocessor instruction
• One 8-bit COUT output for ASMxxxxx
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FIGURE 1.1 : Block Diagram of ASM12712C
(12)
]
(4)
)
ASM12712C
Data Bus[3:0]
(ADDR[18:12])
=0000000b
COUT
PCLATCH(8)
PCH(8) PCL(4)
DPR3,2,1
DLATCH(10)
Data Bus[3:0
Accumlator
ALU(4)
Register(4)
One-Channel
( Voice synthesizer )
COUT
PC[11:0]
ADDR[18:0]
DPR[18:0]
P1,P2,P3,P4
enter test mode
Reset Chip
Reset Chip
ROM_Data[9:0]
Immediate(4
Stack
(2-Level)
ROM_ADDR[18:0]
Program
(Data)
ROM
SRAM
(96 x 4)
00h-1Fh
40h-7Fh
Clock Generator
Tes t s el ect
Power on Reset
RESET pin
Instruction Bus [9:0]
Instruction Bus [9:0]
Timer0(9)
OSC
VDD/GND
PRA0
ROM Latch
Instruction
Latch
Instruction
Decoder
Control Signal
Instruction Bus [9:0]
PRA(4)
PRB(4)
PRC(4)
weak or strong
pull-low for PRA,
PRB, PRC
PRASL(4)
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FIGURE 1.2 : External ROM Map of ASM12712C
g
ASM12712C
PC[11:0]
12bit x 2 STACK
00000h-7FFFFh
19-bit Data Pointer
Reserved for Testing
ram and data ROM
Pro
Data ROM
Reset Vector
00000h
00080h
00080h-003FFh
00400h
00000h-00FFFh
00FFFh(4K)
7FFFFh(512Kx10-bits)
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1.2 Pin-Out
ASM12712C
ASM12712C Pin-Out
VDD3
PRC1
PRC0/RESET
PRA3-1
PRA0/RESET
OSC
VDD1
COUT
GND1
GND2
TEST
VDD2
PRB0-3
PRC2-3
GND3
I - Third Power supply during operation
ISTI
Std./O.D.
ISTI
Std./O.D.
I/O STI
Std./O.D.
I/O STI
Std./O.D.
I - RM mode Oscillator input
I - First Power supply during operation
O - Current Output of Audio
I - First Circuit Ground Potential
I - Second Circuit Ground Potential
O - Enter Test Mode. ( TEST = High )
I - Second Power supply during operation
O Std./O.D. Output type with standard or Open-Drain output
ISTI
Std./O.D.
I - Third Circuit Ground Potential
Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability
Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability
Mask option selected as an external RESET pin with weak pull-low capability
I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability
Output type with standard or Open-Drain output
I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability
Output type with standard or Open-Drain output
Mask option selected as an external RESET pin with weak pull-low capability
Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability
1.3 Application circuit
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1.4 Bonding Diagram
ASM12712C
X= 3090 + 100 (um)
Y= 3140 + 100 (um)
3
4 5 6 7 8 9 10 1112 13 1817161514 2 1 19 20 21
(256K x 10 bit) x 2-Block ROM
ASM12712C
CH IP SIZE: X= 3090 + 100 (um), Y= 314 0 + 100 (u m)
ASM12712C Pad Location
PAD# PAD Name X Y PAD # PAD Name X Y
Chip Size: X= 3090 + 100 (um) , Y= 3140 + 100 (um)
1 VDD3 -1445.96 -1456.08 12 GND2 118.72 -1450.56
2 RC_PAD[1] -1325.24 -1456.08 13 TEST_PAD 319.68 -1456.08
3 RC_PAD[0] -1202.92 -1456.08 14 VDD2 575.32 -1456.08
RA_PAD[3]
4
-1080.6 -1456.08 15 RB[0] 714.48 -1456.08
5 RA_PAD[2] -958.28 -1456.08 16 RB[1] 836.8 -1456.08
6 RA_PAD[1] -835.96 -1456.08 17 RB[2] 959.12 -1456.08
RA_PAD[0]/RESET
7
-713.64 -1456.08 18 RB[3] 1081.44 -1456.08
8 AOSC_PAD -591.32 -1456.08 19 RC_PAD[2] 1203.76 -1456.08
9 VDD1 -414.36 -1456.08 20 RC_PAD[3] 1326.08 -1456.08
10 ACOUT -162.24 -1456.08 21 GND3 1449.36 -1456.08
11 GND1 38.72 -1450.56
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1.5 DC Characteristics for ASMXXXX
ASM12712C
SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION
VDD
Isb
Iop
Iih
Ioh
Iol
dF/F
dF/F Fosc VARIATION -20 20 %
OPERATING
VOLTAGE
SUPPLY
STANDBY
CURREN
T
OPERATING
INPUT CURRENT
/Internal pull low
OUTPUT HIGH
CURRENT
OUTPUT LOW
CURRENT
FREQUENCY
STABILITY
2.4 3 5 V depending on Freq.
31
51
32
57
uA
mA
33
59
uA
5 -5.2
4MHz, RM
in HALT Mode
4MHz, RM
IO Floating
4MHz, RM
in HALT Mode
(IO Ports with
weak pull-high
3-3
5-8
37
mA
4MHz, RM
(IO ports)
520
Fosc(3v)-
-10 10 %
Fosc(2.4v)
VDD=3V,
Rosc=740k, 4MHz
pull-low)
Fosc (3v)
FIGURE 1.3 : Frequency Range for Rosc in RM mode
Resistor(k ohm) 1200 1000 820 470
3v Freq.(MHz)
8
6
4
Freq. MHz
2
0
0 200 400 600 800 1000 1200 1400
2.47 3.04 3.31 6.25
Rosc & Freq.
6.25
Rosc k ohm
3.31
3.04
2.47
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