The ASM1232LP/LPS is a fully integrated microprocessor
supervisor. It can halt and restart a “hung-up” microprocessor,
restart a microprocessor after a power failure. It has a
watchdog timer and external reset override.
A precision temperature-compensated reference and
comparator circuits monitor the 5V, V
During power-up or when the VCC power supply falls outside
selectable tolerance limits, both RESET and RESET become
active. When V
signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to
stabilize. The trip point tolerance signal, TOL, selects the trip
level tolerance to be either 5% or 10%.
rises above the threshold voltage, the reset
CC
input voltage status.
CC
ASM1232LP/LPS
•Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin
DIP and 8-pin Micro SO packages
•Wide operating temperature -40°C to +85°C (N suffixed
devices)
Applications
•Microprocessor Systems
•Computers
•Controllers
•Portable Equipment
•Intelligent Instuments
•Automotive Systems
Typical Operating Circuit
Each device has both a push-pull, active HIGH reset output
and an open drain active LOW reset output. A debounced
manual reset input, PBRST
minimum period of 250ms.
There is a watchdog timer to stop and restart a microprocessor
that is “hung-up”. The watchdog timeouts periods are
selectable: 150ms, 610ms and 1200ms. If the ST input is not
strobed LOW before the time-out period expires, a reset is
generated.
Devices are available in 8-pin DIP, 16-pin SO and compact 8-
pin MicroSO packages.
, activates the reset outputs for a
Key Features
•5V supply monitor
•Selectable watchdog period
•Debounce manual push-button reset input
•Precision temperature-compensated voltage reference
and comparator.
•Power-up, power-down and brown out detection
•250ms minimum reset time
•Active LOW open drain reset output and active HIGH
push-pull output
•Selectable trip point tolerance: 5% or 10%
Block Diagram
V
CC
TOL
PBRST
TD
ST
ASM1232LP/LPS
TD
Tolerance Selection
Reference
Push Button
Debounce
Voltage Sense
Comparators
Watchdog Transition
Detector
V
CC
40kΩ
GND
ST
RESET
TOL
+5V
10kΩ
I/O
RESET
ASM1232LP/LPS
+
-
Reset &
Watchdog Timer
µP
RESET
RESET
Alliance Semiconductor
2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
GND
Page 2
January 2005
rev 1.5
Pin Configuration
ASM1232LP/LPS
PBRST
Pin Description
Pin #
8-Pin Package
12PBRSTDebounced manual pushbutton RESET input.
24TD
DIP/SO/MicroSO
1
2
TD
3
TOL
GND
ASM1232LPU
4
16-Pin Package
ASM1232LP
ASM1232LPS-2
Pin #
8
7
6
5
Pin
Name
V
CC
ST
RESET
RESET
SO
NC
1
NC
TD
NC
TOL
NC
GND
2
3
4
ASM1232LPS
5
6
7
8
Function
= 150ms for TD = GND, tTD = 610ms
TD
PBRST
Watchdog time delay selection. (t
for TD=Open, and tTD = 1200ms for TD = VCC).
15
14
12
11
10
16
13
9
NC
V
CC
NC
ST
NC
RESET
NC
RESET
36TOL
48GNDGround.
59RESET
611RESET
713ST
815
10,12,14,16
1,3,5,7,
V
CC
NCNo internal connection.
Selects 5% (TOL connected to GND) or 10% (TOL connected to V
trip point tolerance.
Active HIGH reset output. RESET is active:
1. If V
2. If PBRST
3. If ST
4. During power-up.
Active LOW reset output. (See RESET).
Strobe input.
5V power.
falls below the reset voltage trip point.
CC
is LOW.
is not strobed LOW before the timeout period set by TD expires.
5V µP Power Supply Monitor and Reset Circuit
)
CC
2 of 10
Notice: The information in this document is subject to change without notice
Page 3
January 2005
rev 1.5
ASM1232LP/LPS
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or
microcontroller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
RESET and RESET
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to RESET
RESET
drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is
required to connect with the output.
Trip Point Tolerance Selection
The TOL input is used to determine the level V
below 5V without asserting a reset. With TOL conected to
VCC, RESET and RESET become active whenever VCC falls
below 4.5V. RESET and RESET
VCC falls below 4.75V if TOL is connected to ground.
is an active LOW signal. It is developed with an open
outputs
can vary
CC
become active when the
t
R
V
(MAX)
CCTP
V
V
CCTP
CCTP
t
RPU
(MIN)
RESET
V
OH
V
OL
RESET
(MIN)
V
CCTP
V
CC
.
Figure 1: Timing Diagram : Power Up
V
CC
V
CCTP
(MAX)
V
CCTP
~
~
~
~
~
~
t
F
After V
and RESET remain active for a minimum time period of
250ms. On power-down, once V
threshold RESET stays LOW and is guaranteed to be 0.4V or
less until V
is valid down to a VCC level of 1.2V also.
has risen above the trip point set by TOL, RESET
CC
falls below the reset
CC
drops below 1.2V. The active HIGH reset signal
CC
TRIP Point Voltage
Tolerance
Select
TOL = V
TOL = GND5%4.54.624.74
CC
Tolerance
MinNomMax
10%4.254.374.49
(V)
~
RESET
RESET
Figure 2: Timing Diagram : Power Down
t
RPD
V
OH
V
OL
~
~
~
~
~
Application Information
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override
the internal trip point detection circuits and issue reset
signals. The pushbutton input is debounced and is pulled
HIGH through an internal 40kΩ resistor.
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
3 of 10
Page 4
January 2005
rev 1.5
ASM1232LP/LPS
When PBRST is held LOW for the minimum time tPB, both
resets become active and remain active for a minimum time
period of 250ms after PBRST
The debounced input is guaranteed to recognize pulses
greater than 20ms. No external pull-up resistor is required,
since PBRST
The PBRST
shorted to ground with a mechanical switch.
is pulled HIGH by an internal 40kΩ resistor.
can be driven from a TTL or CMOS logic line or
PBRST
t
PDLY
V
IL
RESET
RESET
returns HIGH.
t
PB
~
~
~
~
~
~
t
V
RST
IH
V
OH
V
OL
power-up after the supply voltage returns to an in-tolerance
condition, the reset signal remains active for 250ms
minimum, allowing the power supply and system
microprocessor to stabilize. ST
be detected.
Valid
Strobe
ST
t
RST
~
~
RESET
Note: ST is ignored whenever a reset is active
pulses as short as 20ns can
Valid
Strobe
t
ST
tTD (min)
(max)
t
TD
Invalid
Strobe
Figure 5: Timing Diagram: Strobe Input
Timeouts periods of approximately 150ms, 610ms or
1,200ms are selected through the TD pin.
TD Voltage level
Watchdog Time-out Period
(ms)
Figure 3: Timing Diagram: Pushbutton Reset
5V
ASM1232LP/LPS
1
PBRST
2
TD
3
TOL
4
GND
Figure 4: Application Circuit: Pushbutton Reset
V
CC
ST
RESET
RESET
8
7
6
5
I/O
µP
RESET
Watchdog Timer and ST
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. The µP must toggle the ST
period (as selectable through TD input) to verify proper
software execution. If the ST
minimum timeout period, reset signals become active. In
Input
input within a set
is not toggled low within the
MinNomMax
GND62.5150250
Floating2506101000
V
CC
The watchdog timer can not be disabled. It must be strobed
with a high-to-low transition to avoid watchdog timeout and
reset.
ASM1232 LP/LPS
1
PBRST
2
T
3
TOL
4
GND
Figure 6: Application Circuit: Watchdog Timer
V
CC
D
ST
RESET
50012002000
5V
8
7
10kΩ
µP
6
5
RESET
MREQ
Decoder
Address
Bus
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
4 of 10
Page 5
January 2005
rev 1.5
Absolute Maximum Ratings
ParameterMinMaxUnit
ASM1232LP/LPS
Voltage on V
Voltage on ST
Voltage on PBRST
Operating Temperature Range (N suffixed devices)-40+85°C
Operating Temperature Range (others)070°C
Soldering Temperature (for 10 sec)+260°C
Storage Temperature-55+125°C
ESD rating
Note:
1. Voltages are measured with respect to ground
2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
CC
, TD-0.5
, RESET, RESET-0.5
HBM
MM
-0.57V
+ 0.5
V
CC
+ 0.5
V
CC
2
200
KV
V
V
V
DC Electrical Characteristics
Unless otherwise stated, 4.5V <= VCC<= 5.5V and over the operating temperature range of 0°C to 70°C (-40°C to +85°C. for N devices). All
voltages are referenced to ground.
ParameterSymbolConditionsMinTypMaxUnit
V
CC
V
IH
V
IL
CCTP
CCTP
t
TD
t
TD
t
TD
V
OH
I
OH
I
OL
Supply Voltage
ST
and PBRST Input High Level
ST and PBRST Input Low Level
V
Trip Point (TOL = GND)V
CC
V
Trip Point (TOL = VCC)V
CC
Watchdog Timeout Period
Watchdog Timeout Period
Watchdog Timeout Period
Output Voltage
Output Current
Output Current
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
4.55.5V
+ 0.3
2
-0.30.8V
4.504.624.74V
4.254.374.49V
TD = GND
TD = VCC
TD Floating
I=-500µA, Note 3
Output = 2.4V, Note 2-8-10mA
Output = 0.4V10mA
62.5150250ms
50012002000ms
2506101000ms
V
- 0.5VCC - 0.1
CC
V
CC
V
V
5 of 10
Page 6
January 2005
rev 1.5
ParameterSymbolConditionsMinTypMaxUnit
ASM1232LP/LPS
Input Leakage
RESET Low Level
Internal Pull-up ResistorNote 140kΩ
Operating Current (CMOS)
Input Capacitance
Output Capacitance
PBRST Manual Reset
Minimum Low Time
Reset Active Time
ST
Pulse Width
VCC Fail Detect to RESET or
RESET
Slew Ratet
V
CC
PBRST Stable LOW to RESET and
RESET
Active
V
Detect to RESET or RESET
CC
inactive
VCC Slew Ratet
I
V
I
CC1
C
C
OUT
t
t
RST
t
t
RPD
t
PDLY
t
RPU
IL
OL
PB
ST
F
R
Note 1-1.01.0µA
Note 30.4V
30µA
IN
PBRST = V
Note 420ns
4.75V to 4.25V300µs
t
RISE
4.25V to 4.75V0ns
IL
= 5µs
20ms
2506101000ms
58µs
2506101000ms
5pF
10pF
20ms
Notes
1. PBRST
2. RESET
3. RESET remains within 0.5V of V
falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (t
is internally pulled HIGH to VCC through a nominal 40kΩ resistor.
is an open drain output.
on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until V
CC
5V µP Power Supply Monitor and Reset Circuit
). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.
TD
CC
6 of 10
Notice: The information in this document is subject to change without notice
Page 7
January 2005
C
rev 1.5
Package Information
ASM1232LP/LPS
MicroSO (8-Pin)
SO (8-Pin)
D
A2
e
B
A1
Plastic DIP (8-Pin)
InchesMillimeteres
MinMaxMinMax
MicroSO (8-Pin)
A0.0320.0440.811.10
A10.0020.0060.050.15
A20.0300.0380.760.97
b0.012 BSC0.30 BSC
C0.0040.0080.100.20
D0.1140.1222.903.10
e0.0256 BSC0.65 BSC
E0.1840.2004.675.08
E10.1140.1222.903.10
L0.0160.0260.410.66
S0.0206 BSC0.52 BSC
a0°6°0°6°
SO (8-Pin)
A0.0530.0691.351.75
A10.0040.0100.100.25
A20.0490.0591.251.50
H
E
A
θ
D
L
B0.0120.0200.310.51
C0.0070.0100.180.25
D0.193 BSC4.90 BSC
E0.154 BSC3.91 BSC
e0.050 BSC1.27 BSC
H0.236 BSC6.00 BSC
L0.0160.0500.411.27
θ0°8°0°8°
Plastic DIP (8-Pin)
A-0.210-5.33
A10.015-0.38-
A20.1150.1952.924.95
b0.0140.0220.360.56
b20.0450.0701.141.78
C0.0080.0140.200.36
D0.3550.4009.0210.16
E0.3000.3257.628.26
E10.2400.2806.107.11
e0.100 BSC2.54 BSC
eB-0.430-10.92
L0.1150.1502.923.81
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
7 of 10
Page 8
January 2005
C
rev 1.5
SO (16-Pin)
8
916
1
E
PIN 1 ID
H
ASM1232LP/LPS
D
A2
A
e
B
InchesMillimeter
MinMaxMinMax
A0.0530.0691.351.75
A10.0040.0100.100.25
A20.0490.0591.251.50
B0.0130.0220.330.53
C0.0080.0120.190.27
D0.3860.3949.8010.01
E0.1500.1573.804.00
A1
SO (16-Pin)*
D
0.004
Seating Plane
θ
h
L
e0.050 BSC1.27 BSC
H0.2280.2445.806.20
h0.0100.0160.250.41
L0.0160.0350.400.89
θ0°8°0°8°
* JEDEC Drawing MS-013AA
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
8 of 10
Page 9
January 2005
rev 1.5
Ordering Information
ASM1232LP/LPS
Operating
Part NumberPackage
TIN-LEAD DEVICES
ASM1232LP8L PDIP0°C to +70°C305VASM1232LP
ASM1232LPN8L PDIP-40° C to +85°C305VASM1232LPN
ASM1232LPS16L SOIC0°C to +70°C305VASM1232LPS
ASM1232LPS-28L SOIC0°C to +70° C305VASM1232LPS-2
ASM1232LPSN16L SOIC-40°C to +85°C305VASM1232LPSN
ASM1232LPSN-28L SOIC-40°C to +85°C305VASM1232LPSN-2
ASM1232LPU8L MSOP0°C to +70°C305VASM1232LP
ASM1232LPUN8L MSOP-40°C to +85°C305VASM1232LPN
LEAD FREE DEVICES
ASM1232LPF8L PDIP0°C to +70°C305VASM1232LPF
ASM1232LPNF8L PDIP-40°C to +85°C305VASM1232LPNF
ASM1232LPS-2F8L SOIC0°C to +70°C305VASM1232LPS-2F
Temperature
Range
Maximum
Supply
Current (µA)
Vol tag e
Monitoring
Application
Package Marking
ASM1232LPSF16L SOIC0°C to +70°C305VASM1232LPSF
ASM1232LPSN-2F8L SOIC-40°C to +85°C305VASM1232LPSN-2F
ASM1232LPSNF16L SOIC-40°C to +85°C305VASM1232LPSNF
ASM1232LPUF8L MSOP0°C to +70°C305VASM1232LPF
ASM1232LPUNF8L MSOP-40°C to +85°C305VASM1232LPNF
5V µP Power Supply Monitor and Reset Circuit
9 of 10
Notice: The information in this document is subject to change without notice