Datasheet ASM1232LP, ASM1232LPS Datasheet (Alliance Semiconductor)

Download

Page 1

查询ASM1232LP供应商

January 2005

rev 1.5

5V µP Power Supply Monitor and Reset Circuit

General Description

The ASM1232LP/LPS is a fully integrated microprocessor

supervisor. It can halt and restart a “hung-up” microprocessor,

restart a microprocessor after a power failure. It has a

watchdog timer and external reset override.

A precision temperature-compensated reference and

comparator circuits monitor the 5V, V

During power-up or when the VCC power supply falls outside

selectable tolerance limits, both RESET and RESET become

active. When V

signals remain active for an additional 250ms minimum,

allowing the power supply and system microprocessor to

stabilize. The trip point tolerance signal, TOL, selects the trip

level tolerance to be either 5% or 10%.

rises above the threshold voltage, the reset

input voltage status.

ASM1232LP/LPS

• Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin

DIP and 8-pin Micro SO packages

• Wide operating temperature -40°C to +85°C (N suffixed

devices)

Applications

• Microprocessor Systems

• Computers

• Controllers

• Portable Equipment

• Intelligent Instuments

• Automotive Systems

Typical Operating Circuit

Each device has both a push-pull, active HIGH reset output

and an open drain active LOW reset output. A debounced

manual reset input, PBRST

minimum period of 250ms.

There is a watchdog timer to stop and restart a microprocessor

that is “hung-up”. The watchdog timeouts periods are

selectable: 150ms, 610ms and 1200ms. If the ST input is not

strobed LOW before the time-out period expires, a reset is

generated.

Devices are available in 8-pin DIP, 16-pin SO and compact 8-

pin MicroSO packages.

, activates the reset outputs for a

Key Features

• 5V supply monitor

• Selectable watchdog period

• Debounce manual push-button reset input

• Precision temperature-compensated voltage reference

and comparator.

• Power-up, power-down and brown out detection

• 250ms minimum reset time

• Active LOW open drain reset output and active HIGH

push-pull output

• Selectable trip point tolerance: 5% or 10%

Block Diagram

TOL

PBRST

ASM1232LP/LPS

Tolerance Selection

Reference

Push Button

Debounce

Voltage Sense

Comparators

Watchdog Transition

Detector

40kΩ

GND

RESET

TOL

+5V

10kΩ

I/O

RESET

ASM1232LP/LPS

Reset &

Watchdog Timer

µP

RESET

Alliance Semiconductor

2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com

Notice: The information in this document is subject to change without notice

GND

Page 2

January 2005

rev 1.5

Pin Configuration

ASM1232LP/LPS

PBRST

Pin Description

Pin #

8-Pin Package

1 2 PBRST Debounced manual pushbutton RESET input.

24TD

DIP/SO/MicroSO

TOL

GND

ASM1232LPU

16-Pin Package

ASM1232LP

ASM1232LPS-2

Pin #

Name

RESET

TOL

GND

ASM1232LPS

Function

= 150ms for TD = GND, tTD = 610ms

PBRST

Watchdog time delay selection. (t

for TD=Open, and tTD = 1200ms for TD = VCC).

RESET

36TOL

4 8 GND Ground.

5 9 RESET

6 11 RESET

713ST

815

10,12,14,16

1,3,5,7,

NC No internal connection.

Selects 5% (TOL connected to GND) or 10% (TOL connected to V

trip point tolerance.

Active HIGH reset output. RESET is active:

1. If V

2. If PBRST

3. If ST

4. During power-up.

Active LOW reset output. (See RESET).

Strobe input.

5V power.

falls below the reset voltage trip point.

is LOW.

is not strobed LOW before the timeout period set by TD expires.

5V µP Power Supply Monitor and Reset Circuit

)

2 of 10

Notice: The information in this document is subject to change without notice

Page 3

January 2005

rev 1.5

ASM1232LP/LPS

Detailed Description

The ASM1232LP/LPS monitors the microprocessor or

microcontroller power supply and generates reset signal,

both active HIGH and Active LOW, that halt processor

operation whenever the power supply voltage levels are

outside a predetermined tolerance.

RESET and RESET

RESET is an active HIGH signal developed by a CMOS

push-pull output stage and is the logical opposite to RESET

RESET

drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is

required to connect with the output.

Trip Point Tolerance Selection

The TOL input is used to determine the level V

below 5V without asserting a reset. With TOL conected to

VCC, RESET and RESET become active whenever VCC falls

below 4.5V. RESET and RESET

VCC falls below 4.75V if TOL is connected to ground.

is an active LOW signal. It is developed with an open

outputs

can vary

become active when the

(MAX)

CCTP

RPU

(MIN)

RESET

(MIN)

CCTP

Figure 1: Timing Diagram : Power Up

CCTP

(MAX)

CCTP

After V

and RESET remain active for a minimum time period of

250ms. On power-down, once V

threshold RESET stays LOW and is guaranteed to be 0.4V or

less until V

is valid down to a VCC level of 1.2V also.

has risen above the trip point set by TOL, RESET

falls below the reset

drops below 1.2V. The active HIGH reset signal

TRIP Point Voltage

Tolerance

Select

TOL = V

TOL = GND 5% 4.5 4.62 4.74

Tolerance

Min Nom Max

10% 4.25 4.37 4.49

(V)

RESET

Figure 2: Timing Diagram : Power Down

RPD

Application Information

Manual Reset Operation

Push-button switch input, PBRST, allows the user to override

the internal trip point detection circuits and issue reset

signals. The pushbutton input is debounced and is pulled

HIGH through an internal 40kΩ resistor.

5V µP Power Supply Monitor and Reset Circuit

Notice: The information in this document is subject to change without notice

3 of 10

Page 4

January 2005

rev 1.5

ASM1232LP/LPS

When PBRST is held LOW for the minimum time tPB, both

resets become active and remain active for a minimum time

period of 250ms after PBRST

The debounced input is guaranteed to recognize pulses

greater than 20ms. No external pull-up resistor is required,

since PBRST

The PBRST

shorted to ground with a mechanical switch.

is pulled HIGH by an internal 40kΩ resistor.

can be driven from a TTL or CMOS logic line or

PBRST

PDLY

RESET

returns HIGH.

RST

power-up after the supply voltage returns to an in-tolerance

condition, the reset signal remains active for 250ms

minimum, allowing the power supply and system

microprocessor to stabilize. ST

be detected.

Valid Strobe

RST

RESET

Note: ST is ignored whenever a reset is active

pulses as short as 20ns can

Valid Strobe

tTD (min)

(max)

Invalid Strobe

Figure 5: Timing Diagram: Strobe Input

Timeouts periods of approximately 150ms, 610ms or

1,200ms are selected through the TD pin.

TD Voltage level

Watchdog Time-out Period

(ms)

Figure 3: Timing Diagram: Pushbutton Reset

ASM1232LP/LPS

PBRST

TOL

GND

Figure 4: Application Circuit: Pushbutton Reset

RESET

I/O

µP

RESET

Watchdog Timer and ST

A watchdog timer stops and restarts a microprocessor that is

“hung-up”. The µP must toggle the ST

period (as selectable through TD input) to verify proper

software execution. If the ST

minimum timeout period, reset signals become active. In

Input

input within a set

is not toggled low within the

Min Nom Max

GND 62.5 150 250

Floating 250 610 1000

The watchdog timer can not be disabled. It must be strobed

with a high-to-low transition to avoid watchdog timeout and

reset.

ASM1232 LP/LPS

PBRST

TOL

GND

Figure 6: Application Circuit: Watchdog Timer

RESET

500 1200 2000

10kΩ

µP

RESET

MREQ

Decoder

Address

Bus

5V µP Power Supply Monitor and Reset Circuit

Notice: The information in this document is subject to change without notice

4 of 10

Page 5

January 2005

rev 1.5

Absolute Maximum Ratings

Parameter Min Max Unit

ASM1232LP/LPS

Voltage on V

Voltage on ST

Voltage on PBRST

Operating Temperature Range (N suffixed devices) -40 +85 °C

Operating Temperature Range (others) 0 70 °C

Soldering Temperature (for 10 sec) +260 °C

Storage Temperature -55 +125 °C

ESD rating

Note:

1. Voltages are measured with respect to ground

2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

, TD -0.5

, RESET, RESET -0.5

HBM

-0.5 7 V

+ 0.5

200

DC Electrical Characteristics

Unless otherwise stated, 4.5V <= VCC<= 5.5V and over the operating temperature range of 0°C to 70°C (-40°C to +85°C. for N devices). All voltages are referenced to ground.

Parameter Symbol Conditions Min Typ Max Unit

CCTP

Supply Voltage

and PBRST Input High Level

ST and PBRST Input Low Level

Trip Point (TOL = GND) V

Trip Point (TOL = VCC)V

Watchdog Timeout Period

Output Voltage

Output Current

5V µP Power Supply Monitor and Reset Circuit

Notice: The information in this document is subject to change without notice

4.5 5.5 V

+ 0.3

-0.3 0.8 V

4.50 4.62 4.74 V

4.25 4.37 4.49 V

TD = GND

TD = VCC

TD Floating

I=-500µA, Note 3

Output = 2.4V, Note 2 -8 -10 mA

Output = 0.4V 10 mA

62.5 150 250 ms

500 1200 2000 ms

250 610 1000 ms

- 0.5 VCC - 0.1

5 of 10

Page 6

January 2005

rev 1.5

Parameter Symbol Conditions Min Typ Max Unit

ASM1232LP/LPS

Input Leakage

RESET Low Level

Internal Pull-up Resistor Note 1 40 kΩ

Operating Current (CMOS)

Input Capacitance

Output Capacitance

PBRST Manual Reset Minimum Low Time

Reset Active Time

Pulse Width

VCC Fail Detect to RESET or

RESET

Slew Rate t

PBRST Stable LOW to RESET and RESET

Active

Detect to RESET or RESET

inactive

VCC Slew Rate t

CC1

OUT

RST

RPD

PDLY

RPU

Note 1 -1.0 1.0 µA

Note 3 0.4 V

30 µA

PBRST = V

Note 4 20 ns

4.75V to 4.25V 300 µs

RISE

4.25V to 4.75V 0 ns

= 5µs

20 ms

250 610 1000 ms

58µs

250 610 1000 ms

5pF

10 pF

20 ms

Notes

1. PBRST

2. RESET

3. RESET remains within 0.5V of V falls below 2.0V.

4. Must not exceed the minimum watchdog time-out period (t

is internally pulled HIGH to VCC through a nominal 40kΩ resistor. is an open drain output.

on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until V

5V µP Power Supply Monitor and Reset Circuit

). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.

6 of 10

Notice: The information in this document is subject to change without notice

Page 7

January 2005

rev 1.5

Package Information

ASM1232LP/LPS

MicroSO (8-Pin)

SO (8-Pin)

Plastic DIP (8-Pin)

Inches Millimeteres

Min Max Min Max

MicroSO (8-Pin)

A 0.032 0.044 0.81 1.10

A1 0.002 0.006 0.05 0.15

A2 0.030 0.038 0.76 0.97

b 0.012 BSC 0.30 BSC

C 0.004 0.008 0.10 0.20

D 0.114 0.122 2.90 3.10

e 0.0256 BSC 0.65 BSC

E 0.184 0.200 4.67 5.08

E1 0.114 0.122 2.90 3.10

L 0.016 0.026 0.41 0.66

S 0.0206 BSC 0.52 BSC

a0°6°0°6°

SO (8-Pin)

A 0.053 0.069 1.35 1.75

A1 0.004 0.010 0.10 0.25

A2 0.049 0.059 1.25 1.50

B 0.012 0.020 0.31 0.51

C 0.007 0.010 0.18 0.25

D 0.193 BSC 4.90 BSC

E 0.154 BSC 3.91 BSC

e 0.050 BSC 1.27 BSC

H 0.236 BSC 6.00 BSC

L 0.016 0.050 0.41 1.27

θ 0° 8° 0° 8°

Plastic DIP (8-Pin)

A - 0.210 - 5.33

A1 0.015 - 0.38 -

A2 0.115 0.195 2.92 4.95

b 0.014 0.022 0.36 0.56

b2 0.045 0.070 1.14 1.78

C 0.008 0.014 0.20 0.36

D 0.355 0.400 9.02 10.16

E 0.300 0.325 7.62 8.26

E1 0.240 0.280 6.10 7.11

e 0.100 BSC 2.54 BSC

eB - 0.430 - 10.92

L 0.115 0.150 2.92 3.81

5V µP Power Supply Monitor and Reset Circuit

Notice: The information in this document is subject to change without notice

7 of 10

Page 8

January 2005

rev 1.5

SO (16-Pin)

916

PIN 1 ID

ASM1232LP/LPS

Inches Millimeter

Min Max Min Max

A 0.053 0.069 1.35 1.75

A1 0.004 0.010 0.10 0.25

A2 0.049 0.059 1.25 1.50

B 0.013 0.022 0.33 0.53

C 0.008 0.012 0.19 0.27

D 0.386 0.394 9.80 10.01

E 0.150 0.157 3.80 4.00

SO (16-Pin)*

0.004

Seating Plane

e 0.050 BSC 1.27 BSC

H 0.228 0.244 5.80 6.20

h 0.010 0.016 0.25 0.41

L 0.016 0.035 0.40 0.89

θ 0° 8° 0° 8°

* JEDEC Drawing MS-013AA

5V µP Power Supply Monitor and Reset Circuit

Notice: The information in this document is subject to change without notice

8 of 10

Page 9

January 2005

rev 1.5

Ordering Information

ASM1232LP/LPS

Operating

Part Number Package

TIN-LEAD DEVICES

ASM1232LP 8L PDIP 0°C to +70°C 30 5V ASM1232LP

ASM1232LPN 8L PDIP -40° C to +85°C 30 5V ASM1232LPN

ASM1232LPS 16L SOIC 0°C to +70°C 30 5V ASM1232LPS

ASM1232LPS-2 8L SOIC 0°C to +70° C 30 5V ASM1232LPS-2

ASM1232LPSN 16L SOIC -40°C to +85°C 30 5V ASM1232LPSN

ASM1232LPSN-2 8L SOIC -40°C to +85°C 30 5V ASM1232LPSN-2

ASM1232LPU 8L MSOP 0°C to +70°C 30 5V ASM1232LP

ASM1232LPUN 8L MSOP -40°C to +85°C 30 5V ASM1232LPN

LEAD FREE DEVICES

ASM1232LPF 8L PDIP 0°C to +70°C 30 5V ASM1232LPF

ASM1232LPNF 8L PDIP -40°C to +85°C 30 5V ASM1232LPNF

ASM1232LPS-2F 8L SOIC 0°C to +70°C 30 5V ASM1232LPS-2F

Temperature

Range

Maximum

Supply

Current (µA)

Vol tag e

Monitoring

Application

Package Marking

ASM1232LPSF 16L SOIC 0°C to +70°C 30 5V ASM1232LPSF

ASM1232LPSN-2F 8L SOIC -40°C to +85°C 30 5V ASM1232LPSN-2F

ASM1232LPSNF 16L SOIC -40°C to +85°C 30 5V ASM1232LPSNF

ASM1232LPUF 8L MSOP 0°C to +70°C 30 5V ASM1232LPF

ASM1232LPUNF 8L MSOP -40°C to +85°C 30 5V ASM1232LPNF

5V µP Power Supply Monitor and Reset Circuit

9 of 10

Notice: The information in this document is subject to change without notice

Page 10

ASM1232LP/LPS

Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com

© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.