Datasheet ASM0912CB Datasheet (APLUS)

PLUS MAKE YOUR PRODUCTION A-PLUS

A

ASM0912CB

DATA SHEET

PLUS INTEGRATED CIRCUITS INC.

A

Address:

3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,

Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.

TEL: [phone]

FAX: [phone]

WEBSITE : http: //www.aplusinc.com.tw

Sales E-mail: Mr. Jason

[e-mail]

Technology E-mail: Mr. George

[e-mail]

ASM0912CB – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

ASM0912CB

1.0 General Description

The ASM0912CB is very low cost voice synthesizer with 4-bit microprocessor. It has various

features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog

timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS

technology and halt function can minimize power dissipation. Its architecture is similar to RISC,

with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,

except for program branches and data table read instructions (which need two instruction

cycles).

1.1 Feature



Single power supply can operate from 2.4V through 5V



Internal Program ROM: 4K x 10-bit



1 sets of 16-bit DPR can access up to 32K x 10 bits data memory space



Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh



I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)



On-chip clock generator: Resistive Clock Drive(RM)



Timer: 1

• Timer0: a 9-bit auto-reload timer/counter



Stack: 2-level subroutine nesting



HALT and Release from HALT function to reduce power consumption



Watch Dog Timer (WDT)



Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles



Number of instruction: 22



The Voice function can be implemented by microprocessor instruction

• One 8-bit COUT output for ASMxxxxx

1

Rev 1.0

FIGURE 1.1 : Block Diagram of ASM0912CB

(12)

]

)

)

ASM0912CB

(ADDR[14:12])

=0000b

COUT

PCLATCH(8)

PCH(8)

DPR3,2,1

DLATCH(10)

Data Bus[3:0

ALU(4)

Register(4)

One-Channel

( Voice synthesizer )

COUT

PCL(4)

PC[11:0]

ADDR[14:0]

DPR[14:0]

Accumlator(4

enter test mode

Data Bus[3:0]

ROM_Data[9:0]

Immediate(4

P1,P2,P3,P4

Reset Chip

Reset Chip

Stack

(2-Level)

ROM_ADDR[14:0]

Program

(Data)

ROM

SRAM

(96 x 4)

00h-1Fh
40h-7Fh

Clock Generator

Tes t s el ect

Power on Reset

RESET pin

Instruction Bus [9:0]

ROM Latch

Instruction

Instruction Bus [9:0]

Instruction

Decoder

Control Signal

VDD/GND

PRA0

OSC

Timer0(9)

Latch

PRASL(4)

Instruction Bus [9:0]

PRA(4)
PRB(4)
PRC(4)

weak or strong
pull-low for PRA,

PRB, PRC

2

Rev 1.0

FIGURE 1.2 : External ROM Map of ASM0912CB

g

ASM0912CBASM0912CBASM0912CB

00000h-07FFFh

ram and data ROM

Pro

PC[11:0]

12bit x 2 STACK

15-bit Data Pointer

Reserved for Testing

Reset Vector

00000h

00080h

00080h-003FFh

00400h

00FFFh(4K)

00000h-00FFFh

Data ROM

07FFFh(32Kx10-bits)

3

Rev 1.0

1.2 Pin-Out

ASM0912CB

ASM0912CB Pin-Out

PRC1

PRC0/RESET

PRA3-1

PRA0/RESET

OSC
VDD1
COUT
GND1
GND2
TEST
VDD2
PRB0-3
PRC2-3

I STI

Std./O.D.

I STI

Std./O.D.

I/O STI

Std./O.D.

I/O

I - RM mode Oscillator input
I

O - Current Output of Audio

I
I - Second Circuit Ground Potential

O - Enter Test Mode. ( TEST = High )

I - Second Power supply during operation

O Std./O.D. Output type with standard or Open-Drain output

I STI

Std./O.D.

Std./O.D.

STI

-

-

Input port with programmable strong pull-low or weak pull-low or
fix-input-floating capability
Input port with programmable strong pull-low or weak pull-low or
fix-input-floating capability

Mask option selected as an external RESET pin with weak pull-low
capability

I/O port with programmable strong pull-low or weak pull-low or
fix-input-floating capability
Output type with standard or Open-Drain output
I/O port with programmable strong pull-low or weak pull-low or
fix-input-floating capability
Output type with standard or Open-Drain output

Mask option selected as an external RESET pin with weak pull-low
capability

First Power supply during operation

First Circuit Ground Potential

Input port with programmable strong pull-low or weak pull-low or
fix-input-floating capability

1.3 Application circuit

4

Rev 1.0

ASM0912CBASM0912CB

X= 1540+80 (um)

Y=1510+80 (um)

1.4 Bonding Diagram

19 18 17 16 15 14 13 12

RC3 RC2 RC1 RC0 GND2 VDD2 TEST OSC

RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 RB3

1 2 3 4 5 6 7 8 9 10 11

( 32K x 10-bit ) Block ROM

ASM0912CB

Substrate must be connected to GND.

ASM0912CB Pad Location Chip Size: X= 1540+80 (um), Y=1510+80 (um)
PAD # PAD Name X Y PAD # PAD Name X Y

1 RA3 -682.16 -638.92 11 RB3 674.88 -638.92
2 RA2 -559.84 -638.92 12 OSC 633.56 670.24
3 RA1 -437.52 -638.92 13 TEST 432.48 670.24
4 RA0 -315.2 -638.92 14 VDD2 273.16 670.24
5 VDD1 -191.28 -638.92 15 GND2 134.68 670.24
6 COUT 71.12 -638.92 16 RC0 -51.76 670.24
7 GND1 189.52 -638.92 17 RC1 -248.4 670.24
8 RB0 307.92 -638.92 18 RC2 -454.24 670.24
9 RB1 430.24 -638.92 19 RC3 -650.88 670.24

10 RB2 552.56 -638.92

5

Rev 1.0

ASM0912CB

1.5 DC Characteristics for ASMxxxxx

SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION

VDD OPERATING VOLTAGE 2.4 3 5.0 V depending on Freq.

Isb STANDBY

Iop

Iih

Ioh OUTPUT HIGH CURRENT

Iol OUTPUT LOW CURRENT

Cout

dF/F

dF/F Fosc VARIATION -20 20 %

SUPPLY

CURRENT

INPUT CURRENT

/Internal pull low

DA CURRENT OUT

(FULL SCALE)

FREQUENCY

OPERATING

STABILITY

3 1
5 1
3 2
5 7
3 3
5 9

5 -5.2

3 -3
5 -8
3 7
5 20
3 4
5 5.2

-10 10 %

uA

mA

uA

mA

in HALT Mode

in HALT Mode

(IO Ports with weak

pull-high pull-low)

Fosc(3v- 2.4v)

Rosc=200k, 4MHz

4MHz, RM

4MHz, RM

IO Floating

4MHz, RM

4MHz, RM

(IO ports)

Fosc (3v)
VDD=3V,

FIGURE 1.3 : Frequency Range for Rosc in RM mode

Resistor(k ohm) 300 200 130 100

3v Freq.(MHz) 2.7 4.1 6.7 8.0

Rosc & Freq.

10

8

6

4

8

6.7

4.1

Freq. MHz

2

0

0 100 200 300 400

Rosc k ohm

2.7

6

Rev 1.0